I had some difficulties getting the TX_COOMPLETE interrupt to work. Here is an excerpt from my test code.

can.enable_interrupt_line(InterruptLine::_0, true);
can.enable_interrupts(Interrupts::RX_FIFO0_NEW_MSG | Interrupts::TX_COMPLETE);
unsafe {
    cp.NVIC.set_priority(interrupt::FDCAN1_IT0, 1);
    NVIC::unmask(interrupt::FDCAN1_IT0);
}

If I now send and receive CAN bus datagrams, RX_FIFO0_NEW_MSG is triggered, but not TX_COMPLETE.

After the following lines have been inserted, the TX_COMPLETE Intterupt is triggered on the STM32H743 system, as expected. However, this is certainly not the intended path.

unsafe {
    // FDCAN_TXBTIE Tx buffer transmission interrupt enable register
    core::ptr::write_volatile(0x4000a0e0 as *mut u32, 0xffff_ffff);
}

Have I overlooked something, or is there a mistake here?