Unprivileged Load Store

[BugraEryilmaz]

Description
Unprivileged load and store instructions (LDTR and STTR) are decoded properly, but they cause pagefult in Flexus because the memory hierarchy does not take into account that those instructions should use different page table base addresses.

Steps to Reproduce
Run data caching image with 2 cores
After some time, there will be LDTR and STTR instructions that cause a pagefult although they shouldn't.
Expected Behavior
There should be no pageful.

Actual Behavior
Those instructions cause a page fault and resynchronize.

[BugraEryilmaz]

Actually, after further inspection, the memory hierarchy was working properly. It was not using the exception level to determine which page table base address to use but it was using the virtual address range to determine it.

However, the problem was with QEMU side translation check. Because QEMU is not aware of the different page table base address needed to use for that translation, the check was causing page fault. Modified the QEMU interface so that it gets unprivileged flag as a parameter while doing the translation and uses the correct page table base address and stuff. Fix: 2878fa0 and also modification to libqflex: parsa-epfl/libqflex@29383f3