System Registers - The Movie: The Return II

[BugraEryilmaz]

(I could not write additional posts on the system registers issue, so I created a new cart)
Description
The SCTLR_EL system register is not one of the supported registers, but some other system registers (DCZID_EL0) depend on its internal value, which is never initialized or updated.

Steps to Reproduce
Run data caching image with 2 cores
Most msr xt, DCZID_EL0 will not cause any issue
After some time, the value of SCTLR_EL0 will change and cause a value mismatch for DCZID_EL0 between QEMU and Flexus
Expected Behavior
QEMU and flexus should agree on the value.

Actual Behavior
it will cause a value mismatch for DCZID_EL0 between QEMU and Flexus

Fix: c0b4600

[BugraEryilmaz]

Description
NZCV flags are not updated properly at the resync time. Two problems, first pstate variable does not keep the NZCV flags anymore. Secondly, We should not extract these bits before updating the CC registers because it expects the flags to be at bits 28-31 not 0-3.

Steps to Reproduce
Run data caching image with 2 cores
After some time there will be such a sequence:
cmp xn, xm
black-box
... (instructions that do not modify flags)
b.ne label
and cause validation error for the next PC
Expected Behavior
QEMU and flexus should agree on the value.

Actual Behavior
it will cause validation error for the next PC

Fixes:

1. Remove extract32 function while updating the CC registers: 7b884a9
2. QEMU has an internal function that reassembles pstate using the flags and pstate itself, use it for the pstate read function in libqflex: parsa-epfl/libqflex@a866d2e