Memory decoding

[BugraEryilmaz]

Description
There are a couple problematic cases for memory decoding. Namely prefetch instruction with register offset and atomic load stores (ldxr)

Expected Behavior
Prefetch instruction should be decoded as nop and ldxr register should be decoded with blackbox as it is not implemented.

Actual Behavior
They are decoded as normal load store instructions.

[BugraEryilmaz]

Fix: c72dcb5

[BugraEryilmaz]

The LDTR instruction was not decoded properly. It is a normal load with a signed offset, so everything is already implemented for it; we just need to check the opcode to set the offset type properly. (same for STTR btw)
Fix: 8e416b4

Deep note: What is the purpose of this instruction? ARM manual says it allows higher exception levels to read lower exception level data. But a normal load cannot do that?