This repository contains Group 16's work for Lab 4, focused on creating a simplified RISC-V CPU.
| Name | Role |
|---|---|
| Liu Shenghong | Repository Manager |
| Flavio Gazzeta | Contributor |
| Michael Li | Contributor |
| Soon Yung | Contributor |
| Task | Shenghong (opnuub) | Flavio (FlavioGazzetta) | Michael (Happymic) | Soon Yung (so0nyung) |
|---|---|---|---|---|
| Program Counter () | S | |||
| ALU (ALU.sv) | S | M | ||
| Register File | S | |||
| Instruction Memory | S | |||
| Control Unit | ||||
| Sign Extend | ||||
| Testbench | S |
* S = Significant role
**M = Minor role
The commits done do not accurately mirror the workload. More often than not commits were done via a single computer while the rest were used for testing and writitng of code. This streamlining, while affecting the commits history, is compensated for by a comprehensive logbook + clear designation of workload.