Interrupt driven serial #201
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An earlier release of the original PR #145 was tested on some other CH32 chips:
These are related issues and PRs:
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Note: This PR replaces PR #145, which was accidentally closed after renaming the branch.
TLDR: support for interrupt driven serial and dual serial usage of Serial1 and Serial2.
This PR reintroduces a read buffer for reading Serial1 and Serial2 input using a hardware interrupt.
The read buffer allows for proper implementation of serial.available() and serial.peek().
It also prevents loosing serial input data received when the processor is doing something else.
This PR includes changes proposed in PR #180.
This PR was tested mainly on the CH32V003, CH32X033 and confirmed to also work on the CH32X035. Other processors may work as well, but have not been tested. The current implementation only supports the Serial1 and Serial2 interfaces.
The CH32X033 was used to test interrupt driven Serial1 and Serial2 as single interfaces and as dual interface. The X033/X035 have 4 x UART Serial, but the CH32X033F8P6 (in the TSSOP20 package) only has usable pins for Serial1 and Serial2 (RX1_1=PA11, TX1_1=PA10 / RX2=PA3, TX2=PA2).
Using Serial1 and/or Serial2 on CH32X033 requires the board definition added by PR #171.
To configure the number of instances enabled, change the definition in variant_CH32X933F8P.h.
That header file defines these constants:
SERIAL_UART_INSTANCES - the number of UART instances enabled (1 or 2 for CH32X033)
SERIAL_UART_INSTANCE - the UART instance selected for Serial (either 1 or 2 for CH32X033)
When SERIAL_UART_INSTANCES is 2, SERIAL_UART_INSTANCE is not defined and both Serial1 and Serial2 are available.