Consider interface to expose P2P capabilities

[npmiller]

Some devices have peer to peer capabilities for memory transfers and/or USM buffers, we may need to consider a way to expose this in the unified runtime.

There's currently an extension proposal in DPC++ to handle this, with some discussion on it:

• [SYCL][DOC] Initial commit of oneapi extension proposal for adding P2P intel/llvm#6104

It's currently only a SYCL level extension but I suspect implementing it would require some changes in PI or UR, so we should consider it.

[kbenzie]

@pbalcer @igchor @vinser52 another relevant topic for you, related to #53.

[kbenzie]

Add requirements for each adapter to a table on this issue to kick off the design process of a combined multi-device context and P2P proposal.

[jandres742]

related: this is what L0 has https://spec.oneapi.io/level-zero/latest/core/PROG.html#peer-to-peer-access-and-queries

[JackAKirk]

FYI I made a draft impl (https://github.com/intel/llvm/pull/8303) of Intel's sycl extension proposal for P2P USM: intel/llvm#6104. This is fully functional now for the cuda backend only, but should support HIP and L0 in the future using the same pi functions.
It introduces three new PI/UR functions: https://github.com/intel/llvm/pull/8303/files#diff-40b7cb921a961e9c240e665df7a099783d3d2896a3f973c90397ea031032c961R154

I'm pretty sure that these three functions will be required, although the naming is subject to change, particularly "piextCanAccessPeer".

[jandres742]

@kbenzie : what is the next step on this issue? are there any points to clarify?

[kbenzie]

I asked @JackAKirk to bring these changes over to UR here.

[kbenzie]

Added in #631