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[RISCV] Add processor definition for SpacemiT-X60 #94564

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Merged
merged 8 commits into from
Jun 18, 2024
Merged

[RISCV] Add processor definition for SpacemiT-X60 #94564

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363e293
[RISCV] Add processor definition for Spacemit-K1
sunshaoce Jun 6, 2024
4c1dccc
fixup! Update RISCVProcessors.td
sunshaoce Jun 6, 2024
620f8cc
fixup! Use name spacemit-x60
sunshaoce Jun 6, 2024
d0a6664
fixup! Add missing extensions
sunshaoce Jun 6, 2024
eb0d50d
fixup! Add svnapot ext
sunshaoce Jun 7, 2024
67a7d08
fixup! Adjust extensions info
sunshaoce Jun 11, 2024
4471092
fixup! Remove Zvfhmin
sunshaoce Jun 11, 2024
264bba2
fixup! Remove Zmmul
sunshaoce Jun 18, 2024
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57 changes: 57 additions & 0 deletions clang/test/Driver/riscv-cpus.c
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Original file line number Diff line number Diff line change
Expand Up @@ -31,6 +31,63 @@
// MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+zks" "-target-feature" "+zksed" "-target-feature" "+zksh" "-target-feature" "+svinval"
// MCPU-XIANGSHAN-NANHU-SAME: "-target-abi" "lp64d"

// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=spacemit-x60 | FileCheck -check-prefix=MCPU-SPACEMIT-X60 %s
// MCPU-SPACEMIT-X60: "-nostdsysteminc" "-target-cpu" "spacemit-x60"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+m"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+a"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+f"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+d"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+c"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+v"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zic64b"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicbom"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicbop"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicboz"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+ziccamoa"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+ziccif"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicclsm"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+ziccrse"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicntr"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicond"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicsr"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zifencei"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zihintpause"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zihpm"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zmmul"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+za64rs"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zfh"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zfhmin"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zba"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zbb"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zbc"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zbkc"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zbs"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zkt"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zve32f"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zve32x"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zve64d"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zve64f"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zve64x"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvfh"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvfhmin"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvkt"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvl128b"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvl256b"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvl32b"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvl64b"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+ssccptr"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+sscofpmf"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+sscounterenw"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+sstc"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+sstvala"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+sstvecd"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svade"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svbare"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svinval"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svnapot"
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svpbmt"
// MCPU-SPACEMIT-X60-SAME: "-target-abi" "lp64d"

// We cannot check much for -mcpu=native, but it should be replaced by a valid CPU string.
// RUN: %clang --target=riscv64 -### -c %s -mcpu=native 2> %t.err || true
// RUN: FileCheck --input-file=%t.err -check-prefix=MCPU-NATIVE %s
Expand Down
4 changes: 2 additions & 2 deletions clang/test/Misc/target-invalid-cpu-note.c
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Original file line number Diff line number Diff line change
Expand Up @@ -85,12 +85,12 @@

// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
// RISCV64: error: unknown target CPU 'not-a-cpu'
// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, veyron-v1, xiangshan-nanhu{{$}}

// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
// TUNE-RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max, generic, rocket, sifive-7-series{{$}}

// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
18 changes: 18 additions & 0 deletions llvm/lib/Target/RISCV/RISCVProcessors.td
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Expand Up @@ -381,3 +381,21 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
TuneZExtHFusion,
TuneZExtWFusion,
TuneShiftedZExtWFusion]>;

def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
NoSchedModel,
!listconcat(RVA22S64Features,
[FeatureStdExtV,
FeatureStdExtSscofpmf,
FeatureStdExtSstc,
FeatureStdExtSvnapot,
FeatureStdExtZbc,
FeatureStdExtZbkc,
FeatureStdExtZfh,
FeatureStdExtZicond,
FeatureStdExtZmmul,
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Please don't list Zmmul separate from M.

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Generated "-target-feature" "-zmmul" in clang/test/Driver/riscv-cpus.c.
It seems that M imply Zmmul is not supported yet.
#95070

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Generated "-target-feature" "-zmmul" in clang/test/Driver/riscv-cpus.c.
It seems that M imply Zmmul is not supported yet.
#95070

It's not, but what is the benefit to the user to have Zmmul and M both listed?

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Addressed. Thanks!

FeatureStdExtZvfh,
FeatureStdExtZvfhmin,
FeatureStdExtZvkt,
FeatureStdExtZvl256b]),
[TuneDLenFactor2]>;
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Does X60 support any macro-fusion?

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Since no specific information is publicly available, I think this patch can ignore macro-fusion for now