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GlobalISel: Fix defined register of invariant.start #125664

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Merged
arsenm merged 4 commits into from
Feb 4, 2025
Merged

GlobalISel: Fix defined register of invariant.start #125664

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839080f
GlobalISel: Fix defined register of invariant.start
ro-i Feb 4, 2025
d8bdb59
simplify promote-dependency-on-invariant-result.ll
ro-i Feb 4, 2025
eab32fb
simplify promote-dependency-on-invariant-result.ll further
ro-i Feb 4, 2025
885344e
add store again to promote-dependency-on-invariant-result.ll
ro-i Feb 4, 2025
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4 changes: 1 addition & 3 deletions llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2441,9 +2441,7 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
return true;
}
case Intrinsic::invariant_start: {
LLT PtrTy = getLLTForType(*CI.getArgOperand(0)->getType(), *DL);
Register Undef = MRI->createGenericVirtualRegister(PtrTy);
MIRBuilder.buildUndef(Undef);
MIRBuilder.buildUndef(getOrCreateVReg(CI));
return true;
}
case Intrinsic::invariant_end:
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
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Expand Up @@ -2262,7 +2262,7 @@ declare ptr @llvm.invariant.start.p0(i64, ptr nocapture) readonly nounwind
declare void @llvm.invariant.end.p0(ptr, i64, ptr nocapture) nounwind
define void @test_invariant_intrin() {
; CHECK-LABEL: name: test_invariant_intrin
; CHECK: %{{[0-9]+}}:_(s64) = G_IMPLICIT_DEF
; CHECK: %{{[0-9]+}}:_(p0) = G_IMPLICIT_DEF
; CHECK-NEXT: RET_ReallyLR
%x = alloca %t
%inv = call ptr @llvm.invariant.start.p0(i64 8, ptr %x)
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24 changes: 24 additions & 0 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/promote-dependency-on-invariant-result.ll
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@@ -0,0 +1,24 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -O0 -global-isel=true --stop-after=irtranslator -o - %s | FileCheck %s
target datalayout = "A5"

declare ptr @llvm.invariant.start.p5(i64 immarg, ptr addrspace(5) nocapture)
declare void @llvm.invariant.end.p5(ptr, i64 immarg, ptr addrspace(5) nocapture)

define amdgpu_kernel void @use_invariant_promotable_lds(ptr addrspace(5) %arg, i32 %i) {
; CHECK-LABEL: name: use_invariant_promotable_lds
; CHECK: bb.1.bb:
; CHECK-NEXT: liveins: $sgpr4_sgpr5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; CHECK-NEXT: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
; CHECK-NEXT: %13:_(p4) = nuw nusw G_PTR_ADD [[INT]], [[C]](s64)
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD %13(p4) :: (dereferenceable invariant load (p5) from %ir.arg.kernarg.offset, addrspace 4)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
; CHECK-NEXT: S_ENDPGM 0
bb:
%tmp = call ptr @llvm.invariant.start.p5(i64 4, ptr addrspace(5) %arg)
call void @llvm.invariant.end.p5(ptr %tmp, i64 4, ptr addrspace(5) %arg)
ret void
}