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GlobalISel: Fix defined register of invariant.start #125664

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Merged
arsenm merged 4 commits into from
Feb 4, 2025
Merged

GlobalISel: Fix defined register of invariant.start #125664

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839080f
GlobalISel: Fix defined register of invariant.start
ro-i Feb 4, 2025
d8bdb59
simplify promote-dependency-on-invariant-result.ll
ro-i Feb 4, 2025
eab32fb
simplify promote-dependency-on-invariant-result.ll further
ro-i Feb 4, 2025
885344e
add store again to promote-dependency-on-invariant-result.ll
ro-i Feb 4, 2025
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4 changes: 1 addition & 3 deletions llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2441,9 +2441,7 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
return true;
}
case Intrinsic::invariant_start: {
LLT PtrTy = getLLTForType(*CI.getArgOperand(0)->getType(), *DL);
Register Undef = MRI->createGenericVirtualRegister(PtrTy);
MIRBuilder.buildUndef(Undef);
MIRBuilder.buildUndef(getOrCreateVReg(CI));
return true;
}
case Intrinsic::invariant_end:
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
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Expand Up @@ -2262,7 +2262,7 @@ declare ptr @llvm.invariant.start.p0(i64, ptr nocapture) readonly nounwind
declare void @llvm.invariant.end.p0(ptr, i64, ptr nocapture) nounwind
define void @test_invariant_intrin() {
; CHECK-LABEL: name: test_invariant_intrin
; CHECK: %{{[0-9]+}}:_(s64) = G_IMPLICIT_DEF
; CHECK: %{{[0-9]+}}:_(p0) = G_IMPLICIT_DEF
; CHECK-NEXT: RET_ReallyLR
%x = alloca %t
%inv = call ptr @llvm.invariant.start.p0(i64 8, ptr %x)
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37 changes: 37 additions & 0 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/promote-dependency-on-invariant-result.ll
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@@ -0,0 +1,37 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -O0 -global-isel=true --stop-after=instruction-select --verify-machineinstrs -o - %s | FileCheck %s
target datalayout = "A5"

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare ptr @llvm.invariant.start.p5(i64 immarg, ptr addrspace(5) nocapture) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.invariant.end.p5(ptr, i64 immarg, ptr addrspace(5) nocapture) #0

; Function Attrs: nounwind
define amdgpu_kernel void @use_invariant_promotable_lds(ptr addrspace(1) %arg) #2 {
; CHECK-LABEL: name: use_invariant_promotable_lds
; CHECK: bb.1.bb:
; CHECK-NEXT: liveins: $sgpr4_sgpr5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
; CHECK-NEXT: early-clobber %13:sreg_64_xexec = S_LOAD_DWORDX2_IMM_ec [[COPY]], 36, 0 :: (dereferenceable invariant load (p1) from %ir.arg.kernarg.offset, align 4, addrspace 4)
; CHECK-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %13, 0, 0 :: ("amdgpu-noclobber" load (s32) from %ir.arg.load, addrspace 1)
; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[S_LOAD_DWORD_IMM]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vreg_64_align2 = COPY [[DEF]]
; CHECK-NEXT: FLAT_STORE_DWORD [[COPY2]], [[COPY1]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.tmpI)
; CHECK-NEXT: S_ENDPGM 0
bb:
%i = load i32, ptr addrspace(1) %arg, align 4
%tmp = alloca i32, align 4, addrspace(5)
%tmpI = call ptr @llvm.invariant.start.p5(i64 4, ptr addrspace(5) %tmp) #3
call void @llvm.invariant.end.p5(ptr %tmpI, i64 4, ptr addrspace(5) %tmp) #3
store i32 %i, ptr %tmpI, align 4
ret void
}

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(inaccessiblemem: readwrite) }
attributes #2 = { nounwind }
attributes #3 = { nounwind memory(argmem: readwrite) }