firtool-1.127.0

What's Changed

• [ESI] MessageData utility functions by @mortbopet in #8777
• [ESI] Always find_package Python3 Development by @mortbopet in #8778
• [ESI] Disallow calls on an unconnected FuncService::Function by @mortbopet in #8779
• [Datapath] Create Datapath to Comb Pass by @cowardsa in #8736
• [Comb] Fix more recursive mux folders by @TaoBi22 in #8756
• [AIG] Remove aig.cut by @uenoku in #8784
• Bump LLVM by @uenoku in #8783
• Update to new builder format. by @jpienaar in #8785
• Create .git-blame-ignore-revs by @jpienaar in #8787
• [ESI] Also publish releases on workflow_dispatch by @mortbopet in #8780
• [ESI] Yield gil before blocking operations in MessageDataFuture by @mortbopet in #8789
• [Comb] Add comb.reverse operation with Verilog Export by @mafeguimaraes in #8758
• [HW][HWAggregateToComb] Add support for hw.array_inject operation in HWAggregateToComb pass by @uenoku in #8788
• [FIRRTL] Type check in Cat operatnds in FIR parser by @uenoku in #8793
• [ESI] Expose accelerator through AcceleratorConnection py api by @mortbopet in #8781
• [ESI] Better single-argument handling for FunctionPort by @mortbopet in #8782
• [ESI] Extend instead of override CMAKE_CXX_FLAGS by @mortbopet in #8551
• [RTG] Add InsertTestToFileMappingPass by @maerhart in #8795
• Bump LLVM to 76bebb5be9daf9ca035777b17fa63d4ce13e79b9 by @maerhart in #8796
• [RTG] Don't hardcode the root op of passes where not necessary by @maerhart in #8791
• [RTG] Sequences are always private by @maerhart in #8792
• [RTG] Rely on textual pass pipeline in Python and CAPI by @maerhart in #8797
• [RTG] Simplify EmitISAEmission pass by @maerhart in #8798
• [HWToSMT] Return an unbound value for OOB hw.array_inject by @uenoku in #8794
• [HWToLLVM] Add lowering support for 'hw.array_inject' op by @mvpant in #8774
• [ESI] Always build zlib statically into ESI runtime by @mortbopet in #8801
• [FIRRTL] Add layer colour verifiers to force and release ops by @rwy7 in #8800
• [ESI][Runtime] Fix wheel build by @teqdruid in #8803
• [ESI][Runtime] Fix backend DLL loading by @teqdruid in #8805
• [ESI] Improve backend loading error on windows by @mortbopet in #8802
• [LowerFIRRTLToHW] Add SYNTHESIS guard to fprintf lib by @uenoku in #8812

New Contributors

• @mafeguimaraes made their first contribution in #8758

Full Changelog: firtool-1.126.0...firtool-1.127.0

firtool-1.126.0

What's Changed

• [ESI] Add a transaction snoop operation by @teqdruid in #8684
• [HW] MaterializeConstant: check for null block by @teqdruid in #8687
• [VerifToSMT] Fix lowering of initial integer values for BMC by @fzi-hielscher in #8689
• [FIRRTL] Add "knownlayers" specifications to ExtModules by @rwy7 in #8623
• [Deseq] Add bin flag to enable mux by @fabianschuiki in #8686
• [Datapath] Add Datapath to SMT conversion pass by @cowardsa in #8682
• [Comb] Avoid some non-terminating MuxOp fold cases by @TaoBi22 in #8691
• [Comb] Fix excessive const shifts causing crashes and invalid IR by @fabianschuiki in #8696
• [AIG] Add canonicalization to simplify inversion by @uenoku in #8697
• Fix filecheck directive typos and fix now-active test lines by @dtzSiFive in #8702
• [Verif][LEC] Make LECOp result optional to avoid unsafe conversion by @fzi-hielscher in #8701
• [hw] Convert HW Passes to use ODS constructors by @seldridge in #8703
• [OM] Deprecate the OM map by @prithayan in #8606
• Bump LLVM to ace1c838ca91c83c7a271d9378b86ea56051e83f. by @mikeurbach in #8705
• [RTG] Redefine RandomNumberInRangeOp upper bound to be inclusive by @maerhart in #8710
• [AIG] Add slice indexing support to LongestPathCollection in AIG python on bindings by @uenoku in #8709
• [MooreToCore] Lower empty string_constant to expected bit width. by @mvpant in #8688
• Bump LLVM to d9190f8141661bd6120dea61d28ae8940fd775d0 by @maerhart in #8715
• [RTG] Add custom tuple type to support empty tuples by @maerhart in #8711
• [RTG] Enable conditional value forwarding for ValidateOp by @maerhart in #8712
• [AIG] Use llvm::stable_sort to sort paths by @uenoku in #8717
• [circt-verilog] Enable SROA again by @maerhart in #8720
• [PyRTG] Support Python config parameters by @maerhart in #8719
• [Python] Speed up type_to_pytype and attribute_to_var by @maerhart in #8718
• [FIRRTL] Remove circuit from macro used by inline layers by @rwy7 in #8714
• [FIRRTL] SFCCompat: properly lower invalidated enums by @youngar in #8722
• [FIRRTL] FIRParser: support caching constants in match statements by @youngar in #8723
• [FIRRTL] check bundles have unique field names by @youngar in #8729
• [FIRRTL] TagExtract: make type inference parser friendly by @youngar in #8727
• [ESI] Fix wrap op canonicalizers by @teqdruid in #8730
• [ExportVerilog] localparam should always print bitwidths by @youngar in #8732
• [circt-lec] Adding support for the datapath dialect by @cowardsa in #8721
• [circt-synth] Add an option to disable WordsToBits, remove verification code from design by @uenoku in #8733
• [CombToSMT] Force conversion from bool to bv<1> after icmp by @maerhart in #8737
• [FIRRTL] LowerSigs: Add enum support by @youngar in #8731
• [RTG] Add a pass to print a list of tests by @maerhart in #8734
• [Verif] Add RefinementCheckingOp by @fzi-hielscher in #8713
• [FIRRTL] Enums: Add user-defined constructor encodings by @youngar in #8724
• [FIRRTL] FIRParser: parse tagExtract operations by @youngar in #8728
• [FIRRTL] LowerToHW: handle TagExtractOp by @youngar in #8726
• [FIRRTL] Do not allow uninferred widths or rests in enums by @youngar in #8740
• [RTG] Add immediate concat and slice operations by @maerhart in #8735
• [RTG] Add concat_immediate and slice_immediate folders by @maerhart in #8738
• [RTG] Fix ValidateOp elaboration by @maerhart in #8743
• [AIG][LongestPathAnalysis] Fix a bug in deduplicatePathsImpl by @uenoku in #8746
• [RTG] Support immediate slice/concat after validate by @maerhart in #8744
• [VerifToSMT] Move some LEC lowering code to a superclass, NFC by @fzi-hielscher in #8748
• [circt-opt][FSMToSV] Fix bug of operations not being cloned in transition region in FSMToSV Conversion by @AtticusKuhn in #8753
• [circt-bmc] Support seq.firreg with sync reset by @liuyic00 in #8698
• [RTG] Add operations to report test result by @maerhart in #8751
• [AIG][NFC] Add a module to OutputPort data structure and refactor the name handling by @uenoku in #8759
• [VerifToSMT] Fix lowering of no output, no result LEC op by @fzi-hielscher in #8763
• [ImportVerilog] Add (* full_case *) attribute support by @mvpant in #8762
• [HW][AIG] Add InstancePath CAPI and use native structures for AIG longest path analysis by @uenoku in #8760
• [Seq] Add a pass to convert an array seq.firreg to seq.firmem by @prithayan in #8716
• [FIRRTL] Make enums behave less like aggregates by @youngar in #8742
• [FIRRTL] FlattenMemories: handle memories with enums by @youngar in #8741
• [HWToSMT] Add ArrayInject lowering to HWToSMT by @uenoku in #8765
• [VerifToSMT] Lower verif.refines to SMT by @fzi-hielscher in #8749
• [Support] Add NPN class for Boolean function canonicalization by @uenoku in #8747
• [MooreToCore] Preserve module port order by @fabianschuiki in #8768
• [circt-verilog] Add register-to-memory pass to pipeline by @fabianschuiki in #8773
• [FIRRTL] Fix TagExtractOp's type inference by @youngar in #8766
• [FIRRTL] make mux type inference support enumeration types by @youngar in #8769
• [FIRRTL] FRT: support creating 0-valued enums by @youngar in #8772
• Migrate away from ArrayRef(std::nullopt_t) by @kazutakahirata in #8776

New Contributors

• @mvpant made their first contribution in #8688
• @AtticusKuhn made their first contribution in #8753
• @kazutakahirata made their first contribution in #8776

Full Changelog: firtool-1.125.0...firtool-1.126.0

ESIRuntime-0.1.3

What's Changed

• [ESI] Add a transaction snoop operation by @teqdruid in #8684
• [ESI] Fix wrap op canonicalizers by @teqdruid in #8730
• [ESI] MessageData utility functions by @mortbopet in #8777
• [ESI] Always find_package Python3 Development by @mortbopet in #8778
• [ESI] Disallow calls on an unconnected FuncService::Function by @mortbopet in #8779

Full Changelog: firtool-1.125.0...ESIRuntime-0.1.3

firtool-1.125.0

What's Changed

• [LLHD] Use initial signal value to fill gaps in CombineDrives by @fabianschuiki in #8636
• Datapath Dialect Definition by @cowardsa in #8638
• [RTG] Add ValidationTypeInterface by @maerhart in #8639
• [Python] Add Python bindings for AIG dialect by @uenoku in #8646
• [circt-verilog] Add MapArithToComb pass to pipeline by @fabianschuiki in #8649
• [ExportVerilog] Add support for hw.array_inject by @fabianschuiki in #8645
• [AIG] Enhance longest path analysis with detailed timing statistics and JSON output by @uenoku in #8644
• [AIG][NFC] Introduce a helper struct to manage result paths by @uenoku in #8651
• [AIG][CAPI] Add C API for LongestPathAnalysis by @uenoku in #8652
• [RTG] Add EmbedValidationValuesPass by @maerhart in #8648
• [PyCDE] Improve location information by @teqdruid in #8635
• [Datapath] Operator definitions and canonicalization patterns by @cowardsa in #8647
• [ESI] Make RAM delarations' addresses unsigned by @teqdruid in #8658
• [PyCDE] Add bundle transform and rework coerce by @teqdruid in #8660
• [LLHD] Add loop unrolling pass by @fabianschuiki in #8620
• [seq] Simplify clock enabled when constant enabled. by @jpienaar in #8655
• [circt-synth] Add -emit-bytecode option by @uenoku in #8661
• [LLHD] Make Deseq pass emit seq.firreg instead of seq.compreg by @fabianschuiki in #8662
• [importverilog] Lvalue RangelSelect and ElementSelect to use range. by @jpienaar in #8663
• Convert to CF before running LLHD inline. by @jpienaar in #8667
• [FIRRTL] Delete BlackBoxResourceFileNameAnno by @seldridge in #8669
• [RTG] Add LowerValidateToLabels pass by @maerhart in #8666
• [AIG][Python] Add Python bindings for LongestPathAnalysis by @uenoku in #8659
• [FIRRTL] Lint XMRs in the "design" by @seldridge in #8668
• [ImportVerilog] Add support for SVA declarations by @towoe in #8656
• [Datapath] Conversion Pass Comb to Datapath by @cowardsa in #8664
• Add SitestBlackBoxLibrariesAnnotation; process in CreateSiFiveMetadataPass by @tmckay-sifive in #8670
• [FIRRTL] Fix inject-dut-hier deleting new top by @seldridge in #8678
• [ImportVerilog] Incorporate block names to variable/instance names by @fabianschuiki in #8680
• [RTG] Add Randomization Pipeline by @maerhart in #8675
• Insert probes at least post def. by @jpienaar in #8674
• [FIRRTL] Lower registers under ifdefs by @rwy7 in #8605
• [MooreToCore] Lower exponentiation to math.ipowi (PowUOpConversion) by @liamslj13 in #8654
• [circt-synth] [Synthesis] Add synthesis pipeline and refactor the lib structure by @uenoku in #8681
• [Comb] Replace mux cond uses in true/false operand with constant by @fabianschuiki in #8685
• [FIRRTL][firtool] Enable advanced layer sink by default by @rwy7 in #8683

New Contributors

• @tmckay-sifive made their first contribution in #8670

Full Changelog: firtool-1.124.0...firtool-1.125.0

firtool-1.124.0

What's Changed

• [Support] Add concatPath method to InstancePathCache by @uenoku in #8627
• [RTG] Add CAPI and python bindings to register passes by @maerhart in #8632
• [MooreToCore] Lower exponentiation to math.ipowi (PowSOpConversion) by @liamslj13 in #8574
• [ImportVerilog] Detect and fixup two-state-exhaustive case statements by @fabianschuiki in #8628
• [LLHD] Remove drive-only signals in Sig2Reg pass by @fabianschuiki in #8629
• [AIG] Refactor Longest Path Analysis with hierarchical path support by @uenoku in #8630
• [RTG] Add validate operation by @maerhart in #8631
• [RTG] Add UniqueValidateOpsPass by @maerhart in #8633
• [AIG] Fix history's instance path update in LongestPathAnalysis by @uenoku in #8637
• [FIRRTL] Allow layers to RWProbe into the design by @rwy7 in #8641
• [circt-bmc] Support registers with reset signals by @liuyic00 in #8622

New Contributors

• @liamslj13 made their first contribution in #8574

Full Changelog: firtool-1.123.2...firtool-1.124.0

firtool-1.123.2

What's Changed

• [CI] Add smarter cache cleanup with size-based filtering by @uenoku in #8580
• [PyCDE] Import MLIR: provide hook to preprocess ops by @teqdruid in #8624
• [FIRRTL] Fix Grand Central companion not-in-design by @seldridge in #8625

Full Changelog: firtool-1.123.1...firtool-1.123.2

firtool-1.123.1

What's Changed

• [PyCDE] Support for importing Kanagawa by @teqdruid in #8616
• [PyCDE] Support custom op conversion on import by @teqdruid in #8617
• [FIRRTL] Fix cat canonicalization to handle mixed signed/unsigned operands by @uenoku in #8621
• [FIRRTL] Avoid interface cast in inject-dut-hier by @seldridge in #8619

Full Changelog: firtool-1.123.0...firtool-1.123.1

firtool-1.123.0

What's Changed

• [SV] Enhanced name validation: support IEEE standard escape name checking by @RonxBulld in #8518
• [Docs][HW] Missing formatting in docs by @dobios in #8569
• [docs] Fix variable names by @towoe in #8568
• [Seq] Add a canonicalization to remove read-only memory by @uenoku in #8564
• [FIRRTL] Prevent name propagation for register by @uenoku in #8565
• [AIG][AIGER] Add AIGER Importer by @uenoku in #8567
• [FIRRTL] Make XMRRef and Deref pure by @rwy7 in #8570
• [FIRRTL] Add canonicalization test to ensure dead ref ops are eliminated by @rwy7 in #8577
• [FIRRTL] AdvancedLayerSink: clone ref ops into layerblocks by @rwy7 in #8576
• [circt-bmc] Add feature to ignore asserts on some initial cycles by @TaoBi22 in #8573
• [Arcilator] Don't try to run JIT if only part of the pipeline is run by @TaoBi22 in #8575
• [circt-verilog] Add updated LLHD passes to the pipeline by @fabianschuiki in #8579
• [ImportVerilog] Add support for concurrent assertions by @towoe in #8559
• [Arc] don't sink ops with nested writes in MergeIfs by @TaoBi22 in #8584
• [ImportVerilog] Support packed structs in inside operator by @AnnuCode in #8545
• [AIG][ImportAIGER] Fix incorrect tokenization and simplify parser by @uenoku in #8588
• [AIG][AIGER] Add AIGER Exporter by @uenoku in #8582
• [LLHD] Embed procedural ops within modules into llhd.combinational ops by @fabianschuiki in #8590
• [AIG][NFC] Refactor longest path analysis to enable caching and separate to a different file by @uenoku in #8593
• [AIG] Add AIGER runner passes for external logic solver integration by @uenoku in #8592
• [firld] Add firld to link FIRRTL circuits by @unlsycn in #8561
• [LLHD] Update function call inlining pass; add to circt-verilog by @fabianschuiki in #8597
• Bump LLVM to 945ce1aa3d29e24c49720ae9e0bcfbac88f2defd. by @mikeurbach in #8589
• [CI] Only use ccache for Release builds in nightly integration tests by @uenoku in #8581
• [Kanagawa] Replace CSE with specialized pass by @teqdruid in #8599
• [FIRRTL] Allow duplicate tracker annotations in LowerClasses. by @mikeurbach in #8598
• [OM] Use SymbolTable::lookup instead of lookupNearestSymbolFrom by @uenoku in #8602
• [LLHD] Add pass to lower acyclic control flow to mux ops by @fabianschuiki in #8600
• [Comb] Enable cross-block folds on and/or/xor by @fabianschuiki in #8607
• [FIRRTL] Make CatPrimOp variadic by @uenoku in #8557
• [Comb] Enable cross-block folds on add/sub/mul/div/mod by @fabianschuiki in #8608
• [Comb] Enable cross-block folds on replicate/parity/shl/shr/mux/icmp by @fabianschuiki in #8609
• [FIRRTL] Improve canonicalization patterns for variadic cat and reduction operations by @uenoku in #8578
• [firtool] Enable WireElimination pass by @uenoku in #8594
• [Comb] Enable cross-block folds on extract/concat/array_create(mux) by @fabianschuiki in #8611
• [FIRRTL] Move all annotations in inject-dut-hier by @seldridge in #8596
• [Pipeline] Python dialect and pass registration by @teqdruid in #8612
• [FIRRTL] Allow GC Companion multi-instantiation by @seldridge in #8603
• [Kanagawa] Python dialect and pass registration by @teqdruid in #8613
• [AIG][AIGERRunner] Refactor AIG external solver passes and add continueOnFailure option by @uenoku in #8615

New Contributors

• @RonxBulld made their first contribution in #8518
• @towoe made their first contribution in #8568

Full Changelog: firtool-1.122.0...firtool-1.123.0

firtool-1.122.0

What's Changed

• [RTG][Elaboration] Improve how tests are matched with targets by @maerhart in #8391
• [RTG] Add MemoryAllocation pass by @maerhart in #8395
• [RTG] Add MemoryAllocation pass to pipeline by @maerhart in #8397
• [PyRTG] Refactor targets/configs by @maerhart in #8399
• [AIG] Add LongestPathAnalysis implementation by @uenoku in #8529
• [FIRRTL] Dedup: MustDedup support merging of pub+priv modules by @youngar in #8546
• [LLHD] Add combinational process op by @fabianschuiki in #8536
• [LLHD] Add llhd.sig.extract support to Mem2Reg by @fabianschuiki in #8542
• [LLHD] Use new combinational process instead of execute regions by @fabianschuiki in #8537
• [PyRTG] Add type wrappers by @maerhart in #8550
• [PyRTG] Codegen sequences lazily by @maerhart in #8554
• [FIRRTL][InjectDUT] Update rwprobes when relocating them. by @dtzSiFive in #8553
• [OM][Python] Support string and list as evaluator arguments by @uenoku in #8556
• [FIRRTL] Extract instances above DUT w/ moveDut by @seldridge in #8555
• [Seq] Add canonicalization for FirReg with mux-based constant drivers by @uenoku in #8562

Full Changelog: firtool-1.121.0...firtool-1.122.0

firtool-1.121.0

What's Changed

• [SCFToCalyx] Lower Math AbsFOp by @jiahanxie353 in #8492
• [FIRRTL] Drop ExcludeMemFromMemToRegOfVec, unused by @seldridge in #8533
• [CombToAIG] Implement Wallace Tree Multiplier by @uenoku in #8523
• [Support] Factor out unused op pruning from LLHD Mem2Reg; NFC by @fabianschuiki in #8531
• [CI] Bump docker images by @hovind in #8500
• [RTG][Elaboration] Properly handle values with identity by @maerhart in #8388
• [RTG][Elaboration] Treat randomized sequences as regular identity values by @maerhart in #8389
• [LLHD] Add pass to combine drives to aggregate signals by @fabianschuiki in #8534
• [CombToSMT] Fix conversion target by @maerhart in #8540
• [FIRRTL] Add moveDut field for inject DUT hier by @seldridge in #8535

Full Changelog: ESIRuntime-0.1.2...firtool-1.121.0