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[SYCL][FPGA] Remove deprecation message for intel::disable_loop_pipelining attribute #6404

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smanna12
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@smanna12 smanna12 commented Jul 6, 2022

#6254 added the fpga_pipeline attribute and
deprecated the intel::disable_loop_pipelining attribute.
While this was in the pipeline, the internal decision was made to switch to properties
rather than attributes for this type of thing.

At this point, internal request is that (at a minimum) the deprecation message for
intel::disable_loop_pipelining be removed, as we no longer plan to deprecate it.
Optionally the intel::fpga_pipeline attribute can be removed from the frontend as well.

Signed-off-by: Soumi Manna [email protected]

…ining attribute

intel#6254 added the fpga_pipeline attribute and
deprecated the intel::disable_loop_pipelining attribute.
While this was in the pipeline, the internal decision was made to switch to properties
rather than attributes for this type of thing.

At this point, internal request is that (at a minimum) the deprecation message for
intel::disable_loop_pipelining be removed, as we no longer plan to deprecate it.

Signed-off-by: Soumi Manna <[email protected]>
@smanna12 smanna12 changed the title [SYCL][FPGA] Remove deprecation message for intel::disable_loop_pipel… [SYCL][FPGA] Remove deprecation message for intel::disable_loop_pipelining attribute Jul 6, 2022
@smanna12 smanna12 requested a review from mendell27 July 6, 2022 11:40
@smanna12 smanna12 marked this pull request as ready for review July 6, 2022 11:40
@smanna12 smanna12 requested a review from a team as a code owner July 6, 2022 11:40
Signed-off-by: Soumi Manna <[email protected]>
@smanna12 smanna12 requested a review from premanandrao July 6, 2022 11:45
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smanna12 commented Jul 6, 2022

Failures are not related to my PR:

https://github.com/intel/llvm/runs/7214257852?check_suite_focus=true


Failed Tests (1):
SYCL :: Basic/stream/release_resources_test.cpp

https://github.com/intel/llvm/runs/7214258579?check_suite_focus=true


Failed Tests (1):
SYCL :: Assert/assert_in_simultaneously_multiple_tus.cpp

mendell27
mendell27 previously approved these changes Jul 6, 2022
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Optionally the intel::fpga_pipeline attribute can be removed from the frontend as well.

I am assuming this will be done in a later patch?

Signed-off-by: Soumi Manna <[email protected]>
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smanna12 commented Jul 6, 2022

Optionally the intel::fpga_pipeline attribute can be removed from the frontend as well.

I am assuming this will be done in a later patch?

Yes, this will be done in a later patch.

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smanna12 commented Jul 6, 2022

Failure is not related to this PR:
https://github.com/intel/llvm/runs/7221701309?check_suite_focus=true
Failed Tests (1):
SYCL :: Assert/assert_in_simultaneously_multiple_tus_one_ndebug.cpp

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smanna12 commented Jul 7, 2022

Thank you @premanandrao and @mendell27 for reviews.

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smanna12 commented Jul 7, 2022

@intel/llvm-gatekeepers, this PR is ready to be merged. Thank you

@steffenlarsen steffenlarsen merged commit 07201f5 into intel:sycl Jul 7, 2022
@smanna12 smanna12 deleted the Update_disable_loop_pipelining_attribute branch July 7, 2022 11:00
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4 participants