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Fix tidy issues #10

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Merged
merged 1 commit into from
Nov 11, 2019
Merged

Fix tidy issues #10

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57 changes: 23 additions & 34 deletions src/librustc_target/abi/call/xtensa.rs
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Original file line number Diff line number Diff line change
@@ -1,25 +1,23 @@
// reference: https://github.com/espressif/clang-xtensa/commit/6fb488d2553f06029e6611cf81c6efbd45b56e47#diff-aa74ae1e1ab6b7149789237edb78e688R8450


use crate::abi::call::{ArgType, FnType, Reg, Uniform};

const NUM_ARG_GPR: u64 = 6;
const MAX_ARG_IN_REGS_SIZE: u64 = 4 * 32;
const MAX_ARG_IN_REGS_SIZE: u64 = 4 * 32;
// const MAX_ARG_DIRECT_SIZE: u64 = MAX_ARG_IN_REGS_SIZE;
const MAX_RET_IN_REGS_SIZE: u64 = 2 * 32;
const MAX_RET_IN_REGS_SIZE: u64 = 2 * 32;

fn classify_ret_ty<Ty>(arg: &mut ArgType<'_, Ty>, xlen: u64) {
// The rules for return and argument types are the same, so defer to
// classifyArgumentType.
classify_arg_ty(arg, xlen, &mut 2); // two as max return size
}


fn classify_arg_ty<Ty>(arg: &mut ArgType<'_, Ty>, xlen: u64, remaining_gpr: &mut u64) {
// Determine the number of GPRs needed to pass the current argument
// according to the ABI. 2*XLen-aligned varargs are passed in "aligned"
// register pairs, so may consume 3 registers.

let arg_size = arg.layout.size;
if arg_size.bits() > MAX_ARG_IN_REGS_SIZE {
arg.make_indirect();
Expand All @@ -31,7 +29,7 @@ fn classify_arg_ty<Ty>(arg: &mut ArgType<'_, Ty>, xlen: u64, remaining_gpr: &mut

if alignment.bits() == 2 * xlen {
required_gpr = 2 + (*remaining_gpr % 2);
} else if arg_size.bits() > xlen && arg_size.bits() <= MAX_ARG_IN_REGS_SIZE {
} else if arg_size.bits() > xlen && arg_size.bits() <= MAX_ARG_IN_REGS_SIZE {
required_gpr = (arg_size.bits() + (xlen - 1)) / xlen;
}

Expand All @@ -44,14 +42,16 @@ fn classify_arg_ty<Ty>(arg: &mut ArgType<'_, Ty>, xlen: u64, remaining_gpr: &mut

// if a value can fit in a reg and the
// stack is not required, extend
if !arg.layout.is_aggregate() { // non-aggregate types
if !arg.layout.is_aggregate() {
// non-aggregate types
if arg_size.bits() < xlen && !stack_required {
arg.extend_integer_width_to(xlen);
}
} else if arg_size.bits() as u64 <= MAX_ARG_IN_REGS_SIZE { // aggregate types
} else if arg_size.bits() as u64 <= MAX_ARG_IN_REGS_SIZE {
// aggregate types
// Aggregates which are <= 4*32 will be passed in registers if possible,
// so coerce to integers.

// Use a single XLen int if possible, 2*XLen if 2*XLen alignment is
// required, and a 2-element XLen array if only XLen alignment is
// required.
Expand All @@ -61,48 +61,37 @@ fn classify_arg_ty<Ty>(arg: &mut ArgType<'_, Ty>, xlen: u64, remaining_gpr: &mut
// arg.extend_integer_width_to(arg_size + (xlen - 1) / xlen);
// }
if alignment.bits() == 2 * xlen {
arg.cast_to(Uniform {
unit: Reg::i64(),
total: arg_size
});
arg.cast_to(Uniform { unit: Reg::i64(), total: arg_size });
} else {
//TODO array type - this should be a homogenous array type
//FIXME array type - this should be a homogenous array type
// arg.extend_integer_width_to(arg_size + (xlen - 1) / xlen);
}

} else {
// if we get here the stack is required
assert!(stack_required);
arg.make_indirect();
}


// if arg_size as u64 <= MAX_ARG_IN_REGS_SIZE {
// let align = arg.layout.align.abi.bytes();
// let total = arg.layout.size;
// arg.cast_to(Uniform {
// unit: if align <= 4 { Reg::i32() } else { Reg::i64() },
// total
// });
// return;
// }


// if arg_size as u64 <= MAX_ARG_IN_REGS_SIZE {
// let align = arg.layout.align.abi.bytes();
// let total = arg.layout.size;
// arg.cast_to(Uniform {
// unit: if align <= 4 { Reg::i32() } else { Reg::i64() },
// total
// });
// return;
// }
}

pub fn compute_abi_info<Ty>(fty: &mut FnType<'_, Ty>, xlen: u64) {
if !fty.ret.is_ignore() {
classify_ret_ty(&mut fty.ret, xlen);
}

let return_indirect = fty.ret.layout.size.bits() > MAX_RET_IN_REGS_SIZE ||
fty.ret.is_indirect();
let return_indirect =
fty.ret.layout.size.bits() > MAX_RET_IN_REGS_SIZE || fty.ret.is_indirect();

let mut remaining_gpr = if return_indirect {
NUM_ARG_GPR - 1
} else {
NUM_ARG_GPR
};
let mut remaining_gpr = if return_indirect { NUM_ARG_GPR - 1 } else { NUM_ARG_GPR };

for arg in &mut fty.args {
if arg.is_ignore() {
Expand Down
6 changes: 3 additions & 3 deletions src/librustc_target/spec/xtensa_esp32_none_elf.rs
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
use crate::spec::{LinkerFlavor, PanicStrategy, Target, TargetOptions, TargetResult, abi::Abi};
use crate::spec::{abi::Abi, LinkerFlavor, PanicStrategy, Target, TargetOptions, TargetResult};
// use crate::spec::abi::Abi;

pub fn target() -> TargetResult {
Expand Down Expand Up @@ -60,7 +60,7 @@ pub fn target() -> TargetResult {
Abi::SysV64,
],

.. Default::default( )
}
..Default::default()
},
})
}
6 changes: 3 additions & 3 deletions src/librustc_target/spec/xtensa_esp8266_none_elf.rs
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
use crate::spec::{LinkerFlavor, PanicStrategy, Target, TargetOptions, TargetResult, abi::Abi};
use crate::spec::{abi::Abi, LinkerFlavor, PanicStrategy, Target, TargetOptions, TargetResult};
// use crate::spec::abi::Abi;

pub fn target() -> TargetResult {
Expand Down Expand Up @@ -60,7 +60,7 @@ pub fn target() -> TargetResult {
Abi::SysV64,
],

.. Default::default( )
}
..Default::default()
},
})
}
6 changes: 3 additions & 3 deletions src/librustc_target/spec/xtensa_none_elf.rs
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
use crate::spec::{LinkerFlavor, PanicStrategy, Target, TargetOptions, TargetResult, abi::Abi};
use crate::spec::{abi::Abi, LinkerFlavor, PanicStrategy, Target, TargetOptions, TargetResult};
// use crate::spec::abi::Abi;

pub fn target() -> TargetResult {
Expand Down Expand Up @@ -60,7 +60,7 @@ pub fn target() -> TargetResult {
Abi::SysV64,
],

.. Default::default( )
}
..Default::default()
},
})
}