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Verilog: lowering for types #846

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Merged
merged 1 commit into from
Dec 27, 2024
Merged

Verilog: lowering for types #846

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8 changes: 8 additions & 0 deletions src/verilog/verilog_lowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -416,3 +416,11 @@ exprt verilog_lowering(exprt expr)

UNREACHABLE;
}

typet verilog_lowering(typet type)
{
if(type.id() == ID_verilog_signedbv || type.id() == ID_verilog_unsignedbv)
return lower_to_aval_bval(type);
else
return type;
}
2 changes: 2 additions & 0 deletions src/verilog/verilog_lowering.h
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Expand Up @@ -10,7 +10,9 @@ Author: Daniel Kroening, [email protected]
#define CPROVER_VERILOG_LOWERING_H

class exprt;
class typet;

exprt verilog_lowering(exprt);
typet verilog_lowering(typet);

#endif
4 changes: 4 additions & 0 deletions src/verilog/verilog_synthesis.cpp
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Expand Up @@ -3314,6 +3314,10 @@ exprt verilog_synthesist::symbol_expr(
{
exprt result=exprt(curr_or_next==NEXT?ID_next_symbol:ID_symbol, symbol.type);
result.set(ID_identifier, symbol.name);

// The type may need to be lowered
result.type() = verilog_lowering(result.type());

return result;
}

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