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Verilog logical (in)equality expression #593

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Merged
merged 1 commit into from
Jul 16, 2024
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Verilog logical (in)equality expression #593

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2 changes: 2 additions & 0 deletions src/hw_cbmc_irep_ids.h
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Original file line number Diff line number Diff line change
Expand Up @@ -51,6 +51,8 @@ IREP_ID_ONE(ports)
IREP_ID_ONE(inst)
IREP_ID_ONE(Verilog)
IREP_ID_ONE(verilog_assignment_pattern)
IREP_ID_ONE(verilog_logical_equality)
IREP_ID_ONE(verilog_logical_inequality)
IREP_ID_ONE(verilog_explicit_cast)
IREP_ID_ONE(verilog_size_cast)
IREP_ID_ONE(verilog_implicit_typecast)
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4 changes: 2 additions & 2 deletions src/verilog/parser.y
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Expand Up @@ -3541,9 +3541,9 @@ expression:
| expression TOK_PERCENT expression
{ init($$, ID_mod); mto($$, $1); mto($$, $3); }
| expression TOK_EQUALEQUAL expression
{ init($$, ID_equal); mto($$, $1); mto($$, $3); }
{ init($$, ID_verilog_logical_equality); mto($$, $1); mto($$, $3); }
| expression TOK_EXCLAMEQUAL expression
{ init($$, ID_notequal); mto($$, $1); mto($$, $3); }
{ init($$, ID_verilog_logical_inequality); mto($$, $1); mto($$, $3); }
| expression TOK_EQUALEQUALEQUAL expression
{ init($$, ID_verilog_case_equality); mto($$, $1); mto($$, $3); }
| expression TOK_EXCLAMEQUALEQUAL expression
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37 changes: 37 additions & 0 deletions src/verilog/verilog_typecheck_expr.cpp
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Expand Up @@ -2404,9 +2404,46 @@ exprt verilog_typecheck_exprt::convert_binary_expr(binary_exprt expr)

return std::move(expr);
}
else if(
expr.id() == ID_verilog_logical_equality ||
expr.id() == ID_verilog_logical_inequality)
{
// == and !=
Forall_operands(it, expr)
convert_expr(*it);

tc_binary_expr(expr);

// This returns 'x' if either of the operands contains x or z.
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I have to admit that I don't understand how this comment relates to or explains what follows?!

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@kroening kroening Jul 16, 2024 •
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Maybe by example:

'b0 == 'b0 is 0
'b1x == 'b10 is x
'b1z == 'b1z is x

Hence, if both operands are two-valued, the result is two-valued. If either operand is four-valued, the result is four-valued.

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I understand the example and was assuming as much, but the code that follows just deals with types, it doesn't actually change the expression id or the likes. To me, the comment suggested that the code that follows actually evaluates the expression (or, rather, constructs some code to produce a value for the given operands).

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It does change the ID when it's two-valued -- lines 2431 and 2433.

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Yes, but not in the four-valued case. So I was just a bit confused - but really only by the comment, not the actual implementation.

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Yes, in the four-valued case, the ID stays D_verilog_logical_equality/D_verilog_logical_inequality. I'll add a comment for that.

if(
expr.lhs().type().id() == ID_verilog_signedbv ||
expr.lhs().type().id() == ID_verilog_unsignedbv ||
expr.rhs().type().id() == ID_verilog_signedbv ||
expr.rhs().type().id() == ID_verilog_unsignedbv)
{
// Four-valued case. The ID stays
// ID_verilog_logical_equality or
// ID_verilog_logical_inequality.
expr.type() = verilog_unsignedbv_typet(1);
}
else
{
// On two-valued logic, it's the same as proper equality.
expr.type() = bool_typet();
if(expr.id() == ID_verilog_logical_equality)
expr.id(ID_equal);
else
expr.id(ID_notequal);
}

return std::move(expr);
}
else if(expr.id()==ID_verilog_case_equality ||
expr.id()==ID_verilog_case_inequality)
{
// === and !==
// The result is always Boolean, and semantically
// a proper equality is performed.
expr.type()=bool_typet();

Forall_operands(it, expr)
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