world-level BMC: implement two empty match rules #1167
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This adds a PRECONDITION on the starting timeframe to the word-level SVA sequence encoding.
This adds parentheses around the arguments of SVA ## to avoid ambiguity.
This replaces the sva_sequence_concatenation_exprt by multi-operand variants of sva_cycle_delay_exprt, sva_cycle_delay_plus_exprt and sva_cycle_delay_star_exprt. This simplifies the implementation of the SystemVerilog concatenation rules.
This implements two SVA empty match rules in the word-level BMC encoding.
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This implements two SVA empty match rules in the word-level BMC encoding.