SVA: default sequence semantics #1071
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SVA sequences can have weak or strong semantics. 1800-2017 16.12.2 Sequence property requires that sequences in properties that are not explicitly marked as strong or weak are interpreted as weak when used in assert property or assume property, and strong otherwise. The Verilog type checker now emits corresponding expressions sva_implict_weak and sva_implicit_strong for uses of SVA sequences in properties.
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tautschnig
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Apr 22, 2025
Yes, the use of it is in #1067 |
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SVA sequences can have weak or strong semantics. 1800-2017 16.12.2 Sequence property requires that sequences in properties that are not explicitly marked as strong or weak are interpreted as weak when used in
assert propertyorassume property, and strong otherwise.The Verilog type checker now emits corresponding expressions
sva_implict_weakandsva_implicit_strongfor uses of SVA sequences in properties.