linkedin article link: https://www.linkedin.com/pulse/rtl-design-verification-maze-solver-algorithm-using-verilog-ng-6zcqe%3FtrackingId=IEF1Iu7pTEqZ%252FPRBluoLwQ%253D%253D/?trackingId=IEF1Iu7pTEqZ%2FPRBluoLwQ%3D%3D
Will implememnt other mazer related algorithm such as BFS, Astar.... when I am very free to make it. Probably implement it in FPGA + communication with the host to evaluate the performance too!