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1. chipyard chipyard Public

   Forked from soc-dv/chipyard

   An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

   Scala 1 1

2. Fibonacci_calculator Fibonacci_calculator Public

   This repository includes Vivado Project composed of Verilog code for a Fibonacci calculator, featuring both FSM and datapath modules, as well as the top-level integration and a simulation testbench.

   Verilog 1

3. AXI_WB_Complete_bridge AXI_WB_Complete_bridge Public

   This repo contains the complete bridge that translates AXI signals to Wishbone and vice versa

   Verilog 1

4. Complete_bridge_verification Complete_bridge_verification Public

   This repository provides the verification environment for a complete bidirectional AXI-to-Wishbone bridge.

   Verilog 1

5. serv serv Public

   Forked from olofk/serv

   Customized SERV - The Serial RISC-V CPU, for Integration with Chipyard.

   Verilog 1

6. serv_Integration_in_chipyard serv_Integration_in_chipyard Public

   Forked from Ayysha-Q/Integration

   Critical files for integrating the SERV RISC-V core into Chipyard: core wrappers, Protocol Conversion bridge, custom configs, MMIO test programs, tile information, and build setup.

   Scala 1