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Architech (Silica EMEA)

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  1. Designing-a-Custom-AXI-Slave-Peripheral Designing-a-Custom-AXI-Slave-Peripheral Public

    A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools

    VHDL 41 19

  2. Designing-a-Custom-AXI-Master-using-BFMs Designing-a-Custom-AXI-Master-using-BFMs Public

    A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models

    VHDL 35 21

  3. Zynq-Zedboard-Vivado-Workshop Zynq-Zedboard-Vivado-Workshop Public

    Zynq Workshop for Beginners

    C 30 23

  4. HLS-Axi-Master-on-Microzed-with-Yocto-Linux-device-driver HLS-Axi-Master-on-Microzed-with-Yocto-Linux-device-driver Public

    Creation of a AXI Master and Yocto device driver for Zynq, using High Level Synthesis (HLS) techniques.

    VHDL 14 9

  5. Zynq-Configuration-Controller Zynq-Configuration-Controller Public

    A configuration controller solution allowing a Zynq device to configure downstream FPGAs

    VHDL 14 13

  6. Zynq-MMU-Caches-Control Zynq-MMU-Caches-Control Public

    A guide to controlling the Zynq Cortex A9 MMU / Caches, and a guide showing how to create custom software libraries in Xilinx SDK.

    C 11 9

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