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gadfortgadfort
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Merge pull request #135 from siliconcompiler/ihp130
add ihp enablement
2 parents b280b44 + e8509bd commit 27912a6

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25 files changed

+392
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‎.github/workflows/config/designs.json

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"remote": false,
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"target": "gf180_gf180mcu_fd_sc_mcu9t5v0"
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},
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{
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"design": "aes",
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"remote": false,
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"target": "ihp130_sg13g2_stdcell"
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},
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{
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"design": "aes",
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"remote": false,
@@ -76,6 +81,13 @@
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"skip": "Timeout on github runner",
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"target": "gf180_gf180mcu_fd_sc_mcu9t5v0"
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},
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{
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"cache": false,
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"design": "ariane",
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"remote": false,
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"skip": "Skipped until qualified",
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"target": "ihp130_sg13g2_stdcell"
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},
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{
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"cache": true,
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"design": "ariane",
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"skip": "[ERROR MPL-0010] Macro placement failed for macro cluster:",
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"target": "gf180_gf180mcu_fd_sc_mcu9t5v0"
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},
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{
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"cache": false,
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"design": "black_parrot",
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"remote": false,
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"skip": "Skipped until qualified",
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"target": "ihp130_sg13g2_stdcell"
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},
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{
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"cache": true,
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"design": "black_parrot",
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"remote": false,
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"target": "freepdk45_nangate45"
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},
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{
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"cache": false,
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"design": "caliptra-datavault",
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"remote": false,
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"skip": "Skipped until qualified",
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"target": "ihp130_sg13g2_stdcell"
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},
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{
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"cache": true,
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"design": "caliptra-datavault",
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"skip": "Timeout on github runner",
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"target": "freepdk45_nangate45"
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},
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{
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"cache": false,
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"design": "caliptra-keyvault",
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"remote": false,
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"skip": "Skipped until qualified",
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"target": "ihp130_sg13g2_stdcell"
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},
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{
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"cache": true,
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"design": "caliptra-keyvault",
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"remote": false,
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"target": "gf180_gf180mcu_fd_sc_mcu9t5v0"
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},
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{
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"design": "caliptra-sha512",
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"remote": false,
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"target": "ihp130_sg13g2_stdcell"
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},
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{
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"design": "caliptra-sha512",
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"remote": false,
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"remote": false,
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"target": "gf180_gf180mcu_fd_sc_mcu9t5v0"
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},
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{
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"design": "dynamic_node",
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"remote": false,
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"target": "ihp130_sg13g2_stdcell"
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},
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{
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"design": "dynamic_node",
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"remote": false,
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"remote": false,
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"target": "gf180_gf180mcu_fd_sc_mcu9t5v0"
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},
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{
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"design": "ethmac",
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"remote": false,
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"target": "ihp130_sg13g2_stdcell"
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},
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{
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"design": "ethmac",
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"remote": false,
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"remote": false,
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"target": "gf180_gf180mcu_fd_sc_mcu9t5v0"
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},
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{
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"design": "gcd",
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"remote": false,
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"target": "ihp130_sg13g2_stdcell"
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},
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{
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"design": "gcd",
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"remote": false,
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"remote": false,
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"target": "gf180_gf180mcu_fd_sc_mcu9t5v0"
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},
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{
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"design": "heartbeat",
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"remote": false,
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"target": "ihp130_sg13g2_stdcell"
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},
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{
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"design": "heartbeat",
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"remote": false,
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"remote": false,
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"target": "gf180_gf180mcu_fd_sc_mcu9t5v0"
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},
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{
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"design": "ibex",
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"remote": false,
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"target": "ihp130_sg13g2_stdcell"
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},
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{
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"design": "ibex",
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"remote": false,
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"remote": false,
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"target": "gf180_gf180mcu_fd_sc_mcu9t5v0"
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},
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{
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"design": "jpeg",
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"remote": false,
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"target": "ihp130_sg13g2_stdcell"
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},
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{
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"design": "jpeg",
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"remote": false,
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"remote": false,
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"target": "gf180_gf180mcu_fd_sc_mcu9t5v0"
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},
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{
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"design": "mock_alu",
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"remote": false,
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"target": "ihp130_sg13g2_stdcell"
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},
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{
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"design": "mock_alu",
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"remote": false,
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"remote": false,
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"target": "gf180_gf180mcu_fd_sc_mcu9t5v0"
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},
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{
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"design": "openmsp430",
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"remote": false,
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"target": "ihp130_sg13g2_stdcell"
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},
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{
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"design": "openmsp430",
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"remote": false,
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"remote": false,
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"target": "gf180_gf180mcu_fd_sc_mcu9t5v0"
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},
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{
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"design": "picorv32",
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"remote": false,
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"target": "ihp130_sg13g2_stdcell"
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},
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{
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"design": "picorv32",
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"remote": false,
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"remote": false,
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"target": "gf180_gf180mcu_fd_sc_mcu9t5v0"
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},
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{
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"design": "riscv32i",
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"remote": false,
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"target": "ihp130_sg13g2_stdcell"
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},
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{
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"design": "riscv32i",
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"remote": false,
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"remote": false,
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"target": "gf180_gf180mcu_fd_sc_mcu9t5v0"
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},
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{
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"design": "spi",
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"remote": false,
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"target": "ihp130_sg13g2_stdcell"
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},
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{
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"design": "spi",
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"remote": false,
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"skip": "Timeout on github runner",
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"target": "gf180_gf180mcu_fd_sc_mcu9t5v0"
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},
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{
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"cache": false,
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"design": "swerv",
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"remote": false,
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"skip": "Skipped until qualified",
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"target": "ihp130_sg13g2_stdcell"
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},
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{
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"cache": true,
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"design": "swerv",
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"remote": false,
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"target": "gf180_gf180mcu_fd_sc_mcu9t5v0"
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},
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{
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"cache": false,
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"design": "tiny_rocket",
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"remote": false,
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"skip": "Skipped until qualified",
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"target": "ihp130_sg13g2_stdcell"
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},
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{
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"design": "tiny_rocket",
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"remote": false,
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"remote": false,
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"target": "gf180_gf180mcu_fd_sc_mcu9t5v0"
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},
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{
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"design": "uart",
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"remote": false,
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"target": "ihp130_sg13g2_stdcell"
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},
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{
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"design": "uart",
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"remote": false,

‎pyproject.toml

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@@ -21,9 +21,9 @@ readme = "README.md"
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requires-python = ">=3.8"
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license = {file = "LICENSE"}
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dependencies = [
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"siliconcompiler>=0.27.0",
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"siliconcompiler>=0.28.1",
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"Jinja2>=3.1.2",
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"lambdapdk>=0.1.31",
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"lambdapdk>=0.1.32",
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"lambdalib>=0.2.10"
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]
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dynamic = ["version"]

‎scgallery/designs/aes/constraints/sg13g2_stdcell.sdc

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set clk_period 24.4
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set clk_io_pct 0.2
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set clk_port [get_ports clk]
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create_clock -name clk -period $clk_period $clk_port
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set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
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set_input_delay [expr {$clk_period * $clk_io_pct}] -clock clk $non_clock_inputs
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set_output_delay [expr {$clk_period * $clk_io_pct}] -clock clk [all_outputs]
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set_driving_cell -lib_cell sg13g2_buf_1 [all_inputs]

‎scgallery/designs/ariane/constraints/sg13g2_stdcell.sdc

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set clk_period 40.0
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set clk_io_pct 0.2
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set clk_port [get_ports clk_i]
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create_clock -name core_clock -period $clk_period $clk_port
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set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
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set_input_delay [expr {$clk_period * $clk_io_pct}] -clock core_clock $non_clock_inputs
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set_output_delay [expr {$clk_period * $clk_io_pct}] -clock core_clock [all_outputs]
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set_driving_cell -lib_cell sg13g2_buf_1 [all_inputs]

‎scgallery/designs/black_parrot/constraints/sg13g2_stdcell.sdc

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set clk_period 6.84
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set clk_io_pct 0.2
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set clk_port [get_ports clk_i]
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create_clock -name CLK -period $clk_period $clk_port
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set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
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set_input_delay [expr {$clk_period * $clk_io_pct}] -clock CLK $non_clock_inputs
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set_output_delay [expr {$clk_period * $clk_io_pct}] -clock CLK [all_outputs]
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set_driving_cell -lib_cell sg13g2_buf_1 [all_inputs]

‎scgallery/designs/caliptra/constraints/datavault/sg13g2_stdcell.sdc

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set clk_period 40.0
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set clk_io_pct 0.2
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set clk_port [get_ports clk]
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create_clock -name clk -period $clk_period $clk_port
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set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
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set_input_delay [expr {$clk_period * $clk_io_pct}] -clock clk $non_clock_inputs
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set_output_delay [expr {$clk_period * $clk_io_pct}] -clock clk [all_outputs]
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set_driving_cell -lib_cell sg13g2_buf_1 [all_inputs]

‎scgallery/designs/caliptra/constraints/keyvault/sg13g2_stdcell.sdc

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set clk_period 51.0
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set clk_io_pct 0.2
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set clk_port [get_ports clk]
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create_clock -name clk -period $clk_period $clk_port
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set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
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set_input_delay [expr {$clk_period * $clk_io_pct}] -clock clk $non_clock_inputs
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set_output_delay [expr {$clk_period * $clk_io_pct}] -clock clk [all_outputs]
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set_driving_cell -lib_cell sg13g2_buf_1 [all_inputs]

‎scgallery/designs/caliptra/constraints/sha512/sg13g2_stdcell.sdc

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set clk_period 66.9
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set clk_io_pct 0.2
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set clk_port [get_ports clk]
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create_clock -name clk -period $clk_period $clk_port
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set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
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set_input_delay [expr {$clk_period * $clk_io_pct}] -clock clk $non_clock_inputs
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set_output_delay [expr {$clk_period * $clk_io_pct}] -clock clk [all_outputs]
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set_driving_cell -lib_cell sg13g2_buf_1 [all_inputs]

‎scgallery/designs/dynamic_node/constraints/sg13g2_stdcell.sdc

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set clk_period 20
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set clk_io_pct 0.2
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set clk_port [get_ports clk]
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create_clock -name clk -period $clk_period $clk_port
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set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
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set_input_delay [expr {$clk_period * $clk_io_pct}] -clock clk $non_clock_inputs
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set_output_delay [expr {$clk_period * $clk_io_pct}] -clock clk [all_outputs]
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set_driving_cell -lib_cell sg13g2_buf_1 [all_inputs]

‎scgallery/designs/ethmac/constraints/sg13g2_stdcell.sdc

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set clk_io_pct 0.2
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set clk_period 30.0
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set clk_port [get_ports wb_clk_i]
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create_clock -name wb_clk_i -period $clk_period $clk_port
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set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
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set_input_delay [expr {$clk_period * $clk_io_pct}] -clock wb_clk_i $non_clock_inputs
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set_output_delay [expr {$clk_period * $clk_io_pct}] -clock wb_clk_i [all_outputs]
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set tx_clk_period 20.0
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set tx_clk_port [get_ports mtx_clk_pad_i]
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create_clock -name mtx_clk_pad_i -period $tx_clk_period $tx_clk_port
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set mtx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $tx_clk_port]
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set_input_delay [expr {$tx_clk_period * $clk_io_pct}] -clock mtx_clk_pad_i $mtx_non_clock_inputs
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set_output_delay [expr {$tx_clk_period * $clk_io_pct}] -clock mtx_clk_pad_i [all_outputs]
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set rx_clk_period 20.0
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set rx_clk_port [get_ports mrx_clk_pad_i]
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create_clock -name mrx_clk_pad_i -period $rx_clk_period $rx_clk_port
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set mrx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $rx_clk_port]
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set_input_delay [expr {$rx_clk_period * $clk_io_pct}] -clock mrx_clk_pad_i $mrx_non_clock_inputs
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set_output_delay [expr {$rx_clk_period * $clk_io_pct}] -clock mrx_clk_pad_i [all_outputs]
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set_clock_groups -name core_clock -logically_exclusive \
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-group [get_clocks wb_clk_i] \
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-group [get_clocks mtx_clk_pad_i] \
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-group [get_clocks mrx_clk_pad_i]
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set_driving_cell -lib_cell sg13g2_buf_1 [all_inputs]

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