cleanup rebase disaster for VPCLMUL

Author: DevJPM

crates/core_arch/src/x86/avx512vpclmulqdq.rs

@@ -57,6 +57,26 @@ pub unsafe fn _mm512_clmulepi64_epi128(a: __m512i, b: __m512i, imm8: i32) -> __m
 #[target_feature(enable = "avx512vpclmulqdq,avx512vl")]
 #[cfg_attr(test, assert_instr(vpclmul, imm8 = 0))]
 #[rustc_args_required_const(2)]
+pub unsafe fn _mm256_clmulepi64_epi128(a: __m256i, b: __m256i, imm8: i32) -> __m256i {
+    macro_rules! call {
+        ($imm8:expr) => {
+            pclmulqdq_256(a, b, $imm8)
+        };
+    }
+    constify_imm8!(imm8, call)
+}
+
+#[cfg(test)]
+mod tests {
+    // The constants in the tests below are just bit patterns. They should not
+    // be interpreted as integers; signedness does not make sense for them, but
+    // __mXXXi happens to be defined in terms of signed integers.
+    #![allow(overflowing_literals)]
+
+    use stdarch_test::simd_test;
+
+    use crate::core_arch::x86::*;
+
     macro_rules! verify_kat_pclmul {
         ($broadcast:ident, $clmul:ident, $assert:ident) => {
             // Constants taken from https://software.intel.com/sites/default/files/managed/72/cc/clmul-wp-rev-2.02-2014-04-20.pdf