Fix: loads to an MMIO region triggers a resync and does not read

(loads were assumed to be idempotent, but have a case where it is not in data caching)

Author: xusine

components/uArch/CoreModel/cycle.cpp

@@ -1659,8 +1659,11 @@ CoreImpl::valuePredictAtomic()
             ++theValuePredictions;
 
             if (theSpeculateOnAtomicValuePerfect) {
-                lsq_head->theExtendedValue =
-                  ValueTracker::valueTracker(theNode).load(theNode, lsq_head->thePaddr, lsq_head->theSize);
+                bits val = ValueTracker::valueTracker(theNode).load(theNode, lsq_head->thePaddr, lsq_head->theSize);
+                lsq_head->theExtendedValue = val;
+                if (val == -1) {
+                    lsq_head->theInstruction->forceResync(true);
+                }
             } else {
                 if (lsq_head->theOperation == kCAS) {
                     lsq_head->theExtendedValue = lsq_head->theCompareValue;

components/uArch/ValueTracker.hpp

@@ -527,6 +527,10 @@ struct ValueTracker
         DBG_Assert(aSize <= 16 && aSize >= 1);
         DBG_Assert(anAddress < 0x40000000000LL);
         DBG_(Iface, (<< "CPU[" << aCPU << "] Load " << anAddress << "[" << aSize << "]"));
+        
+        // mmio
+        // higher region of MMIO starts at 0x40_0000_0000 for RAM less than 256GB
+        if (anAddress < 0x40000000 || anAddress >= 0x4000000000) return -1;
 
         Flexus::Qemu::Processor cpu = Flexus::Qemu::Processor::getProcessor(aCPU);
 

components/uArch/microArch.cpp

@@ -154,6 +154,9 @@ class microArchImpl : public microArch
         if (op->theOperation == kLoadReply || op->theOperation == kAtomicPreloadReply) {
 
             bits val     = ValueTracker::valueTracker(theCPU.id()).load(theCPU.id(), op->thePAddr, op->theSize);
+            if (val == -1) {
+                op->theInstruction->forceResync(true);
+            }
             op->theValue = val;
             //      }
         } else if (op->theOperation == kRMWReply || op->theOperation == kCASReply) {