Question: Why do some x86 micro-ops in gem5 show >2 source operands?

[agirones]

Hi gem5 community,

I'm seeking some clarification regarding the number of source operands for certain x86 micro-ops as observed in gem5 traces.

While micro-ops are generally considered two-operand. I've noticed cases where micro-ops appear to consume more than two source operands. I've observed instances where the same physical register index is listed as a source operand more than once.

For instance, when tracing the mmulf instruction, its mulsd macro-op shows three source operands in the gem5 output, as detailed below:

Micro-op Instruction name: mmulf

Macro-op name: mulsd

Source Register type for source 0: 1

Source Physical register index for source 0: 10

Source Register type for source 1: 1

Source Physical register index for source 1: 48

Source Register type for source 2: 1

Source Physical register index for source 2: 10

Dest Register type for dest 0: 1

Dest Physical register index for dest 0: 49

Note: Register type 1 indicates a Floating Point Register

Could someone explain why this occurs? Is this a specific characteristic of certain floating-point or SIMD operations, a gem5-specific decomposition into micro-ops that exposes more implicit sources, or something else I'm misunderstanding about how x86 micro-architectural operations are represented?

Any insights or pointers to relevant documentation would be greatly appreciated.

Thanks!