[examples] Add stm32g0-lilos-node example

Author: mcbridejc

.github/workflows/rust.yml

@@ -28,3 +28,6 @@ jobs:
         run: cargo fmt --check
       - name: Run tests
         run: cargo test --verbose
+      - name: Build stm32g0-lilos-node example
+        working-directory: examples/stm32g0-lilos-node
+        run: cargo build

examples/stm32g0-lilos-node/.cargo/config.toml

@@ -0,0 +1,10 @@
+[target.'cfg(all(target_arch = "arm", target_os = "none"))']
+runner = "probe-rs run --always-print-stacktrace --chip STM32G0B1CBTx"
+
+rustflags = [
+  "-C", "link-arg=-Tlink.x",
+  "-C", "link-arg=-Tdefmt.x",
+]
+
+[build]
+target = "thumbv6m-none-eabi"

examples/stm32g0-lilos-node/Cargo.toml

@@ -0,0 +1,40 @@
+[package]
+name = "stm32g0-lilos-node"
+version = "0.1.0"
+edition = "2024"
+
+# Don't include this project in the workspace above it
+[workspace]
+
+[dependencies]
+# Local
+zencan-node = { path = "../../zencan-node", default-features = false, features = ["defmt"]}
+
+# External
+cortex-m = { version = "0.7.4", features=["critical-section-single-core"] }
+cortex-m-rt = "0.7.5"
+critical-section = "1.2.0"
+defmt = "1.0.1"
+embedded-io = "0.6.1"
+fdcan = { version = "0.2.1", features = ["fdcan_g0_g4_l5"] }
+stm32-metapac = { version = "15.0.0", features = ["stm32g0b1cb", "rt"] }
+hash32 = "1.0.0"
+lilos = "1.3"
+panic-probe = { version = "1.0.0", features = ["print-defmt"] }
+rtt-target = { version = "0.6.1", features = ["defmt"] }
+
+[build-dependencies]
+zencan-build = { path = "../../zencan-build" }
+
+[profile.dev]
+codegen-units = 1       # better optimizations
+debug = true
+lto = true              # better optimizations
+opt-level = "s"
+
+[profile.release]
+codegen-units = 1 # better optimizations
+debug = true # symbols are nice and they don't increase the size on Flash
+lto = true # better optimizations
+opt-level = "s"
+overflow-checks = true

examples/stm32g0-lilos-node/Embed.toml

@@ -0,0 +1,14 @@
+[default.general]
+chip = "STM32G0B1CBTx"
+
+[default.rtt]
+enabled = true
+up_channels = [
+    { channel = 0, name = "Defmt Output", up_mode = "NoBlockTrim", format = "Defmt" },
+]
+
+[connect.flashing]
+enabled = false
+
+[connect.reset]
+enabled = false

examples/stm32g0-lilos-node/README.md

@@ -0,0 +1,5 @@
+# stm32g0-lilos-node
+
+An example node targetting an STM32G0B1 cortex M0 MCU, using lilos as an async runtime.
+
+It reads ADC channels and stores them into objects.

examples/stm32g0-lilos-node/build.rs

@@ -0,0 +1,8 @@
+fn main() {
+    if let Err(e) =
+        zencan_build::build_node_from_device_config("ZENCAN_CONFIG", "zencan_config.toml")
+    {
+        eprintln!("Failed to parse zencan_config.toml: {}", e.to_string());
+        std::process::exit(-1);
+    }
+}

examples/stm32g0-lilos-node/memory.x

@@ -0,0 +1,7 @@
+MEMORY
+{
+  /* NOTE K = KiBi = 1024 bytes */
+  /* FLASH is 128k, but last two 2k pages are reserved for config data */
+  FLASH  (rx)  : ORIGIN = 0x08000000, LENGTH = 124K
+  RAM    (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
+}

examples/stm32g0-lilos-node/rust-toolchain.toml

@@ -0,0 +1,5 @@
+[toolchain]
+channel = "1.86"
+targets = [ "thumbv6m-none-eabi" ]
+profile = "default"
+components = [ "rustfmt", "rust-analyzer", "clippy", "llvm-tools" ]

examples/stm32g0-lilos-node/src/adc.rs

@@ -0,0 +1,57 @@
+use stm32_metapac as pac;
+
+/// Setup the ADC for reading the analog channels
+pub fn configure_adc() {
+    pac::RCC.apbenr2().modify(|w| w.set_adcen(true));
+    pac::ADC1.cr().modify(|w| {
+        w.set_advregen(true);
+    });
+
+    // Delay 1/40th of a second for regulator to turn on
+    cortex_m::asm::delay(16_000_000 / 40);
+
+    pac::ADC1.cr().modify(|w| w.set_adcal(true));
+
+    // Wait for calibration to complete
+    while pac::ADC1.cr().read().adcal() {}
+
+    // Clear ADRDY IRQ
+    pac::ADC1.isr().write(|w| w.set_adrdy(true));
+    // Enable
+    pac::ADC1.cr().modify(|w| w.set_aden(true));
+
+    // Wait for ADRDY signal
+    while !pac::ADC1.isr().read().adrdy() {}
+    // Clear the flag again
+    pac::ADC1.isr().write(|w| w.set_adrdy(true));
+
+    pac::ADC1.cfgr1().modify(|w| {
+        w.set_cont(false);
+    });
+
+    // Enable oversampling
+    pac::ADC1.cfgr2().modify(|w| {
+        w.set_ovse(true);
+        // 16x oversample
+        w.set_ovsr(3);
+        // shift by 4 bits
+        w.set_ovss(4);
+    });
+
+    pac::ADC1
+        .smpr()
+        .modify(|w| w.set_smp1(pac::adc::vals::SampleTime::CYCLES39_5));
+}
+
+pub fn read_adc(channel: usize) -> u16 {
+    // Configure channel
+    pac::ADC1.chselr().write(|w| w.set_chsel(1 << channel));
+    // Clear EOC
+    pac::ADC1.isr().write(|w| w.set_eoc(true));
+    // Start sampling
+    pac::ADC1.cr().modify(|w| w.set_adstart(true));
+    // Wait for complete
+    while !pac::ADC1.isr().read().eoc() {}
+    // Read result
+    pac::ADC1.dr().read().regular_data()
+}

examples/stm32g0-lilos-node/src/flash.rs

@@ -0,0 +1,210 @@
+//! Flash driver for STM32G0 family
+
+#![allow(dead_code)]
+
+use core::{
+    ptr::slice_from_raw_parts,
+    sync::atomic::{Ordering, fence},
+};
+
+use crate::{
+    pac::flash::Flash,
+    persist::{FlashAccess, Page},
+};
+
+const PAGE_SIZE: usize = 2048;
+
+pub struct FlashError {}
+
+pub struct Stm32g0Flash {
+    flash: Flash,
+
+    page_a: usize,
+    page_b: usize,
+}
+
+pub struct Stm32g0FlashUnlocked<'a> {
+    flash: &'a Flash,
+
+    cache: [u8; 8],
+    active_page: Page,
+
+    page_a: usize,
+    page_b: usize,
+
+    write_pos: usize,
+}
+
+impl Stm32g0Flash {
+    pub fn new(flash: Flash, page_a: usize, page_b: usize) -> Self {
+        Self {
+            flash,
+            page_a,
+            page_b,
+        }
+    }
+
+    fn page_slice(&self, n: usize) -> &[u8] {
+        let addr = (crate::pac::FLASH_BASE + n * PAGE_SIZE) as *const u8;
+        // Safety: I don't think the flash is going anywhere
+        unsafe { slice_from_raw_parts(addr, PAGE_SIZE).as_ref().unwrap() }
+    }
+
+    pub fn page(&self, page: Page) -> &[u8] {
+        match page {
+            Page::A => self.page_slice(self.page_a),
+            Page::B => self.page_slice(self.page_b),
+        }
+    }
+
+    pub fn unlock<'a>(&'a mut self) -> Stm32g0FlashUnlocked<'a> {
+        self.flash.keyr().write_value(0x45670123);
+        self.flash.keyr().write_value(0xCDEF89AB);
+        Stm32g0FlashUnlocked {
+            flash: &self.flash,
+            cache: [0; 8],
+            active_page: Page::A,
+            page_a: self.page_a,
+            page_b: self.page_b,
+            write_pos: 0,
+        }
+    }
+}
+
+impl<'a> Stm32g0FlashUnlocked<'a> {
+    pub fn lock(self) {
+        self.flash.cr().modify(|w| w.set_lock(true));
+    }
+}
+
+impl<'a> Drop for Stm32g0FlashUnlocked<'a> {
+    fn drop(&mut self) {
+        self.flash.cr().modify(|w| w.set_lock(true));
+    }
+}
+
+impl<'a> Stm32g0FlashUnlocked<'a> {
+    fn page_slice(&self, n: usize) -> &[u8] {
+        let addr = (crate::pac::FLASH_BASE + n * PAGE_SIZE) as *const u8;
+        // Safety: I don't think the flash is going anywhere
+        unsafe { slice_from_raw_parts(addr, PAGE_SIZE).as_ref().unwrap() }
+    }
+
+    fn page_ptr_mut(&mut self, n: usize, offset: usize) -> *mut u32 {
+        (crate::pac::FLASH_BASE + n * PAGE_SIZE + offset) as *mut u32
+    }
+
+    fn active_page_num(&self) -> usize {
+        match self.active_page {
+            Page::A => self.page_a,
+            Page::B => self.page_b,
+        }
+    }
+
+    fn write_cache(&mut self, offset: usize) {
+        let word1 = u32::from_le_bytes(self.cache[0..4].try_into().unwrap());
+        let word2 = u32::from_le_bytes(self.cache[4..8].try_into().unwrap());
+
+        let dst1 = self.page_ptr_mut(self.active_page_num(), offset);
+        let dst2 = self.page_ptr_mut(self.active_page_num(), offset + 4);
+        self.clear_errors();
+        self.wait_busy();
+
+        self.flash.cr().modify(|w| w.set_pg(true));
+
+        // Writing to flash must be done as a sequence of two 32-bit writes, starting on a 64-bit
+        // aligned address
+        fence(Ordering::SeqCst);
+        unsafe { core::ptr::write_volatile(dst1, word1) };
+        fence(Ordering::SeqCst);
+        unsafe { core::ptr::write_volatile(dst2, word2) };
+        fence(Ordering::SeqCst);
+        self.wait_busy();
+
+        self.flash.sr().write(|w| w.set_eop(true));
+        self.flash.cr().modify(|w| w.set_pg(false));
+    }
+
+    fn clear_errors(&mut self) -> u32 {
+        let sr = self.flash.sr().read().0;
+        // Clear error flags
+        self.flash.sr().modify(|w| {
+            w.set_fasterr(true);
+            w.set_miserr(true);
+            w.set_operr(true);
+            w.set_pgserr(true);
+            w.set_pgaerr(true);
+            w.set_progerr(true);
+            w.set_rderr(true);
+            w.set_sizerr(true);
+            w.set_wrperr(true);
+        });
+
+        sr
+    }
+
+    fn wait_busy(&mut self) {
+        // note: bsy() here is bsy1, bit 16
+        while self.flash.sr().read().bsy() {}
+    }
+}
+
+impl<'a> FlashAccess for Stm32g0FlashUnlocked<'a> {
+    type Error = FlashError;
+
+    fn page(&self, page: Page) -> &[u8] {
+        match page {
+            Page::A => self.page_slice(self.page_a),
+            Page::B => self.page_slice(self.page_b),
+        }
+    }
+
+    fn set_write_page(&mut self, page: Page) {
+        self.active_page = page;
+        self.write_pos = 0;
+    }
+
+    fn erase(&mut self) {
+        self.wait_busy();
+        self.clear_errors();
+
+        self.flash.cr().modify(|w| {
+            w.set_per(true);
+            w.set_pnb(self.active_page_num() as u8);
+        });
+        self.flash.cr().modify(|w| {
+            w.set_strt(true);
+        });
+
+        self.wait_busy();
+
+        self.flash.cr().modify(|w| w.set_per(false));
+    }
+
+    fn write(&mut self, data: &[u8]) {
+        // Data has to be written in 64-bit chunks, aligned to 64-bit words.
+
+        let mut in_pos = 0;
+
+        while in_pos < data.len() {
+            let buf_pos = self.write_pos % 8;
+            let to_copy = (8 - buf_pos).min(data.len() - in_pos);
+            self.cache[buf_pos..buf_pos + to_copy].copy_from_slice(&data[in_pos..in_pos + to_copy]);
+            in_pos += to_copy;
+            self.write_pos += to_copy;
+            if self.write_pos % 8 == 0 {
+                self.write_cache(self.write_pos - 8);
+            }
+        }
+    }
+
+    fn finalize(&mut self) {
+        // Pad remaining bytes with 0s
+        let buf_pos = self.write_pos % 8;
+        if buf_pos == 0 {
+            return;
+        }
+        self.cache[buf_pos..8].fill(0);
+        self.write_cache(self.write_pos & !0x7);
+    }
+}