From c650ad9a25f492f3011c6db416171d346d60b759 Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Mon, 13 May 2024 17:15:44 +0100 Subject: [PATCH 01/19] [AArch64][TargetParser] move ArchInfo into tablegen --- .../llvm/TargetParser/AArch64TargetParser.h | 48 +---- llvm/lib/Target/AArch64/AArch64Features.td | 174 ++++++++++-------- llvm/utils/TableGen/ARMTargetDefEmitter.cpp | 65 +++++++ 3 files changed, 163 insertions(+), 124 deletions(-) diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h b/llvm/include/llvm/TargetParser/AArch64TargetParser.h index 20c3f95173c28..0c89b7859975c 100644 --- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h +++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h @@ -238,8 +238,8 @@ enum ArchProfile { AProfile = 'A', RProfile = 'R', InvalidProfile = '?' }; struct ArchInfo { VersionTuple Version; // Architecture version, major + minor. ArchProfile Profile; // Architecuture profile - StringRef Name; // Human readable name, e.g. "armv8.1-a" - StringRef ArchFeature; // Command line feature flag, e.g. +v8a + StringRef Name; // Name as supplied to -march e.g. "armv8.1-a" + StringRef ArchFeature; // Name as supplied to -target-feature, e.g. "+v8a" AArch64::ExtensionBitset DefaultExts; // bitfield of default extensions ArchExtKind @@ -288,48 +288,8 @@ struct ArchInfo { static std::optional findBySubArch(StringRef SubArch); }; -// clang-format off -inline constexpr ArchInfo ARMV8A = { VersionTuple{8, 0}, AProfile, "armv8-a", "+v8a", ( - AArch64::ExtensionBitset({AArch64::AEK_FP, AArch64::AEK_SIMD})), }; -inline constexpr ArchInfo ARMV8_1A = { VersionTuple{8, 1}, AProfile, "armv8.1-a", "+v8.1a", (ARMV8A.DefaultExts | - AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_LSE, AArch64::AEK_RDM}))}; -inline constexpr ArchInfo ARMV8_2A = { VersionTuple{8, 2}, AProfile, "armv8.2-a", "+v8.2a", (ARMV8_1A.DefaultExts | - AArch64::ExtensionBitset({AArch64::AEK_RAS}))}; -inline constexpr ArchInfo ARMV8_3A = { VersionTuple{8, 3}, AProfile, "armv8.3-a", "+v8.3a", (ARMV8_2A.DefaultExts | - AArch64::ExtensionBitset({AArch64::AEK_FCMA, AArch64::AEK_JSCVT, AArch64::AEK_PAUTH, AArch64::AEK_RCPC}))}; -inline constexpr ArchInfo ARMV8_4A = { VersionTuple{8, 4}, AProfile, "armv8.4-a", "+v8.4a", (ARMV8_3A.DefaultExts | - AArch64::ExtensionBitset({AArch64::AEK_DOTPROD}))}; -inline constexpr ArchInfo ARMV8_5A = { VersionTuple{8, 5}, AProfile, "armv8.5-a", "+v8.5a", (ARMV8_4A.DefaultExts)}; -inline constexpr ArchInfo ARMV8_6A = { VersionTuple{8, 6}, AProfile, "armv8.6-a", "+v8.6a", (ARMV8_5A.DefaultExts | - AArch64::ExtensionBitset({AArch64::AEK_BF16, AArch64::AEK_I8MM}))}; -inline constexpr ArchInfo ARMV8_7A = { VersionTuple{8, 7}, AProfile, "armv8.7-a", "+v8.7a", (ARMV8_6A.DefaultExts)}; -inline constexpr ArchInfo ARMV8_8A = { VersionTuple{8, 8}, AProfile, "armv8.8-a", "+v8.8a", (ARMV8_7A.DefaultExts | - AArch64::ExtensionBitset({AArch64::AEK_MOPS, AArch64::AEK_HBC}))}; -inline constexpr ArchInfo ARMV8_9A = { VersionTuple{8, 9}, AProfile, "armv8.9-a", "+v8.9a", (ARMV8_8A.DefaultExts | - AArch64::ExtensionBitset({AArch64::AEK_SPECRES2, AArch64::AEK_CSSC, AArch64::AEK_RASV2}))}; -inline constexpr ArchInfo ARMV9A = { VersionTuple{9, 0}, AProfile, "armv9-a", "+v9a", (ARMV8_5A.DefaultExts | - AArch64::ExtensionBitset({AArch64::AEK_FP16, AArch64::AEK_SVE, AArch64::AEK_SVE2}))}; -inline constexpr ArchInfo ARMV9_1A = { VersionTuple{9, 1}, AProfile, "armv9.1-a", "+v9.1a", (ARMV9A.DefaultExts | - AArch64::ExtensionBitset({AArch64::AEK_BF16, AArch64::AEK_I8MM}))}; -inline constexpr ArchInfo ARMV9_2A = { VersionTuple{9, 2}, AProfile, "armv9.2-a", "+v9.2a", (ARMV9_1A.DefaultExts)}; -inline constexpr ArchInfo ARMV9_3A = { VersionTuple{9, 3}, AProfile, "armv9.3-a", "+v9.3a", (ARMV9_2A.DefaultExts | - AArch64::ExtensionBitset({AArch64::AEK_MOPS, AArch64::AEK_HBC}))}; -inline constexpr ArchInfo ARMV9_4A = { VersionTuple{9, 4}, AProfile, "armv9.4-a", "+v9.4a", (ARMV9_3A.DefaultExts | - AArch64::ExtensionBitset({AArch64::AEK_SPECRES2, AArch64::AEK_CSSC, AArch64::AEK_RASV2}))}; -inline constexpr ArchInfo ARMV9_5A = { VersionTuple{9, 5}, AProfile, "armv9.5-a", "+v9.5a", (ARMV9_4A.DefaultExts | - AArch64::ExtensionBitset({AArch64::AEK_CPA}))}; -// For v8-R, we do not enable crypto and align with GCC that enables a more minimal set of optional architecture extensions. -inline constexpr ArchInfo ARMV8R = { VersionTuple{8, 0}, RProfile, "armv8-r", "+v8r", (ARMV8_5A.DefaultExts | - AArch64::ExtensionBitset({AArch64::AEK_SSBS, - AArch64::AEK_FP16, AArch64::AEK_FP16FML, AArch64::AEK_SB}).flip(AArch64::AEK_LSE))}; -// clang-format on - -// The set of all architectures -static constexpr std::array ArchInfos = { - &ARMV8A, &ARMV8_1A, &ARMV8_2A, &ARMV8_3A, &ARMV8_4A, &ARMV8_5A, - &ARMV8_6A, &ARMV8_7A, &ARMV8_8A, &ARMV8_9A, &ARMV9A, &ARMV9_1A, - &ARMV9_2A, &ARMV9_3A, &ARMV9_4A, &ARMV9_5A, &ARMV8R, -}; +#define EMIT_ARCHITECTURES +#include "llvm/TargetParser/AArch64TargetParserDef.inc" // Details of a specific CPU. struct CpuInfo { diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td index 920ca7f4fbfcb..e615ea9b1cede 100644 --- a/llvm/lib/Target/AArch64/AArch64Features.td +++ b/llvm/lib/Target/AArch64/AArch64Features.td @@ -787,90 +787,104 @@ def FeatureTLBIW : Extension<"tlbiw", "TLBIW", //===----------------------------------------------------------------------===// // Architectures. // -def HasV8_0aOps : SubtargetFeature<"v8a", "HasV8_0aOps", "true", - "Support ARM v8.0a instructions", [FeatureEL2VMSA, FeatureEL3]>; - -def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true", - "Support ARM v8.1a instructions", [HasV8_0aOps, FeatureCRC, FeatureLSE, - FeatureRDM, FeaturePAN, FeatureLOR, FeatureVH]>; - -def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true", - "Support ARM v8.2a instructions", [HasV8_1aOps, FeaturePsUAO, - FeaturePAN_RWV, FeatureRAS, FeatureCCPP]>; - -def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true", - "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC, FeaturePAuth, - FeatureJS, FeatureCCIDX, FeatureComplxNum]>; - -def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true", - "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd, - FeatureNV, FeatureMPAM, FeatureDIT, - FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeatureTLB_RMI, - FeatureFlagM, FeatureRCPC_IMMO, FeatureLSE2]>; +class Architecture64< + int major, int minor, string profile, + string target_feature_name, + list implied_features, + list default_extensions +> : SubtargetFeature { + int Major = major; + int Minor = minor; + string Profile = profile; + + // Extensions enabled by default. Not the same as implied SubtargetFeatures. + list DefaultExts = default_extensions; +} -def HasV8_5aOps : SubtargetFeature< - "v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions", +def HasV8_0aOps : Architecture64<8, 0, "a", "v8a", + [FeatureEL2VMSA, FeatureEL3], + [FeatureFPARMv8, FeatureNEON]>; +def HasV8_1aOps : Architecture64<8, 1, "a", "v8.1a", + [HasV8_0aOps, FeatureCRC, FeatureLSE, FeatureRDM, FeaturePAN, FeatureLOR, + FeatureVH], + !listconcat(HasV8_0aOps.DefaultExts, [FeatureCRC, FeatureLSE, FeatureRDM])>; +def HasV8_2aOps : Architecture64<8, 2, "a", "v8.2a", + [HasV8_1aOps, FeaturePsUAO, FeaturePAN_RWV, FeatureRAS, FeatureCCPP], + !listconcat(HasV8_1aOps.DefaultExts, [FeatureRAS])>; +def HasV8_3aOps : Architecture64<8, 3, "a", "v8.3a", + [HasV8_2aOps, FeatureRCPC, FeaturePAuth, FeatureJS, FeatureCCIDX, + FeatureComplxNum], + !listconcat(HasV8_2aOps.DefaultExts, [FeatureComplxNum, FeatureJS, + FeaturePAuth, FeatureRCPC])>; +def HasV8_4aOps : Architecture64<8, 4, "a", "v8.4a", + [HasV8_3aOps, FeatureDotProd, FeatureNV, FeatureMPAM, FeatureDIT, + FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeatureTLB_RMI, FeatureFlagM, + FeatureRCPC_IMMO, FeatureLSE2], + !listconcat(HasV8_3aOps.DefaultExts, [FeatureDotProd])>; +def HasV8_5aOps : Architecture64<8, 5, "a", "v8.5a", [HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict, - FeatureSSBS, FeatureSB, FeaturePredRes, FeatureCacheDeepPersist, - FeatureBranchTargetId]>; - -def HasV8_6aOps : SubtargetFeature< - "v8.6a", "HasV8_6aOps", "true", "Support ARM v8.6a instructions", + FeatureSSBS, FeatureSB, FeaturePredRes, FeatureCacheDeepPersist, + FeatureBranchTargetId], + !listconcat(HasV8_4aOps.DefaultExts, [])>; +def HasV8_6aOps : Architecture64<8, 6, "a", "v8.6a", [HasV8_5aOps, FeatureAMVS, FeatureBF16, FeatureFineGrainedTraps, - FeatureEnhancedCounterVirtualization, FeatureMatMulInt8]>; - -def HasV8_7aOps : SubtargetFeature< - "v8.7a", "HasV8_7aOps", "true", "Support ARM v8.7a instructions", - [HasV8_6aOps, FeatureXS, FeatureWFxT, FeatureHCX]>; - -def HasV8_8aOps : SubtargetFeature< - "v8.8a", "HasV8_8aOps", "true", "Support ARM v8.8a instructions", - [HasV8_7aOps, FeatureHBC, FeatureMOPS, FeatureNMI]>; - -def HasV8_9aOps : SubtargetFeature< - "v8.9a", "HasV8_9aOps", "true", "Support ARM v8.9a instructions", + FeatureEnhancedCounterVirtualization, FeatureMatMulInt8], + !listconcat(HasV8_5aOps.DefaultExts, [FeatureBF16, FeatureMatMulInt8])>; +def HasV8_7aOps : Architecture64<8, 7, "a", "v8.7a", + [HasV8_6aOps, FeatureXS, FeatureWFxT, FeatureHCX], + !listconcat(HasV8_6aOps.DefaultExts, [])>; +def HasV8_8aOps : Architecture64<8, 8, "a", "v8.8a", + [HasV8_7aOps, FeatureHBC, FeatureMOPS, FeatureNMI], + !listconcat(HasV8_7aOps.DefaultExts, [FeatureMOPS, FeatureHBC])>; +def HasV8_9aOps : Architecture64<8, 9, "a", "v8.9a", [HasV8_8aOps, FeatureCLRBHB, FeaturePRFM_SLC, FeatureSPECRES2, - FeatureCSSC, FeatureRASv2, FeatureCHK]>; - -def HasV9_0aOps : SubtargetFeature< - "v9a", "HasV9_0aOps", "true", "Support ARM v9a instructions", - [HasV8_5aOps, FeatureMEC, FeatureSVE2]>; - -def HasV9_1aOps : SubtargetFeature< - "v9.1a", "HasV9_1aOps", "true", "Support ARM v9.1a instructions", - [HasV8_6aOps, HasV9_0aOps]>; - -def HasV9_2aOps : SubtargetFeature< - "v9.2a", "HasV9_2aOps", "true", "Support ARM v9.2a instructions", - [HasV8_7aOps, HasV9_1aOps]>; - -def HasV9_3aOps : SubtargetFeature< - "v9.3a", "HasV9_3aOps", "true", "Support ARM v9.3a instructions", - [HasV8_8aOps, HasV9_2aOps]>; - -def HasV9_4aOps : SubtargetFeature< - "v9.4a", "HasV9_4aOps", "true", "Support ARM v9.4a instructions", - [HasV8_9aOps, HasV9_3aOps]>; - -def HasV9_5aOps : SubtargetFeature< - "v9.5a", "HasV9_5aOps", "true", "Support ARM v9.5a instructions", - [HasV9_4aOps, FeatureCPA]>; - -def HasV8_0rOps : SubtargetFeature< - "v8r", "HasV8_0rOps", "true", "Support ARM v8r instructions", - [//v8.1 - FeatureCRC, FeaturePAN, FeatureLSE, FeatureCONTEXTIDREL2, - //v8.2 - FeatureRAS, FeaturePsUAO, FeatureCCPP, FeaturePAN_RWV, - //v8.3 - FeatureCCIDX, FeaturePAuth, FeatureRCPC, - //v8.4 - FeatureTRACEV8_4, FeatureTLB_RMI, FeatureFlagM, FeatureDIT, FeatureSEL2, - FeatureRCPC_IMMO, - // Not mandatory in v8.0-R, but included here on the grounds that it - // only enables names of system registers - FeatureSpecRestrict - ]>; + FeatureCSSC, FeatureRASv2, FeatureCHK], + !listconcat(HasV8_8aOps.DefaultExts, [FeatureSPECRES2, FeatureCSSC, + FeatureRASv2])>; +def HasV9_0aOps : Architecture64<9, 0, "a", "v9a", + [HasV8_5aOps, FeatureMEC, FeatureSVE2], + !listconcat(HasV8_5aOps.DefaultExts, [FeatureFullFP16, FeatureSVE, + FeatureSVE2])>; +def HasV9_1aOps : Architecture64<9, 1, "a", "v9.1a", + [HasV8_6aOps, HasV9_0aOps], + !listconcat(HasV9_0aOps.DefaultExts, [FeatureBF16, FeatureMatMulInt8])>; +def HasV9_2aOps : Architecture64<9, 2, "a", "v9.2a", + [HasV8_7aOps, HasV9_1aOps], + !listconcat(HasV9_1aOps.DefaultExts, [])>; +def HasV9_3aOps : Architecture64<9, 3, "a", "v9.3a", + [HasV8_8aOps, HasV9_2aOps], + !listconcat(HasV9_2aOps.DefaultExts, [FeatureMOPS, FeatureHBC])>; +def HasV9_4aOps : Architecture64<9, 4, "a", "v9.4a", + [HasV8_9aOps, HasV9_3aOps], + !listconcat(HasV9_3aOps.DefaultExts, [FeatureSPECRES2, FeatureCSSC, + FeatureRASv2])>; +def HasV9_5aOps : Architecture64<9, 5, "a", "v9.5a", + [HasV9_4aOps, FeatureCPA], + !listconcat(HasV9_4aOps.DefaultExts, [FeatureCPA])>; +def HasV8_0rOps : Architecture64<8, 0, "r", "v8r", + [ //v8.1 + FeatureCRC, FeaturePAN, FeatureLSE, FeatureCONTEXTIDREL2, + //v8.2 + FeatureRAS, FeaturePsUAO, FeatureCCPP, FeaturePAN_RWV, + //v8.3 + FeatureCCIDX, FeaturePAuth, FeatureRCPC, + //v8.4 + FeatureTRACEV8_4, FeatureTLB_RMI, FeatureFlagM, FeatureDIT, FeatureSEL2, + FeatureRCPC_IMMO, + // Not mandatory in v8.0-R, but included here on the grounds that it + // only enables names of system registers + FeatureSpecRestrict + ], + // For v8-R, we do not enable crypto and align with GCC that enables a more + // minimal set of optional architecture extensions. + !listconcat( + !listremove(HasV8_5aOps.DefaultExts, [FeatureLSE]), + [FeatureSSBS, FeatureFullFP16, FeatureFP16FML, FeatureSB] + )>; //===----------------------------------------------------------------------===// // Access to privileged registers diff --git a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp index 4a46f2ea95869..70050020865e0 100644 --- a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp +++ b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp @@ -13,9 +13,12 @@ //===----------------------------------------------------------------------===// #include "llvm/ADT/StringSet.h" +#include "llvm/Support/Format.h" +#include "llvm/TableGen/Error.h" #include "llvm/TableGen/Record.h" #include "llvm/TableGen/TableGenBackend.h" #include +#include using namespace llvm; @@ -108,6 +111,68 @@ static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream &OS) { << "#undef EMIT_EXTENSIONS\n" << "#endif // EMIT_EXTENSIONS\n" << "\n"; + + // Emit architecture information + OS << "#ifdef EMIT_ARCHITECTURES\n"; + + auto Architectures = RK.getAllDerivedDefinitionsIfDefined("Architecture64"); + std::vector CppSpellings; + for (const Record *Rec : Architectures) { + const int Major = Rec->getValueAsInt("Major"); + const int Minor = Rec->getValueAsInt("Minor"); + const std::string ProfileLower = Rec->getValueAsString("Profile").str(); + const std::string ProfileUpper = Rec->getValueAsString("Profile").upper(); + + if (ProfileLower != "a" && ProfileLower != "r") + PrintFatalError(Rec->getLoc(), + "error: Profile must be one of 'a' or 'r', got '" + + ProfileLower + "'"); + + // Name of the object in C++ + const std::string CppSpelling = + Minor == 0 ? "ARMV" + std::to_string(Major) + ProfileUpper.c_str() + : "ARMV" + std::to_string(Major) + "_" + + std::to_string(Minor) + ProfileUpper.c_str(); + OS << "inline constexpr ArchInfo " << CppSpelling << " = {\n"; + CppSpellings.push_back(CppSpelling); + + OS << llvm::format(" VersionTuple{%d, %d},\n", Major, Minor); + OS << llvm::format(" %sProfile,\n", ProfileUpper.c_str()); + + // Name as spelled for -march. + if (Minor == 0) + OS << llvm::format(" \"armv%d-%s\",\n", Major, ProfileLower.c_str()); + else + OS << llvm::format(" \"armv%d.%d-%s\",\n", Major, Minor, + ProfileLower.c_str()); + + // SubtargetFeature::Name, used for -target-feature. Here the "+" is added. + const auto TargetFeatureName = Rec->getValueAsString("Name"); + OS << " \"+" << TargetFeatureName << "\",\n"; + + // Construct the list of default extensions + OS << " (AArch64::ExtensionBitset({"; + for (auto *E : Rec->getValueAsListOfDefs("DefaultExts")) { + // Only process subclasses of Extension + OS << "AArch64::" << E->getValueAsString("ArchExtKindSpelling").upper() + << ", "; + } + OS << "}))\n"; + + OS << "};\n"; + } + + OS << "\n" + << "/// The set of all architectures\n" + << "static constexpr std::array ArchInfos = {\n"; + for (auto CppSpelling : CppSpellings) + OS << " &" << CppSpelling << ",\n"; + OS << "};\n"; + + OS << "#undef EMIT_ARCHITECTURES\n" + << "#endif // EMIT_ARCHITECTURES\n" + << "\n"; } static TableGen::Emitter::Opt From 52b8af6cde23d6ceacbc33f292e0bff1265501b5 Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Tue, 14 May 2024 17:20:45 +0100 Subject: [PATCH 02/19] [AArch64][TargetParser] move CPUInfo into tablegen --- .../llvm/TargetParser/AArch64TargetParser.h | 319 +------------- llvm/lib/Target/AArch64/AArch64Processors.td | 399 +++++++++++------- llvm/utils/TableGen/ARMTargetDefEmitter.cpp | 41 +- 3 files changed, 285 insertions(+), 474 deletions(-) diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h b/llvm/include/llvm/TargetParser/AArch64TargetParser.h index 0c89b7859975c..2402f02ab99c1 100644 --- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h +++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h @@ -307,323 +307,8 @@ struct CpuInfo { } }; -inline constexpr CpuInfo CpuInfos[] = { - {"cortex-a34", ARMV8A, - AArch64::ExtensionBitset( - {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_CRC})}, - {"cortex-a35", ARMV8A, - AArch64::ExtensionBitset( - {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_CRC})}, - {"cortex-a53", ARMV8A, - AArch64::ExtensionBitset( - {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_CRC})}, - {"cortex-a55", ARMV8_2A, - AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_FP16, AArch64::AEK_DOTPROD, - AArch64::AEK_RCPC})}, - {"cortex-a510", ARMV9A, - AArch64::ExtensionBitset( - {AArch64::AEK_BF16, AArch64::AEK_I8MM, AArch64::AEK_SB, - AArch64::AEK_PAUTH, AArch64::AEK_MTE, AArch64::AEK_SSBS, - AArch64::AEK_SVE, AArch64::AEK_SVE2, AArch64::AEK_SVE2BITPERM, - AArch64::AEK_FP16FML})}, - {"cortex-a520", ARMV9_2A, - AArch64::ExtensionBitset( - {AArch64::AEK_SB, AArch64::AEK_SSBS, AArch64::AEK_MTE, - AArch64::AEK_FP16FML, AArch64::AEK_PAUTH, AArch64::AEK_SVE2BITPERM, - AArch64::AEK_FLAGM, AArch64::AEK_PERFMON, AArch64::AEK_PREDRES})}, - {"cortex-a520ae", ARMV9_2A, - AArch64::ExtensionBitset( - {AArch64::AEK_SB, AArch64::AEK_SSBS, AArch64::AEK_MTE, - AArch64::AEK_FP16FML, AArch64::AEK_PAUTH, AArch64::AEK_SVE2BITPERM, - AArch64::AEK_FLAGM, AArch64::AEK_PERFMON, AArch64::AEK_PREDRES})}, - {"cortex-a57", ARMV8A, - AArch64::ExtensionBitset( - {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_CRC})}, - {"cortex-a65", ARMV8_2A, - AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_DOTPROD, AArch64::AEK_FP16, - AArch64::AEK_RCPC, AArch64::AEK_SSBS})}, - {"cortex-a65ae", ARMV8_2A, - AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_DOTPROD, AArch64::AEK_FP16, - AArch64::AEK_RCPC, AArch64::AEK_SSBS})}, - {"cortex-a72", ARMV8A, - AArch64::ExtensionBitset( - {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_CRC})}, - {"cortex-a73", ARMV8A, - AArch64::ExtensionBitset( - {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_CRC})}, - {"cortex-a75", ARMV8_2A, - AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_FP16, AArch64::AEK_DOTPROD, - AArch64::AEK_RCPC})}, - {"cortex-a76", ARMV8_2A, - AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_FP16, AArch64::AEK_DOTPROD, - AArch64::AEK_RCPC, AArch64::AEK_SSBS})}, - {"cortex-a76ae", ARMV8_2A, - AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_FP16, AArch64::AEK_DOTPROD, - AArch64::AEK_RCPC, AArch64::AEK_SSBS})}, - {"cortex-a77", ARMV8_2A, - AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_FP16, AArch64::AEK_RCPC, - AArch64::AEK_DOTPROD, AArch64::AEK_SSBS})}, - {"cortex-a78", ARMV8_2A, - AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_FP16, AArch64::AEK_DOTPROD, - AArch64::AEK_RCPC, AArch64::AEK_SSBS, - AArch64::AEK_PROFILE})}, - {"cortex-a78ae", ARMV8_2A, - AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_FP16, AArch64::AEK_DOTPROD, - AArch64::AEK_RCPC, AArch64::AEK_SSBS, - AArch64::AEK_PROFILE})}, - {"cortex-a78c", ARMV8_2A, - AArch64::ExtensionBitset( - {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP16, - AArch64::AEK_DOTPROD, AArch64::AEK_RCPC, AArch64::AEK_SSBS, - AArch64::AEK_PROFILE, AArch64::AEK_FLAGM, AArch64::AEK_PAUTH})}, - {"cortex-a710", ARMV9A, - AArch64::ExtensionBitset({AArch64::AEK_MTE, AArch64::AEK_PAUTH, - AArch64::AEK_FLAGM, AArch64::AEK_SB, - AArch64::AEK_I8MM, AArch64::AEK_FP16FML, - AArch64::AEK_SVE, AArch64::AEK_SVE2, - AArch64::AEK_SVE2BITPERM, AArch64::AEK_BF16})}, - {"cortex-a715", ARMV9A, - AArch64::ExtensionBitset( - {AArch64::AEK_SB, AArch64::AEK_SSBS, AArch64::AEK_MTE, - AArch64::AEK_FP16, AArch64::AEK_FP16FML, AArch64::AEK_PAUTH, - AArch64::AEK_I8MM, AArch64::AEK_PREDRES, AArch64::AEK_PERFMON, - AArch64::AEK_PROFILE, AArch64::AEK_SVE, AArch64::AEK_SVE2BITPERM, - AArch64::AEK_BF16, AArch64::AEK_FLAGM})}, - {"cortex-a720", ARMV9_2A, - AArch64::ExtensionBitset({AArch64::AEK_SB, AArch64::AEK_SSBS, - AArch64::AEK_MTE, AArch64::AEK_FP16FML, - AArch64::AEK_PAUTH, AArch64::AEK_SVE2BITPERM, - AArch64::AEK_FLAGM, AArch64::AEK_PERFMON, - AArch64::AEK_PREDRES, AArch64::AEK_PROFILE})}, - {"cortex-a720ae", ARMV9_2A, - AArch64::ExtensionBitset({AArch64::AEK_SB, AArch64::AEK_SSBS, - AArch64::AEK_MTE, AArch64::AEK_FP16FML, - AArch64::AEK_PAUTH, AArch64::AEK_SVE2BITPERM, - AArch64::AEK_FLAGM, AArch64::AEK_PERFMON, - AArch64::AEK_PREDRES, AArch64::AEK_PROFILE})}, - {"cortex-r82", ARMV8R, - AArch64::ExtensionBitset({AArch64::AEK_LSE, AArch64::AEK_FLAGM, - AArch64::AEK_PERFMON, AArch64::AEK_PREDRES})}, - {"cortex-r82ae", ARMV8R, - AArch64::ExtensionBitset({AArch64::AEK_LSE, AArch64::AEK_FLAGM, - AArch64::AEK_PERFMON, AArch64::AEK_PREDRES})}, - {"cortex-x1", ARMV8_2A, - AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_FP16, AArch64::AEK_DOTPROD, - AArch64::AEK_RCPC, AArch64::AEK_SSBS, - AArch64::AEK_PROFILE})}, - {"cortex-x1c", ARMV8_2A, - AArch64::ExtensionBitset( - {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP16, - AArch64::AEK_DOTPROD, AArch64::AEK_RCPC, AArch64::AEK_SSBS, - AArch64::AEK_PAUTH, AArch64::AEK_PROFILE, AArch64::AEK_FLAGM})}, - {"cortex-x2", ARMV9A, - AArch64::ExtensionBitset( - {AArch64::AEK_MTE, AArch64::AEK_BF16, AArch64::AEK_I8MM, - AArch64::AEK_PAUTH, AArch64::AEK_SSBS, AArch64::AEK_SB, - AArch64::AEK_SVE, AArch64::AEK_SVE2, AArch64::AEK_SVE2BITPERM, - AArch64::AEK_FP16FML, AArch64::AEK_FLAGM})}, - {"cortex-x3", ARMV9A, - AArch64::ExtensionBitset( - {AArch64::AEK_SVE, AArch64::AEK_PERFMON, AArch64::AEK_PROFILE, - AArch64::AEK_BF16, AArch64::AEK_I8MM, AArch64::AEK_MTE, - AArch64::AEK_SVE2BITPERM, AArch64::AEK_SB, AArch64::AEK_PAUTH, - AArch64::AEK_FP16, AArch64::AEK_FP16FML, AArch64::AEK_PREDRES, - AArch64::AEK_FLAGM, AArch64::AEK_SSBS})}, - {"cortex-x4", ARMV9_2A, - AArch64::ExtensionBitset({AArch64::AEK_SB, AArch64::AEK_SSBS, - AArch64::AEK_MTE, AArch64::AEK_FP16FML, - AArch64::AEK_PAUTH, AArch64::AEK_SVE2BITPERM, - AArch64::AEK_FLAGM, AArch64::AEK_PERFMON, - AArch64::AEK_PREDRES, AArch64::AEK_PROFILE})}, - {"neoverse-e1", ARMV8_2A, - AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_DOTPROD, AArch64::AEK_FP16, - AArch64::AEK_RCPC, AArch64::AEK_SSBS})}, - {"neoverse-n1", ARMV8_2A, - AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_DOTPROD, AArch64::AEK_FP16, - AArch64::AEK_PROFILE, AArch64::AEK_RCPC, - AArch64::AEK_SSBS})}, - {"neoverse-n2", ARMV9A, - AArch64::ExtensionBitset( - {AArch64::AEK_BF16, AArch64::AEK_DOTPROD, AArch64::AEK_FP16, - AArch64::AEK_FP16FML, AArch64::AEK_I8MM, AArch64::AEK_MTE, - AArch64::AEK_SB, AArch64::AEK_SSBS, AArch64::AEK_SVE, - AArch64::AEK_SVE2, AArch64::AEK_SVE2BITPERM})}, - {"neoverse-n3", ARMV9_2A, - AArch64::ExtensionBitset({AArch64::AEK_MTE, AArch64::AEK_SSBS, - AArch64::AEK_SB, AArch64::AEK_PREDRES, - AArch64::AEK_FP16FML, AArch64::AEK_PAUTH, - AArch64::AEK_FLAGM, AArch64::AEK_PERFMON, - AArch64::AEK_RAND, AArch64::AEK_SVE2BITPERM, - AArch64::AEK_PROFILE, AArch64::AEK_PERFMON})}, - {"neoverse-512tvb", ARMV8_4A, - AArch64::ExtensionBitset( - {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_SHA3, - AArch64::AEK_SM4, AArch64::AEK_SVE, AArch64::AEK_SSBS, - AArch64::AEK_FP16, AArch64::AEK_BF16, AArch64::AEK_DOTPROD, - AArch64::AEK_PROFILE, AArch64::AEK_RAND, AArch64::AEK_FP16FML, - AArch64::AEK_I8MM})}, - {"neoverse-v1", ARMV8_4A, - AArch64::ExtensionBitset( - {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_SHA3, - AArch64::AEK_SM4, AArch64::AEK_SVE, AArch64::AEK_SSBS, - AArch64::AEK_FP16, AArch64::AEK_BF16, AArch64::AEK_DOTPROD, - AArch64::AEK_PROFILE, AArch64::AEK_RAND, AArch64::AEK_FP16FML, - AArch64::AEK_I8MM})}, - {"neoverse-v2", ARMV9A, - AArch64::ExtensionBitset( - {AArch64::AEK_SVE, AArch64::AEK_SVE2, AArch64::AEK_SSBS, - AArch64::AEK_FP16, AArch64::AEK_BF16, AArch64::AEK_RAND, - AArch64::AEK_DOTPROD, AArch64::AEK_PROFILE, AArch64::AEK_SVE2BITPERM, - AArch64::AEK_FP16FML, AArch64::AEK_I8MM, AArch64::AEK_MTE})}, - {"neoverse-v3", ARMV9_2A, - AArch64::ExtensionBitset( - {AArch64::AEK_PROFILE, AArch64::AEK_MTE, AArch64::AEK_SSBS, - AArch64::AEK_SB, AArch64::AEK_PREDRES, AArch64::AEK_LS64, - AArch64::AEK_BRBE, AArch64::AEK_PAUTH, AArch64::AEK_FLAGM, - AArch64::AEK_PERFMON, AArch64::AEK_RAND, AArch64::AEK_SVE2BITPERM, - AArch64::AEK_FP16FML})}, - {"neoverse-v3ae", ARMV9_2A, - (AArch64::ExtensionBitset( - {AArch64::AEK_PROFILE, AArch64::AEK_MTE, AArch64::AEK_SSBS, - AArch64::AEK_SB, AArch64::AEK_PREDRES, AArch64::AEK_LS64, - AArch64::AEK_BRBE, AArch64::AEK_PAUTH, AArch64::AEK_FLAGM, - AArch64::AEK_PERFMON, AArch64::AEK_RAND, AArch64::AEK_SVE2BITPERM, - AArch64::AEK_FP16FML}))}, - {"cyclone", ARMV8A, - AArch64::ExtensionBitset( - {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_NONE})}, - {"apple-a7", ARMV8A, - AArch64::ExtensionBitset( - {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_NONE})}, - {"apple-a8", ARMV8A, - AArch64::ExtensionBitset( - {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_NONE})}, - {"apple-a9", ARMV8A, - AArch64::ExtensionBitset( - {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_NONE})}, - {"apple-a10", ARMV8A, - AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_CRC, AArch64::AEK_RDM})}, - {"apple-a11", ARMV8_2A, - AArch64::ExtensionBitset( - {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP16})}, - {"apple-a12", ARMV8_3A, - AArch64::ExtensionBitset( - {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP16})}, - {"apple-a13", ARMV8_4A, - AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_SHA3, AArch64::AEK_FP16, - AArch64::AEK_FP16FML})}, - {"apple-a14", ARMV8_5A, - AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_SHA3, AArch64::AEK_FP16, - AArch64::AEK_FP16FML})}, - {"apple-a15", ARMV8_6A, - AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_SHA3, AArch64::AEK_FP16, - AArch64::AEK_FP16FML})}, - {"apple-a16", ARMV8_6A, - AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_SHA3, AArch64::AEK_FP16, - AArch64::AEK_FP16FML})}, - {"apple-a17", ARMV8_6A, - AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_SHA3, AArch64::AEK_FP16, - AArch64::AEK_FP16FML})}, - - {"apple-m1", ARMV8_5A, - AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_SHA3, AArch64::AEK_FP16, - AArch64::AEK_FP16FML})}, - {"apple-m2", ARMV8_6A, - AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_SHA3, AArch64::AEK_FP16, - AArch64::AEK_FP16FML})}, - {"apple-m3", ARMV8_6A, - AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_SHA3, AArch64::AEK_FP16, - AArch64::AEK_FP16FML})}, - - {"apple-s4", ARMV8_3A, - AArch64::ExtensionBitset( - {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP16})}, - {"apple-s5", ARMV8_3A, - AArch64::ExtensionBitset( - {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP16})}, - {"exynos-m3", ARMV8A, - AArch64::ExtensionBitset( - {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_CRC})}, - {"exynos-m4", ARMV8_2A, - AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_DOTPROD, AArch64::AEK_FP16})}, - {"exynos-m5", ARMV8_2A, - AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_DOTPROD, AArch64::AEK_FP16})}, - {"falkor", ARMV8A, - AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_CRC, AArch64::AEK_RDM})}, - {"saphira", ARMV8_3A, - AArch64::ExtensionBitset( - {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_PROFILE})}, - {"kryo", ARMV8A, - AArch64::ExtensionBitset( - {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_CRC})}, - {"thunderx2t99", ARMV8_1A, - AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2})}, - {"thunderx3t110", ARMV8_3A, - AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2})}, - {"thunderx", ARMV8A, - AArch64::ExtensionBitset( - {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_CRC})}, - {"thunderxt88", ARMV8A, - AArch64::ExtensionBitset( - {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_CRC})}, - {"thunderxt81", ARMV8A, - AArch64::ExtensionBitset( - {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_CRC})}, - {"thunderxt83", ARMV8A, - AArch64::ExtensionBitset( - {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_CRC})}, - {"tsv110", ARMV8_2A, - AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_DOTPROD, AArch64::AEK_FP16, - AArch64::AEK_FP16FML, AArch64::AEK_PROFILE, - AArch64::AEK_JSCVT, AArch64::AEK_FCMA})}, - {"a64fx", ARMV8_2A, - AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_FP16, AArch64::AEK_SVE})}, - {"carmel", ARMV8_2A, - AArch64::ExtensionBitset( - {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP16})}, - {"ampere1", ARMV8_6A, - AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_SHA3, AArch64::AEK_FP16, - AArch64::AEK_SB, AArch64::AEK_SSBS, - AArch64::AEK_RAND})}, - {"ampere1a", ARMV8_6A, - AArch64::ExtensionBitset( - {AArch64::AEK_FP16, AArch64::AEK_RAND, AArch64::AEK_SM4, - AArch64::AEK_SHA3, AArch64::AEK_SHA2, AArch64::AEK_AES, - AArch64::AEK_MTE, AArch64::AEK_SB, AArch64::AEK_SSBS})}, - {"ampere1b", ARMV8_7A, - AArch64::ExtensionBitset({AArch64::AEK_FP16, AArch64::AEK_RAND, - AArch64::AEK_SM4, AArch64::AEK_SHA3, - AArch64::AEK_SHA2, AArch64::AEK_AES, - AArch64::AEK_MTE, AArch64::AEK_SB, - AArch64::AEK_SSBS, AArch64::AEK_CSSC})}, -}; +#define EMIT_CPU_INFO +#include "llvm/TargetParser/AArch64TargetParserDef.inc" // Name alias. struct Alias { diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td index f2286ae17dba5..638033a89b9a0 100644 --- a/llvm/lib/Target/AArch64/AArch64Processors.td +++ b/llvm/lib/Target/AArch64/AArch64Processors.td @@ -812,178 +812,271 @@ def ProcessorFeatures { list Generic = [FeatureFPARMv8, FeatureNEON, FeatureETE]; } +class AArch64Processor< + string n, + Architecture64 arch, + SchedMachineModel m, + list f, + list tunef, + list default_extensions +> : ProcessorModel { + // The base architecture for this processor. + Architecture64 Arch = arch; + + // The set of extensions enabled by default for this processor. + list DefaultExts = default_extensions; +} + // FeatureFuseAdrpAdd is enabled under Generic to allow linker merging // optimizations. -def : ProcessorModel<"generic", CortexA510Model, ProcessorFeatures.Generic, +def : AArch64Processor<"generic", HasV9_0aOps, CortexA510Model, ProcessorFeatures.Generic, [FeatureFuseAES, FeatureFuseAdrpAdd, FeaturePostRAScheduler, - FeatureEnableSelectOptimize]>; -def : ProcessorModel<"cortex-a35", CortexA53Model, ProcessorFeatures.A53, - [TuneA35]>; -def : ProcessorModel<"cortex-a34", CortexA53Model, ProcessorFeatures.A53, - [TuneA35]>; -def : ProcessorModel<"cortex-a53", CortexA53Model, ProcessorFeatures.A53, - [TuneA53]>; -def : ProcessorModel<"cortex-a55", CortexA55Model, ProcessorFeatures.A55, - [TuneA55]>; -def : ProcessorModel<"cortex-a510", CortexA510Model, ProcessorFeatures.A510, - [TuneA510]>; -def : ProcessorModel<"cortex-a520", CortexA510Model, ProcessorFeatures.A520, - [TuneA520]>; -def : ProcessorModel<"cortex-a520ae", CortexA510Model, ProcessorFeatures.A520AE, - [TuneA520AE]>; -def : ProcessorModel<"cortex-a57", CortexA57Model, ProcessorFeatures.A53, - [TuneA57]>; -def : ProcessorModel<"cortex-a65", CortexA53Model, ProcessorFeatures.A65, - [TuneA65]>; -def : ProcessorModel<"cortex-a65ae", CortexA53Model, ProcessorFeatures.A65, - [TuneA65]>; -def : ProcessorModel<"cortex-a72", CortexA57Model, ProcessorFeatures.A53, - [TuneA72]>; -def : ProcessorModel<"cortex-a73", CortexA57Model, ProcessorFeatures.A53, - [TuneA73]>; -def : ProcessorModel<"cortex-a75", CortexA57Model, ProcessorFeatures.A55, - [TuneA75]>; -def : ProcessorModel<"cortex-a76", CortexA57Model, ProcessorFeatures.A76, - [TuneA76]>; -def : ProcessorModel<"cortex-a76ae", CortexA57Model, ProcessorFeatures.A76, - [TuneA76]>; -def : ProcessorModel<"cortex-a77", CortexA57Model, ProcessorFeatures.A77, - [TuneA77]>; -def : ProcessorModel<"cortex-a78", CortexA57Model, ProcessorFeatures.A78, - [TuneA78]>; -def : ProcessorModel<"cortex-a78ae", CortexA57Model, ProcessorFeatures.A78AE, - [TuneA78AE]>; -def : ProcessorModel<"cortex-a78c", CortexA57Model, ProcessorFeatures.A78C, - [TuneA78C]>; -def : ProcessorModel<"cortex-a710", NeoverseN2Model, ProcessorFeatures.A710, - [TuneA710]>; -def : ProcessorModel<"cortex-a715", NeoverseN2Model, ProcessorFeatures.A715, - [TuneA715]>; -def : ProcessorModel<"cortex-a720", NeoverseN2Model, ProcessorFeatures.A720, - [TuneA720]>; -def : ProcessorModel<"cortex-a720ae", NeoverseN2Model, ProcessorFeatures.A720AE, - [TuneA720AE]>; -def : ProcessorModel<"cortex-r82", CortexA55Model, ProcessorFeatures.R82, - [TuneR82]>; -def : ProcessorModel<"cortex-r82ae", CortexA55Model, ProcessorFeatures.R82AE, - [TuneR82AE]>; -def : ProcessorModel<"cortex-x1", CortexA57Model, ProcessorFeatures.X1, - [TuneX1]>; -def : ProcessorModel<"cortex-x1c", CortexA57Model, ProcessorFeatures.X1C, - [TuneX1]>; -def : ProcessorModel<"cortex-x2", NeoverseN2Model, ProcessorFeatures.X2, - [TuneX2]>; -def : ProcessorModel<"cortex-x3", NeoverseN2Model, ProcessorFeatures.X3, - [TuneX3]>; -def : ProcessorModel<"cortex-x4", NeoverseN2Model, ProcessorFeatures.X4, - [TuneX4]>; -def : ProcessorModel<"neoverse-e1", CortexA53Model, - ProcessorFeatures.NeoverseE1, [TuneNeoverseE1]>; -def : ProcessorModel<"neoverse-n1", NeoverseN1Model, - ProcessorFeatures.NeoverseN1, [TuneNeoverseN1]>; -def : ProcessorModel<"neoverse-n2", NeoverseN2Model, - ProcessorFeatures.NeoverseN2, [TuneNeoverseN2]>; -def : ProcessorModel<"neoverse-n3", NeoverseN2Model, - ProcessorFeatures.NeoverseN3, [TuneNeoverseN3]>; -def : ProcessorModel<"neoverse-512tvb", NeoverseV1Model, - ProcessorFeatures.Neoverse512TVB, [TuneNeoverse512TVB]>; -def : ProcessorModel<"neoverse-v1", NeoverseV1Model, - ProcessorFeatures.NeoverseV1, [TuneNeoverseV1]>; -def : ProcessorModel<"neoverse-v2", NeoverseV2Model, - ProcessorFeatures.NeoverseV2, [TuneNeoverseV2]>; -def : ProcessorModel<"neoverse-v3", NeoverseV2Model, - ProcessorFeatures.NeoverseV3, [TuneNeoverseV3]>; -def : ProcessorModel<"neoverse-v3ae", NeoverseV2Model, - ProcessorFeatures.NeoverseV3AE, [TuneNeoverseV3AE]>; -def : ProcessorModel<"exynos-m3", ExynosM3Model, ProcessorFeatures.ExynosM3, - [TuneExynosM3]>; -def : ProcessorModel<"exynos-m4", ExynosM4Model, ProcessorFeatures.ExynosM4, - [TuneExynosM4]>; -def : ProcessorModel<"exynos-m5", ExynosM5Model, ProcessorFeatures.ExynosM4, - [TuneExynosM4]>; -def : ProcessorModel<"falkor", FalkorModel, ProcessorFeatures.Falkor, - [TuneFalkor]>; -def : ProcessorModel<"saphira", FalkorModel, ProcessorFeatures.Saphira, - [TuneSaphira]>; -def : ProcessorModel<"kryo", KryoModel, ProcessorFeatures.A53, [TuneKryo]>; + FeatureEnableSelectOptimize], + [/*FIXME what are the default features for generic?*/]>; + +// Alias for the latest Apple processor model supported by LLVM. +def : ProcessorModel<"apple-latest", CycloneModel, ProcessorFeatures.AppleA16, + [TuneAppleA16]>; + +def : AArch64Processor<"cortex-a34", HasV8_0aOps, CortexA53Model, ProcessorFeatures.A53, + [TuneA35], + [FeatureAES, FeatureSHA2, FeatureCRC]>; +def : AArch64Processor<"cortex-a35", HasV8_0aOps, CortexA53Model, ProcessorFeatures.A53, + [TuneA35], + [FeatureAES, FeatureSHA2, FeatureCRC]>; +def : AArch64Processor<"cortex-a53", HasV8_0aOps, CortexA53Model, ProcessorFeatures.A53, + [TuneA53], + [FeatureAES, FeatureSHA2, FeatureCRC]>; +def : AArch64Processor<"cortex-a55", HasV8_2aOps, CortexA55Model, ProcessorFeatures.A55, + [TuneA55], + [FeatureAES, FeatureSHA2, FeatureFullFP16, FeatureDotProd, FeatureRCPC]>; +def : AArch64Processor<"cortex-a510", HasV9_0aOps, CortexA510Model, ProcessorFeatures.A510, + [TuneA510], + [FeatureBF16, FeatureMatMulInt8, FeatureSB, FeaturePAuth, FeatureMTE, FeatureSSBS, FeatureSVE, FeatureSVE2, FeatureSVE2BitPerm, FeatureFP16FML]>; +def : AArch64Processor<"cortex-a520", HasV9_2aOps, CortexA510Model, ProcessorFeatures.A520, + [TuneA520], + [FeatureSB, FeatureSSBS, FeatureMTE, FeatureFP16FML, FeaturePAuth, FeatureSVE2BitPerm, FeatureFlagM, FeaturePerfMon, FeaturePredRes]>; +def : AArch64Processor<"cortex-a520ae", HasV9_2aOps, CortexA510Model, ProcessorFeatures.A520AE, + [TuneA520AE], + [FeatureSB, FeatureSSBS, FeatureMTE, FeatureFP16FML, FeaturePAuth, FeatureSVE2BitPerm, FeatureFlagM, FeaturePerfMon, FeaturePredRes]>; +def : AArch64Processor<"cortex-a57", HasV8_0aOps, CortexA57Model, ProcessorFeatures.A53, + [TuneA57], + [FeatureAES, FeatureSHA2, FeatureCRC]>; +def : AArch64Processor<"cortex-a65", HasV8_2aOps, CortexA53Model, ProcessorFeatures.A65, + [TuneA65], + [FeatureAES, FeatureSHA2, FeatureDotProd, FeatureFullFP16, FeatureRCPC, FeatureSSBS]>; +def : AArch64Processor<"cortex-a65ae", HasV8_2aOps, CortexA53Model, ProcessorFeatures.A65, + [TuneA65], + [FeatureAES, FeatureSHA2, FeatureDotProd, FeatureFullFP16, FeatureRCPC, FeatureSSBS]>; +def : AArch64Processor<"cortex-a72", HasV8_0aOps, CortexA57Model, ProcessorFeatures.A53, + [TuneA72], + [FeatureAES, FeatureSHA2, FeatureCRC]>; +def : AArch64Processor<"cortex-a73", HasV8_0aOps, CortexA57Model, ProcessorFeatures.A53, + [TuneA73], + [FeatureAES, FeatureSHA2, FeatureCRC]>; +def : AArch64Processor<"cortex-a75", HasV8_2aOps, CortexA57Model, ProcessorFeatures.A55, + [TuneA75], + [FeatureAES, FeatureSHA2, FeatureFullFP16, FeatureDotProd, FeatureRCPC]>; +def : AArch64Processor<"cortex-a76", HasV8_2aOps, CortexA57Model, ProcessorFeatures.A76, + [TuneA76], + [FeatureAES, FeatureSHA2, FeatureFullFP16, FeatureDotProd, FeatureRCPC, FeatureSSBS]>; +def : AArch64Processor<"cortex-a76ae", HasV8_2aOps, CortexA57Model, ProcessorFeatures.A76, + [TuneA76], + [FeatureAES, FeatureSHA2, FeatureFullFP16, FeatureDotProd, FeatureRCPC, FeatureSSBS]>; +def : AArch64Processor<"cortex-a77", HasV8_2aOps, CortexA57Model, ProcessorFeatures.A77, + [TuneA77], + [FeatureAES, FeatureSHA2, FeatureFullFP16, FeatureRCPC, FeatureDotProd, FeatureSSBS]>; +def : AArch64Processor<"cortex-a78", HasV8_2aOps, CortexA57Model, ProcessorFeatures.A78, + [TuneA78], + [FeatureAES, FeatureSHA2, FeatureFullFP16, FeatureDotProd, FeatureRCPC, FeatureSSBS, FeatureSPE]>; +def : AArch64Processor<"cortex-a78ae", HasV8_2aOps, CortexA57Model, ProcessorFeatures.A78AE, + [TuneA78AE], + [FeatureAES, FeatureSHA2, FeatureFullFP16, FeatureDotProd, FeatureRCPC, FeatureSSBS, FeatureSPE]>; +def : AArch64Processor<"cortex-a78c", HasV8_2aOps, CortexA57Model, ProcessorFeatures.A78C, + [TuneA78C], + [FeatureAES, FeatureSHA2, FeatureFullFP16, FeatureDotProd, FeatureRCPC, FeatureSSBS, FeatureSPE, FeatureFlagM, FeaturePAuth]>; +def : AArch64Processor<"cortex-a710", HasV9_0aOps, NeoverseN2Model, ProcessorFeatures.A710, + [TuneA710], + [FeatureMTE, FeaturePAuth, FeatureFlagM, FeatureSB, FeatureMatMulInt8, FeatureFP16FML, FeatureSVE, FeatureSVE2, FeatureSVE2BitPerm, FeatureBF16]>; +def : AArch64Processor<"cortex-a715", HasV9_0aOps, NeoverseN2Model, ProcessorFeatures.A715, + [TuneA715], + [FeatureSB, FeatureSSBS, FeatureMTE, FeatureFullFP16, FeatureFP16FML, FeaturePAuth, FeatureMatMulInt8, FeaturePredRes, FeaturePerfMon, FeatureSPE, FeatureSVE, FeatureSVE2BitPerm, FeatureBF16, FeatureFlagM]>; +def : AArch64Processor<"cortex-a720", HasV9_2aOps, NeoverseN2Model, ProcessorFeatures.A720, + [TuneA720], + [FeatureSB, FeatureSSBS, FeatureMTE, FeatureFP16FML, FeaturePAuth, FeatureSVE2BitPerm, FeatureFlagM, FeaturePerfMon, FeaturePredRes, FeatureSPE]>; +def : AArch64Processor<"cortex-a720ae", HasV9_2aOps, NeoverseN2Model, ProcessorFeatures.A720AE, + [TuneA720AE], + [FeatureSB, FeatureSSBS, FeatureMTE, FeatureFP16FML, FeaturePAuth, FeatureSVE2BitPerm, FeatureFlagM, FeaturePerfMon, FeaturePredRes, FeatureSPE]>; +def : AArch64Processor<"cortex-r82", HasV8_0rOps, CortexA55Model, ProcessorFeatures.R82, + [TuneR82], + [FeatureLSE, FeatureFlagM, FeaturePerfMon, FeaturePredRes]>; +def : AArch64Processor<"cortex-r82ae", HasV8_0rOps, CortexA55Model, ProcessorFeatures.R82AE, + [TuneR82AE], + [FeatureLSE, FeatureFlagM, FeaturePerfMon, FeaturePredRes]>; +def : AArch64Processor<"cortex-x1", HasV8_2aOps, CortexA57Model, ProcessorFeatures.X1, + [TuneX1], + [FeatureAES, FeatureSHA2, FeatureFullFP16, FeatureDotProd, FeatureRCPC, FeatureSSBS, FeatureSPE]>; +def : AArch64Processor<"cortex-x1c", HasV8_2aOps, CortexA57Model, ProcessorFeatures.X1C, + [TuneX1], + [FeatureAES, FeatureSHA2, FeatureFullFP16, FeatureDotProd, FeatureRCPC, FeatureSSBS, FeaturePAuth, FeatureSPE, FeatureFlagM]>; +def : AArch64Processor<"cortex-x2", HasV9_0aOps, NeoverseN2Model, ProcessorFeatures.X2, + [TuneX2], + [FeatureMTE, FeatureBF16, FeatureMatMulInt8, FeaturePAuth, FeatureSSBS, FeatureSB, FeatureSVE, FeatureSVE2, FeatureSVE2BitPerm, FeatureFP16FML, FeatureFlagM]>; +def : AArch64Processor<"cortex-x3", HasV9_0aOps, NeoverseN2Model, ProcessorFeatures.X3, + [TuneX3], + [FeatureSVE, FeaturePerfMon, FeatureSPE, FeatureBF16, FeatureMatMulInt8, FeatureMTE, FeatureSVE2BitPerm, FeatureSB, FeaturePAuth, FeatureFullFP16, FeatureFP16FML, FeaturePredRes, FeatureFlagM, FeatureSSBS]>; +def : AArch64Processor<"cortex-x4", HasV9_2aOps, NeoverseN2Model, ProcessorFeatures.X4, + [TuneX4], + [FeatureSB, FeatureSSBS, FeatureMTE, FeatureFP16FML, FeaturePAuth, FeatureSVE2BitPerm, FeatureFlagM, FeaturePerfMon, FeaturePredRes, FeatureSPE]>; +def : AArch64Processor<"neoverse-e1", HasV8_2aOps, CortexA53Model, ProcessorFeatures.NeoverseE1, + [TuneNeoverseE1], + [FeatureAES, FeatureSHA2, FeatureDotProd, FeatureFullFP16, FeatureRCPC, FeatureSSBS]>; +def : AArch64Processor<"neoverse-n1", HasV8_2aOps, NeoverseN1Model, ProcessorFeatures.NeoverseN1, + [TuneNeoverseN1], + [FeatureAES, FeatureSHA2, FeatureDotProd, FeatureFullFP16, FeatureSPE, FeatureRCPC, FeatureSSBS]>; +def : AArch64Processor<"neoverse-n2", HasV9_0aOps, NeoverseN2Model, ProcessorFeatures.NeoverseN2, + [TuneNeoverseN2], + [FeatureBF16, FeatureDotProd, FeatureFullFP16, FeatureFP16FML, FeatureMatMulInt8, FeatureMTE, FeatureSB, FeatureSSBS, FeatureSVE, FeatureSVE2, FeatureSVE2BitPerm]>; +def : AArch64Processor<"neoverse-n3", HasV9_2aOps, NeoverseN2Model, ProcessorFeatures.NeoverseN3, + [TuneNeoverseN3], + [FeatureMTE, FeatureSSBS, FeatureSB, FeaturePredRes, FeatureFP16FML, FeaturePAuth, FeatureFlagM, FeaturePerfMon, FeatureRandGen, FeatureSVE2BitPerm, FeatureSPE, FeaturePerfMon]>; +def : AArch64Processor<"neoverse-512tvb", HasV8_4aOps, NeoverseV1Model, ProcessorFeatures.Neoverse512TVB, + [TuneNeoverse512TVB], + [FeatureAES, FeatureSHA2, FeatureSHA3, FeatureSM4, FeatureSVE, FeatureSSBS, FeatureFullFP16, FeatureBF16, FeatureDotProd, FeatureSPE, FeatureRandGen, FeatureFP16FML, FeatureMatMulInt8]>; +def : AArch64Processor<"neoverse-v1", HasV8_4aOps, NeoverseV1Model, ProcessorFeatures.NeoverseV1, + [TuneNeoverseV1], + [FeatureAES, FeatureSHA2, FeatureSHA3, FeatureSM4, FeatureSVE, FeatureSSBS, FeatureFullFP16, FeatureBF16, FeatureDotProd, FeatureSPE, FeatureRandGen, FeatureFP16FML, FeatureMatMulInt8]>; +def : AArch64Processor<"neoverse-v2", HasV9_0aOps, NeoverseV2Model, ProcessorFeatures.NeoverseV2, + [TuneNeoverseV2], + [FeatureSVE, FeatureSVE2, FeatureSSBS, FeatureFullFP16, FeatureBF16, FeatureRandGen, FeatureDotProd, FeatureSPE, FeatureSVE2BitPerm, FeatureFP16FML, FeatureMatMulInt8, FeatureMTE]>; +def : AArch64Processor<"neoverse-v3", HasV9_2aOps, NeoverseV2Model, ProcessorFeatures.NeoverseV3, + [TuneNeoverseV3], + [FeatureSPE, FeatureMTE, FeatureSSBS, FeatureSB, FeaturePredRes, FeatureLS64, FeatureBRBE, FeaturePAuth, FeatureFlagM, FeaturePerfMon, FeatureRandGen, FeatureSVE2BitPerm, FeatureFP16FML]>; +def : AArch64Processor<"neoverse-v3ae", HasV9_2aOps, NeoverseV2Model, ProcessorFeatures.NeoverseV3AE, + [TuneNeoverseV3AE], + [FeatureSPE, FeatureMTE, FeatureSSBS, FeatureSB, FeaturePredRes, FeatureLS64, FeatureBRBE, FeaturePAuth, FeatureFlagM, FeaturePerfMon, FeatureRandGen, FeatureSVE2BitPerm, FeatureFP16FML]>; +def : AArch64Processor<"exynos-m3", HasV8_0aOps, ExynosM3Model, ProcessorFeatures.ExynosM3, + [TuneExynosM3], + [FeatureAES, FeatureSHA2, FeatureCRC]>; +def : AArch64Processor<"exynos-m4", HasV8_2aOps, ExynosM4Model, ProcessorFeatures.ExynosM4, + [TuneExynosM4], + [FeatureAES, FeatureSHA2, FeatureDotProd, FeatureFullFP16]>; +def : AArch64Processor<"exynos-m5", HasV8_2aOps, ExynosM5Model, ProcessorFeatures.ExynosM4, + [TuneExynosM4], + [FeatureAES, FeatureSHA2, FeatureDotProd, FeatureFullFP16]>; +def : AArch64Processor<"falkor", HasV8_0aOps, FalkorModel, ProcessorFeatures.Falkor, + [TuneFalkor], + [FeatureAES, FeatureSHA2, FeatureCRC, FeatureRDM]>; +def : AArch64Processor<"saphira", HasV8_3aOps, FalkorModel, ProcessorFeatures.Saphira, + [TuneSaphira], + [FeatureAES, FeatureSHA2, FeatureSPE]>; +def : AArch64Processor<"kryo", HasV8_0aOps, KryoModel, ProcessorFeatures.A53, + [TuneKryo], + [FeatureAES, FeatureSHA2, FeatureCRC]>; // Cavium ThunderX/ThunderX T8X Processors -def : ProcessorModel<"thunderx", ThunderXT8XModel, ProcessorFeatures.ThunderX, - [TuneThunderX]>; -def : ProcessorModel<"thunderxt88", ThunderXT8XModel, - ProcessorFeatures.ThunderX, [TuneThunderXT88]>; -def : ProcessorModel<"thunderxt81", ThunderXT8XModel, - ProcessorFeatures.ThunderX, [TuneThunderXT81]>; -def : ProcessorModel<"thunderxt83", ThunderXT8XModel, - ProcessorFeatures.ThunderX, [TuneThunderXT83]>; +def : AArch64Processor<"thunderx", HasV8_0aOps, ThunderXT8XModel, ProcessorFeatures.ThunderX, + [TuneThunderX], + [FeatureAES, FeatureSHA2, FeatureCRC]>; +def : AArch64Processor<"thunderxt88", HasV8_0aOps, ThunderXT8XModel, ProcessorFeatures.ThunderX, + [TuneThunderXT88], + [FeatureAES, FeatureSHA2, FeatureCRC]>; +def : AArch64Processor<"thunderxt81", HasV8_0aOps, ThunderXT8XModel, ProcessorFeatures.ThunderX, + [TuneThunderXT81], + [FeatureAES, FeatureSHA2, FeatureCRC]>; +def : AArch64Processor<"thunderxt83", HasV8_0aOps, ThunderXT8XModel, ProcessorFeatures.ThunderX, + [TuneThunderXT83], + [FeatureAES, FeatureSHA2, FeatureCRC]>; // Cavium ThunderX2T9X Processors. Formerly Broadcom Vulcan. -def : ProcessorModel<"thunderx2t99", ThunderX2T99Model, - ProcessorFeatures.ThunderX2T99, [TuneThunderX2T99]>; +def : AArch64Processor<"thunderx2t99", HasV8_1aOps, ThunderX2T99Model, ProcessorFeatures.ThunderX2T99, + [TuneThunderX2T99], + [FeatureAES, FeatureSHA2]>; // Marvell ThunderX3T110 Processors. -def : ProcessorModel<"thunderx3t110", ThunderX3T110Model, - ProcessorFeatures.ThunderX3T110, [TuneThunderX3T110]>; -def : ProcessorModel<"tsv110", TSV110Model, ProcessorFeatures.TSV110, - [TuneTSV110]>; +def : AArch64Processor<"thunderx3t110", HasV8_3aOps, ThunderX3T110Model, ProcessorFeatures.ThunderX3T110, + [TuneThunderX3T110], + [FeatureAES, FeatureSHA2]>; +def : AArch64Processor<"tsv110", HasV8_2aOps, TSV110Model, ProcessorFeatures.TSV110, + [TuneTSV110], + [FeatureAES, FeatureSHA2, FeatureDotProd, FeatureFullFP16, FeatureFP16FML, FeatureSPE, FeatureJS, FeatureComplxNum]>; // Support cyclone as an alias for apple-a7 so we can still LTO old bitcode. -def : ProcessorModel<"cyclone", CycloneModel, ProcessorFeatures.AppleA7, - [TuneAppleA7]>; +def : AArch64Processor<"cyclone", HasV8_0aOps, CycloneModel, ProcessorFeatures.AppleA7, + [TuneAppleA7], + [FeatureAES, FeatureSHA2]>; // iPhone and iPad CPUs -def : ProcessorModel<"apple-a7", CycloneModel, ProcessorFeatures.AppleA7, - [TuneAppleA7]>; -def : ProcessorModel<"apple-a8", CycloneModel, ProcessorFeatures.AppleA7, - [TuneAppleA7]>; -def : ProcessorModel<"apple-a9", CycloneModel, ProcessorFeatures.AppleA7, - [TuneAppleA7]>; -def : ProcessorModel<"apple-a10", CycloneModel, ProcessorFeatures.AppleA10, - [TuneAppleA10]>; -def : ProcessorModel<"apple-a11", CycloneModel, ProcessorFeatures.AppleA11, - [TuneAppleA11]>; -def : ProcessorModel<"apple-a12", CycloneModel, ProcessorFeatures.AppleA12, - [TuneAppleA12]>; -def : ProcessorModel<"apple-a13", CycloneModel, ProcessorFeatures.AppleA13, - [TuneAppleA13]>; -def : ProcessorModel<"apple-a14", CycloneModel, ProcessorFeatures.AppleA14, - [TuneAppleA14]>; -def : ProcessorModel<"apple-a15", CycloneModel, ProcessorFeatures.AppleA15, - [TuneAppleA15]>; -def : ProcessorModel<"apple-a16", CycloneModel, ProcessorFeatures.AppleA16, - [TuneAppleA16]>; -def : ProcessorModel<"apple-a17", CycloneModel, ProcessorFeatures.AppleA17, - [TuneAppleA17]>; +def : AArch64Processor<"apple-a7", HasV8_0aOps, CycloneModel, ProcessorFeatures.AppleA7, + [TuneAppleA7], + [FeatureAES, FeatureSHA2]>; +def : AArch64Processor<"apple-a8", HasV8_0aOps, CycloneModel, ProcessorFeatures.AppleA7, + [TuneAppleA7], + [FeatureAES, FeatureSHA2]>; +def : AArch64Processor<"apple-a9", HasV8_0aOps, CycloneModel, ProcessorFeatures.AppleA7, + [TuneAppleA7], + [FeatureAES, FeatureSHA2]>; +def : AArch64Processor<"apple-a10", HasV8_0aOps, CycloneModel, ProcessorFeatures.AppleA10, + [TuneAppleA10], + [FeatureAES, FeatureSHA2, FeatureCRC, FeatureRDM]>; +def : AArch64Processor<"apple-a11", HasV8_2aOps, CycloneModel, ProcessorFeatures.AppleA11, + [TuneAppleA11], + [FeatureAES, FeatureSHA2, FeatureFullFP16]>; +def : AArch64Processor<"apple-a12", HasV8_3aOps, CycloneModel, ProcessorFeatures.AppleA12, + [TuneAppleA12], + [FeatureAES, FeatureSHA2, FeatureFullFP16]>; +def : AArch64Processor<"apple-a13", HasV8_4aOps, CycloneModel, ProcessorFeatures.AppleA13, + [TuneAppleA13], + [FeatureAES, FeatureSHA2, FeatureSHA3, FeatureFullFP16, FeatureFP16FML]>; +def : AArch64Processor<"apple-a14", HasV8_5aOps, CycloneModel, ProcessorFeatures.AppleA14, + [TuneAppleA14], + [FeatureAES, FeatureSHA2, FeatureSHA3, FeatureFullFP16, FeatureFP16FML]>; +def : AArch64Processor<"apple-a15", HasV8_6aOps, CycloneModel, ProcessorFeatures.AppleA15, + [TuneAppleA15], + [FeatureAES, FeatureSHA2, FeatureSHA3, FeatureFullFP16, FeatureFP16FML]>; +// Alias for the latest Apple processor model supported by LLVM. +def : AArch64Processor<"apple-a16", HasV8_6aOps, CycloneModel, ProcessorFeatures.AppleA16, + [TuneAppleA16], + [FeatureAES, FeatureSHA2, FeatureSHA3, FeatureFullFP16, FeatureFP16FML]>; +def : AArch64Processor<"apple-a17", HasV8_6aOps, CycloneModel, ProcessorFeatures.AppleA17, + [TuneAppleA17], + [FeatureAES, FeatureSHA2, FeatureSHA3, FeatureFullFP16, FeatureFP16FML]>; // Mac CPUs -def : ProcessorModel<"apple-m1", CycloneModel, ProcessorFeatures.AppleA14, - [TuneAppleA14]>; -def : ProcessorModel<"apple-m2", CycloneModel, ProcessorFeatures.AppleA15, - [TuneAppleA15]>; -def : ProcessorModel<"apple-m3", CycloneModel, ProcessorFeatures.AppleA16, - [TuneAppleA16]>; +def : AArch64Processor<"apple-m1", HasV8_5aOps, CycloneModel, ProcessorFeatures.AppleA14, + [TuneAppleA14], + [FeatureAES, FeatureSHA2, FeatureSHA3, FeatureFullFP16, FeatureFP16FML]>; +def : AArch64Processor<"apple-m2", HasV8_6aOps, CycloneModel, ProcessorFeatures.AppleA15, + [TuneAppleA15], + [FeatureAES, FeatureSHA2, FeatureSHA3, FeatureFullFP16, FeatureFP16FML]>; +def : AArch64Processor<"apple-m3", HasV8_6aOps, CycloneModel, ProcessorFeatures.AppleA16, + [TuneAppleA16], + [FeatureAES, FeatureSHA2, FeatureSHA3, FeatureFullFP16, FeatureFP16FML]>; // watch CPUs. -def : ProcessorModel<"apple-s4", CycloneModel, ProcessorFeatures.AppleA12, - [TuneAppleA12]>; -def : ProcessorModel<"apple-s5", CycloneModel, ProcessorFeatures.AppleA12, - [TuneAppleA12]>; - -// Alias for the latest Apple processor model supported by LLVM. -def : ProcessorModel<"apple-latest", CycloneModel, ProcessorFeatures.AppleA16, - [TuneAppleA16]>; +def : AArch64Processor<"apple-s4", HasV8_3aOps, CycloneModel, ProcessorFeatures.AppleA12, + [TuneAppleA12], + [FeatureAES, FeatureSHA2, FeatureFullFP16]>; +def : AArch64Processor<"apple-s5", HasV8_3aOps, CycloneModel, ProcessorFeatures.AppleA12, + [TuneAppleA12], + [FeatureAES, FeatureSHA2, FeatureFullFP16]>; // Fujitsu A64FX -def : ProcessorModel<"a64fx", A64FXModel, ProcessorFeatures.A64FX, - [TuneA64FX]>; +def : AArch64Processor<"a64fx", HasV8_2aOps, A64FXModel, ProcessorFeatures.A64FX, + [TuneA64FX], + [FeatureAES, FeatureSHA2, FeatureFullFP16, FeatureSVE]>; // Nvidia Carmel -def : ProcessorModel<"carmel", NoSchedModel, ProcessorFeatures.Carmel, - [TuneCarmel]>; +def : AArch64Processor<"carmel", HasV8_2aOps, NoSchedModel, ProcessorFeatures.Carmel, + [TuneCarmel], + [FeatureAES, FeatureSHA2, FeatureFullFP16]>; // Ampere Computing -def : ProcessorModel<"ampere1", Ampere1Model, ProcessorFeatures.Ampere1, - [TuneAmpere1]>; +def : AArch64Processor<"ampere1", HasV8_6aOps, Ampere1Model, ProcessorFeatures.Ampere1, + [TuneAmpere1], + [FeatureAES, FeatureSHA2, FeatureSHA3, FeatureFullFP16, FeatureSB, FeatureSSBS, FeatureRandGen]>; -def : ProcessorModel<"ampere1a", Ampere1Model, ProcessorFeatures.Ampere1A, - [TuneAmpere1A]>; +def : AArch64Processor<"ampere1a", HasV8_6aOps, Ampere1Model, ProcessorFeatures.Ampere1A, + [TuneAmpere1A], + [FeatureFullFP16, FeatureRandGen, FeatureSM4, FeatureSHA3, FeatureSHA2, FeatureAES, FeatureMTE, FeatureSB, FeatureSSBS]>; -def : ProcessorModel<"ampere1b", Ampere1BModel, ProcessorFeatures.Ampere1B, - [TuneAmpere1B]>; +def : AArch64Processor<"ampere1b", HasV8_7aOps, Ampere1BModel, ProcessorFeatures.Ampere1B, + [TuneAmpere1B], + [FeatureFullFP16, FeatureRandGen, FeatureSM4, FeatureSHA3, FeatureSHA2, FeatureAES, FeatureMTE, FeatureSB, FeatureSSBS, FeatureCSSC]>; diff --git a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp index 70050020865e0..c2d9d92570888 100644 --- a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp +++ b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp @@ -115,6 +115,13 @@ static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream &OS) { // Emit architecture information OS << "#ifdef EMIT_ARCHITECTURES\n"; + // Return the C++ name of the of an ArchInfo object + auto ArchInfoName = [](int Major, int Minor, StringRef Profile) { + return Minor == 0 ? "ARMV" + std::to_string(Major) + Profile.upper() + : "ARMV" + std::to_string(Major) + "_" + + std::to_string(Minor) + Profile.upper(); + }; + auto Architectures = RK.getAllDerivedDefinitionsIfDefined("Architecture64"); std::vector CppSpellings; for (const Record *Rec : Architectures) { @@ -129,10 +136,7 @@ static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream &OS) { ProfileLower + "'"); // Name of the object in C++ - const std::string CppSpelling = - Minor == 0 ? "ARMV" + std::to_string(Major) + ProfileUpper.c_str() - : "ARMV" + std::to_string(Major) + "_" + - std::to_string(Minor) + ProfileUpper.c_str(); + const std::string CppSpelling = ArchInfoName(Major, Minor, ProfileUpper); OS << "inline constexpr ArchInfo " << CppSpelling << " = {\n"; CppSpellings.push_back(CppSpelling); @@ -173,6 +177,35 @@ static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream &OS) { OS << "#undef EMIT_ARCHITECTURES\n" << "#endif // EMIT_ARCHITECTURES\n" << "\n"; + + // Emit CPU information + OS << "#ifdef EMIT_CPU_INFO\n" + << "inline constexpr CpuInfo CpuInfos[] = {\n"; + + for (const Record *Rec : + RK.getAllDerivedDefinitionsIfDefined("AArch64Processor")) { + auto Name = Rec->getValueAsString("Name"); + auto Arch = Rec->getValueAsDef("Arch"); + auto Major = Arch->getValueAsInt("Major"); + auto Minor = Arch->getValueAsInt("Minor"); + auto Profile = Arch->getValueAsString("Profile"); + auto ArchInfo = ArchInfoName(Major, Minor, Profile); + + OS << " {\n" + << " \"" << Name << "\",\n" + << " " << ArchInfo << ",\n" + << " AArch64::ExtensionBitset({\n"; + for (auto E : Rec->getValueAsListOfDefs("DefaultExts")) + OS << " AArch64::" + << E->getValueAsString("ArchExtKindSpelling").upper() << ",\n"; + OS << " })\n" + << " },\n"; + } + OS << "};\n"; + + OS << "#undef EMIT_CPU_INFO\n" + << "#endif // EMIT_CPU_INFO\n" + << "\n"; } static TableGen::Emitter::Opt From d461a6d789b4c5866cf34c9d8a5108c9cbfdbda5 Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Wed, 15 May 2024 11:48:41 +0100 Subject: [PATCH 03/19] Remove "generic" from CPUInfo by making it a ProcessorModel Making generic a AArch64Processor caused two test failures: - aarch64-targetattr.c (minor fix) - aarch64-fmv-dependencies.c (all dependencies completely wrong) --- llvm/lib/Target/AArch64/AArch64Processors.td | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td index 638033a89b9a0..428754cfafdfd 100644 --- a/llvm/lib/Target/AArch64/AArch64Processors.td +++ b/llvm/lib/Target/AArch64/AArch64Processors.td @@ -829,10 +829,9 @@ class AArch64Processor< // FeatureFuseAdrpAdd is enabled under Generic to allow linker merging // optimizations. -def : AArch64Processor<"generic", HasV9_0aOps, CortexA510Model, ProcessorFeatures.Generic, +def : ProcessorModel<"generic", CortexA510Model, ProcessorFeatures.Generic, [FeatureFuseAES, FeatureFuseAdrpAdd, FeaturePostRAScheduler, - FeatureEnableSelectOptimize], - [/*FIXME what are the default features for generic?*/]>; + FeatureEnableSelectOptimize]>; // Alias for the latest Apple processor model supported by LLVM. def : ProcessorModel<"apple-latest", CycloneModel, ProcessorFeatures.AppleA16, From b991f5a67290b4e45e47219bda7dfd4f078de86c Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Wed, 15 May 2024 14:36:36 +0100 Subject: [PATCH 04/19] fix tests The order of CPUs has changed --- clang/test/Misc/target-invalid-cpu-note.c | 4 ++-- .../TargetParser/TargetParserTest.cpp | 20 ++++++++----------- 2 files changed, 10 insertions(+), 14 deletions(-) diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c index 768b243b04e3a..9e5c2c2585e68 100644 --- a/clang/test/Misc/target-invalid-cpu-note.c +++ b/clang/test/Misc/target-invalid-cpu-note.c @@ -5,11 +5,11 @@ // RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix AARCH64 // AARCH64: error: unknown target CPU 'not-a-cpu' -// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-r82ae, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, neoverse-v3, neoverse-v3ae, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, ampere1b, cobalt-100, grace{{$}} +// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-r82ae, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, neoverse-v3, neoverse-v3ae, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx, thunderxt88, thunderxt81, thunderxt83, thunderx2t99, thunderx3t110, tsv110, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, a64fx, carmel, ampere1, ampere1a, ampere1b, cobalt-100, grace{{$}} // RUN: not %clang_cc1 -triple arm64--- -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE_AARCH64 // TUNE_AARCH64: error: unknown target CPU 'not-a-cpu' -// TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-r82ae, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, neoverse-v3, neoverse-v3ae, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, ampere1b, cobalt-100, grace{{$}} +// TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-r82ae, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, neoverse-v3, neoverse-v3ae, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx, thunderxt88, thunderxt81, thunderxt83, thunderx2t99, thunderx3t110, tsv110, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, a64fx, carmel, ampere1, ampere1a, ampere1b, cobalt-100, grace{{$}} // RUN: not %clang_cc1 -triple i386--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix X86 // X86: error: unknown target CPU 'not-a-cpu' diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp index 0455e061f0bf7..eecc21f35d8da 100644 --- a/llvm/unittests/TargetParser/TargetParserTest.cpp +++ b/llvm/unittests/TargetParser/TargetParserTest.cpp @@ -1474,27 +1474,23 @@ INSTANTIATE_TEST_SUITE_P( "9.2-A"), ARMCPUTestParams( "cyclone", "armv8-a", "crypto-neon-fp-armv8", - AArch64::ExtensionBitset({AArch64::AEK_NONE, AArch64::AEK_AES, - AArch64::AEK_SHA2, AArch64::AEK_FP, - AArch64::AEK_SIMD}), + AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2, + AArch64::AEK_FP, AArch64::AEK_SIMD}), "8-A"), ARMCPUTestParams( "apple-a7", "armv8-a", "crypto-neon-fp-armv8", - AArch64::ExtensionBitset({AArch64::AEK_NONE, AArch64::AEK_AES, - AArch64::AEK_SHA2, AArch64::AEK_FP, - AArch64::AEK_SIMD}), + AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2, + AArch64::AEK_FP, AArch64::AEK_SIMD}), "8-A"), ARMCPUTestParams( "apple-a8", "armv8-a", "crypto-neon-fp-armv8", - AArch64::ExtensionBitset({AArch64::AEK_NONE, AArch64::AEK_AES, - AArch64::AEK_SHA2, AArch64::AEK_FP, - AArch64::AEK_SIMD}), + AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2, + AArch64::AEK_FP, AArch64::AEK_SIMD}), "8-A"), ARMCPUTestParams( "apple-a9", "armv8-a", "crypto-neon-fp-armv8", - AArch64::ExtensionBitset({AArch64::AEK_NONE, AArch64::AEK_AES, - AArch64::AEK_SHA2, AArch64::AEK_FP, - AArch64::AEK_SIMD}), + AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2, + AArch64::AEK_FP, AArch64::AEK_SIMD}), "8-A"), ARMCPUTestParams( "apple-a10", "armv8-a", "crypto-neon-fp-armv8", From 429a45517617ee88df920315889c1aecf02ec593 Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Wed, 15 May 2024 13:13:36 +0100 Subject: [PATCH 05/19] Handle "generic" like any other CPU --- clang/lib/Basic/Targets/AArch64.cpp | 2 +- clang/lib/Driver/ToolChains/Arch/AArch64.cpp | 14 +++++--------- clang/test/CodeGen/aarch64-targetattr.c | 2 +- llvm/lib/Target/AArch64/AArch64Processors.td | 5 +++-- llvm/lib/TargetParser/AArch64TargetParser.cpp | 3 --- 5 files changed, 10 insertions(+), 16 deletions(-) diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp index 5db1ce78c657f..6f2a6964d34fa 100644 --- a/clang/lib/Basic/Targets/AArch64.cpp +++ b/clang/lib/Basic/Targets/AArch64.cpp @@ -246,7 +246,7 @@ bool AArch64TargetInfo::validateBranchProtection(StringRef Spec, StringRef, } bool AArch64TargetInfo::isValidCPUName(StringRef Name) const { - return Name == "generic" || llvm::AArch64::parseCpu(Name); + return llvm::AArch64::parseCpu(Name).has_value(); } bool AArch64TargetInfo::setCPU(const std::string &Name) { diff --git a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp index 2cd2b35ee51bc..ec248b80251ea 100644 --- a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp +++ b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp @@ -98,16 +98,12 @@ static bool DecodeAArch64Mcpu(const Driver &D, StringRef Mcpu, StringRef &CPU, if (CPU == "native") CPU = llvm::sys::getHostCPUName(); - if (CPU == "generic") { - Extensions.enable(llvm::AArch64::AEK_SIMD); - } else { - const std::optional CpuInfo = - llvm::AArch64::parseCpu(CPU); - if (!CpuInfo) - return false; + const std::optional CpuInfo = + llvm::AArch64::parseCpu(CPU); + if (!CpuInfo) + return false; - Extensions.addCPUDefaults(*CpuInfo); - } + Extensions.addCPUDefaults(*CpuInfo); if (Split.second.size() && !DecodeAArch64Features(D, Split.second, Extensions)) diff --git a/clang/test/CodeGen/aarch64-targetattr.c b/clang/test/CodeGen/aarch64-targetattr.c index 3e7a209245607..966f8b4bc7482 100644 --- a/clang/test/CodeGen/aarch64-targetattr.c +++ b/clang/test/CodeGen/aarch64-targetattr.c @@ -100,7 +100,7 @@ void minusarch() {} // CHECK: attributes #3 = { {{.*}} "target-features"="+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+ras,+rcpc,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" } // CHECK: attributes #4 = { {{.*}} "target-cpu"="cortex-a710" "target-features"="+bf16,+complxnum,+crc,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+mte,+neon,+pauth,+ras,+rcpc,+rdm,+sb,+sve,+sve2,+sve2-bitperm" } // CHECK: attributes #5 = { {{.*}} "tune-cpu"="cortex-a710" } -// CHECK: attributes #6 = { {{.*}} "target-cpu"="generic" } +// CHECK: attributes #6 = { {{.*}} "target-cpu"="generic" "target-features"="+fp-armv8,+neon" } // CHECK: attributes #7 = { {{.*}} "tune-cpu"="generic" } // CHECK: attributes #8 = { {{.*}} "target-cpu"="neoverse-n1" "target-features"="+aes,+crc,+dotprod,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs" "tune-cpu"="cortex-a710" } // CHECK: attributes #9 = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+sve" "tune-cpu"="cortex-a710" } diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td index 428754cfafdfd..b499d81ae1b1b 100644 --- a/llvm/lib/Target/AArch64/AArch64Processors.td +++ b/llvm/lib/Target/AArch64/AArch64Processors.td @@ -829,9 +829,10 @@ class AArch64Processor< // FeatureFuseAdrpAdd is enabled under Generic to allow linker merging // optimizations. -def : ProcessorModel<"generic", CortexA510Model, ProcessorFeatures.Generic, +def : AArch64Processor<"generic", HasV8_0aOps, CortexA510Model, ProcessorFeatures.Generic, [FeatureFuseAES, FeatureFuseAdrpAdd, FeaturePostRAScheduler, - FeatureEnableSelectOptimize]>; + FeatureEnableSelectOptimize], + [FeatureNEON]>; // Alias for the latest Apple processor model supported by LLVM. def : ProcessorModel<"apple-latest", CycloneModel, ProcessorFeatures.AppleA16, diff --git a/llvm/lib/TargetParser/AArch64TargetParser.cpp b/llvm/lib/TargetParser/AArch64TargetParser.cpp index 026214e7e2eac..bffa84e6687aa 100644 --- a/llvm/lib/TargetParser/AArch64TargetParser.cpp +++ b/llvm/lib/TargetParser/AArch64TargetParser.cpp @@ -30,9 +30,6 @@ static unsigned checkArchVersion(llvm::StringRef Arch) { } const AArch64::ArchInfo *AArch64::getArchForCpu(StringRef CPU) { - if (CPU == "generic") - return &ARMV8A; - // Note: this now takes cpu aliases into account std::optional Cpu = parseCpu(CPU); if (!Cpu) From 3848baae5770454a8ab8b5730b4c46da6edb7287 Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Wed, 15 May 2024 13:44:05 +0100 Subject: [PATCH 06/19] Fix AppleA14 and Saphira architecture definitions --- llvm/lib/Target/AArch64/AArch64Processors.td | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td index b499d81ae1b1b..5537684b75238 100644 --- a/llvm/lib/Target/AArch64/AArch64Processors.td +++ b/llvm/lib/Target/AArch64/AArch64Processors.td @@ -718,7 +718,7 @@ def ProcessorFeatures { list AppleA13 = [HasV8_4aOps, FeatureCrypto, FeatureFPARMv8, FeatureNEON, FeaturePerfMon, FeatureFullFP16, FeatureFP16FML, FeatureSHA3]; - list AppleA14 = [HasV8_4aOps, FeatureCrypto, FeatureFPARMv8, + list AppleA14 = [HasV8_5aOps, FeatureCrypto, FeatureFPARMv8, FeatureNEON, FeaturePerfMon, FeatureFRInt3264, FeatureSpecRestrict, FeatureSSBS, FeatureSB, FeaturePredRes, FeatureCacheDeepPersist, @@ -967,7 +967,7 @@ def : AArch64Processor<"exynos-m5", HasV8_2aOps, ExynosM5Model, ProcessorFeature def : AArch64Processor<"falkor", HasV8_0aOps, FalkorModel, ProcessorFeatures.Falkor, [TuneFalkor], [FeatureAES, FeatureSHA2, FeatureCRC, FeatureRDM]>; -def : AArch64Processor<"saphira", HasV8_3aOps, FalkorModel, ProcessorFeatures.Saphira, +def : AArch64Processor<"saphira", HasV8_4aOps, FalkorModel, ProcessorFeatures.Saphira, [TuneSaphira], [FeatureAES, FeatureSHA2, FeatureSPE]>; def : AArch64Processor<"kryo", HasV8_0aOps, KryoModel, ProcessorFeatures.A53, From 45aa541fb45d166056d4f1b07363691047ce3a58 Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Thu, 16 May 2024 15:59:36 +0100 Subject: [PATCH 07/19] make lambda return type explicit --- llvm/utils/TableGen/ARMTargetDefEmitter.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp index c2d9d92570888..8bf4e7ee0978f 100644 --- a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp +++ b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp @@ -116,7 +116,8 @@ static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream &OS) { OS << "#ifdef EMIT_ARCHITECTURES\n"; // Return the C++ name of the of an ArchInfo object - auto ArchInfoName = [](int Major, int Minor, StringRef Profile) { + auto ArchInfoName = [](int Major, int Minor, + StringRef Profile) -> std::string { return Minor == 0 ? "ARMV" + std::to_string(Major) + Profile.upper() : "ARMV" + std::to_string(Major) + "_" + std::to_string(Minor) + Profile.upper(); From 030107160a7b47b770909a5677aeee024cc71bd5 Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Thu, 16 May 2024 18:41:29 +0100 Subject: [PATCH 08/19] fix tests to account for new "generic" cpu, bump number of CPUs --- clang/test/Misc/target-invalid-cpu-note.c | 4 ++-- llvm/unittests/TargetParser/TargetParserTest.cpp | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c index 9e5c2c2585e68..cea3bc7bbfb53 100644 --- a/clang/test/Misc/target-invalid-cpu-note.c +++ b/clang/test/Misc/target-invalid-cpu-note.c @@ -5,11 +5,11 @@ // RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix AARCH64 // AARCH64: error: unknown target CPU 'not-a-cpu' -// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-r82ae, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, neoverse-v3, neoverse-v3ae, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx, thunderxt88, thunderxt81, thunderxt83, thunderx2t99, thunderx3t110, tsv110, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, a64fx, carmel, ampere1, ampere1a, ampere1b, cobalt-100, grace{{$}} +// AARCH64-NEXT: note: valid target CPU values are: generic, cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-r82ae, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, neoverse-v3, neoverse-v3ae, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx, thunderxt88, thunderxt81, thunderxt83, thunderx2t99, thunderx3t110, tsv110, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, a64fx, carmel, ampere1, ampere1a, ampere1b, cobalt-100, grace{{$}} // RUN: not %clang_cc1 -triple arm64--- -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE_AARCH64 // TUNE_AARCH64: error: unknown target CPU 'not-a-cpu' -// TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-r82ae, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, neoverse-v3, neoverse-v3ae, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx, thunderxt88, thunderxt81, thunderxt83, thunderx2t99, thunderx3t110, tsv110, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, a64fx, carmel, ampere1, ampere1a, ampere1b, cobalt-100, grace{{$}} +// TUNE_AARCH64-NEXT: note: valid target CPU values are: generic, cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-r82ae, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, neoverse-v3, neoverse-v3ae, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx, thunderxt88, thunderxt81, thunderxt83, thunderx2t99, thunderx3t110, tsv110, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, a64fx, carmel, ampere1, ampere1a, ampere1b, cobalt-100, grace{{$}} // RUN: not %clang_cc1 -triple i386--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix X86 // X86: error: unknown target CPU 'not-a-cpu' diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp index eecc21f35d8da..ef04a7c5bde8e 100644 --- a/llvm/unittests/TargetParser/TargetParserTest.cpp +++ b/llvm/unittests/TargetParser/TargetParserTest.cpp @@ -1815,7 +1815,7 @@ INSTANTIATE_TEST_SUITE_P( ARMCPUTestParams::PrintToStringParamName); // Note: number of CPUs includes aliases. -static constexpr unsigned NumAArch64CPUArchs = 76; +static constexpr unsigned NumAArch64CPUArchs = 77; TEST(TargetParserTest, testAArch64CPUArchList) { SmallVector List; From 6abf81ad8adddad1ca935281f800aa584cf93d98 Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Thu, 16 May 2024 18:49:23 +0100 Subject: [PATCH 09/19] Replace FeatureCrypto with AES+SHA2 for all CPUs This avoids the need to change a lot of TargetParserTest cases --- llvm/lib/Target/AArch64/AArch64Processors.td | 64 ++++++++++---------- 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td index 5537684b75238..669ef6c0d1d6a 100644 --- a/llvm/lib/Target/AArch64/AArch64Processors.td +++ b/llvm/lib/Target/AArch64/AArch64Processors.td @@ -618,9 +618,9 @@ def TuneAmpere1B : SubtargetFeature<"ampere1b", "ARMProcFamily", "Ampere1B", def ProcessorFeatures { - list A53 = [HasV8_0aOps, FeatureCRC, FeatureCrypto, + list A53 = [HasV8_0aOps, FeatureCRC, FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureNEON, FeaturePerfMon]; - list A55 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, + list A55 = [HasV8_2aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureNEON, FeatureFullFP16, FeatureDotProd, FeatureRCPC, FeaturePerfMon]; list A510 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon, @@ -633,25 +633,25 @@ def ProcessorFeatures { list A520AE = [HasV9_2aOps, FeaturePerfMon, FeatureAM, FeatureMTE, FeatureETE, FeatureSVE2BitPerm, FeatureFP16FML]; - list A65 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, + list A65 = [HasV8_2aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureNEON, FeatureFullFP16, FeatureDotProd, FeatureRCPC, FeatureSSBS, FeatureRAS, FeaturePerfMon]; - list A76 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, + list A76 = [HasV8_2aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureNEON, FeatureFullFP16, FeatureDotProd, FeatureRCPC, FeatureSSBS, FeaturePerfMon]; - list A77 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, + list A77 = [HasV8_2aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureNEON, FeatureFullFP16, FeatureDotProd, FeatureRCPC, FeaturePerfMon, FeatureSSBS]; - list A78 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, + list A78 = [HasV8_2aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureNEON, FeatureFullFP16, FeatureDotProd, FeatureRCPC, FeaturePerfMon, FeatureSPE, FeatureSSBS]; - list A78AE = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, + list A78AE = [HasV8_2aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureNEON, FeatureFullFP16, FeatureDotProd, FeatureRCPC, FeaturePerfMon, FeatureSPE, FeatureSSBS]; - list A78C = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, + list A78C = [HasV8_2aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureNEON, FeatureFullFP16, FeatureDotProd, FeatureFlagM, FeaturePAuth, FeaturePerfMon, FeatureRCPC, FeatureSPE, @@ -679,11 +679,11 @@ def ProcessorFeatures { FeatureSB, FeatureRDM, FeatureDotProd, FeatureComplxNum, FeatureJS, FeatureCacheDeepPersist]; - list X1 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, + list X1 = [HasV8_2aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureNEON, FeatureRCPC, FeaturePerfMon, FeatureSPE, FeatureFullFP16, FeatureDotProd, FeatureSSBS]; - list X1C = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, + list X1C = [HasV8_2aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureNEON, FeatureRCPC_IMMO, FeaturePerfMon, FeatureSPE, FeatureFullFP16, FeatureDotProd, FeaturePAuth, FeatureSSBS, FeatureFlagM, @@ -704,48 +704,48 @@ def ProcessorFeatures { list A64FX = [HasV8_2aOps, FeatureFPARMv8, FeatureNEON, FeatureSHA2, FeaturePerfMon, FeatureFullFP16, FeatureSVE, FeatureComplxNum]; - list Carmel = [HasV8_2aOps, FeatureNEON, FeatureCrypto, + list Carmel = [HasV8_2aOps, FeatureNEON, FeatureSHA2, FeatureAES, FeatureFullFP16]; - list AppleA7 = [HasV8_0aOps, FeatureCrypto, FeatureFPARMv8, + list AppleA7 = [HasV8_0aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureNEON,FeaturePerfMon, FeatureAppleA7SysReg]; - list AppleA10 = [HasV8_0aOps, FeatureCrypto, FeatureFPARMv8, + list AppleA10 = [HasV8_0aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureNEON, FeaturePerfMon, FeatureCRC, FeatureRDM, FeaturePAN, FeatureLOR, FeatureVH]; - list AppleA11 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, + list AppleA11 = [HasV8_2aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureNEON, FeaturePerfMon, FeatureFullFP16]; - list AppleA12 = [HasV8_3aOps, FeatureCrypto, FeatureFPARMv8, + list AppleA12 = [HasV8_3aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureNEON, FeaturePerfMon, FeatureFullFP16]; - list AppleA13 = [HasV8_4aOps, FeatureCrypto, FeatureFPARMv8, + list AppleA13 = [HasV8_4aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureNEON, FeaturePerfMon, FeatureFullFP16, FeatureFP16FML, FeatureSHA3]; - list AppleA14 = [HasV8_5aOps, FeatureCrypto, FeatureFPARMv8, + list AppleA14 = [HasV8_5aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureNEON, FeaturePerfMon, FeatureFRInt3264, FeatureSpecRestrict, FeatureSSBS, FeatureSB, FeaturePredRes, FeatureCacheDeepPersist, FeatureFullFP16, FeatureFP16FML, FeatureSHA3, FeatureAltFPCmp]; - list AppleA15 = [HasV8_6aOps, FeatureCrypto, FeatureFPARMv8, + list AppleA15 = [HasV8_6aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureNEON, FeaturePerfMon, FeatureSHA3, FeatureFullFP16, FeatureFP16FML]; - list AppleA16 = [HasV8_6aOps, FeatureCrypto, FeatureFPARMv8, + list AppleA16 = [HasV8_6aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureNEON, FeaturePerfMon, FeatureSHA3, FeatureFullFP16, FeatureFP16FML, FeatureHCX]; - list AppleA17 = [HasV8_6aOps, FeatureCrypto, FeatureFPARMv8, + list AppleA17 = [HasV8_6aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureNEON, FeaturePerfMon, FeatureSHA3, FeatureFullFP16, FeatureFP16FML, FeatureHCX]; - list ExynosM3 = [HasV8_0aOps, FeatureCRC, FeatureCrypto, + list ExynosM3 = [HasV8_0aOps, FeatureCRC, FeatureSHA2, FeatureAES, FeaturePerfMon]; - list ExynosM4 = [HasV8_2aOps, FeatureCrypto, FeatureDotProd, + list ExynosM4 = [HasV8_2aOps, FeatureSHA2, FeatureAES, FeatureDotProd, FeatureFullFP16, FeaturePerfMon]; - list Falkor = [HasV8_0aOps, FeatureCRC, FeatureCrypto, + list Falkor = [HasV8_0aOps, FeatureCRC, FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureNEON, FeaturePerfMon, FeatureRDM]; - list NeoverseE1 = [HasV8_2aOps, FeatureCrypto, FeatureDotProd, + list NeoverseE1 = [HasV8_2aOps, FeatureSHA2, FeatureAES, FeatureDotProd, FeatureFPARMv8, FeatureFullFP16, FeatureNEON, FeatureRCPC, FeatureSSBS, FeaturePerfMon]; - list NeoverseN1 = [HasV8_2aOps, FeatureCrypto, FeatureDotProd, + list NeoverseN1 = [HasV8_2aOps, FeatureSHA2, FeatureAES, FeatureDotProd, FeatureFPARMv8, FeatureFullFP16, FeatureNEON, FeatureRCPC, FeatureSPE, FeatureSSBS, FeaturePerfMon]; @@ -758,12 +758,12 @@ def ProcessorFeatures { FeatureRandGen, FeatureSPE, FeatureSPE_EEF, FeatureSVE2BitPerm]; list Neoverse512TVB = [HasV8_4aOps, FeatureBF16, FeatureCacheDeepPersist, - FeatureCrypto, FeatureFPARMv8, FeatureFP16FML, + FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureFP16FML, FeatureFullFP16, FeatureMatMulInt8, FeatureNEON, FeaturePerfMon, FeatureRandGen, FeatureSPE, FeatureSSBS, FeatureSVE]; list NeoverseV1 = [HasV8_4aOps, FeatureBF16, FeatureCacheDeepPersist, - FeatureCrypto, FeatureFPARMv8, FeatureFP16FML, + FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureFP16FML, FeatureFullFP16, FeatureMatMulInt8, FeatureNEON, FeaturePerfMon, FeatureRandGen, FeatureSPE, FeatureSSBS, FeatureSVE]; @@ -779,16 +779,16 @@ def ProcessorFeatures { FeatureFullFP16, FeatureLS64, FeatureMTE, FeaturePerfMon, FeatureRandGen, FeatureSPE, FeatureSPE_EEF, FeatureSVE2BitPerm, FeatureBRBE]; - list Saphira = [HasV8_4aOps, FeatureCrypto, FeatureFPARMv8, + list Saphira = [HasV8_4aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureNEON, FeatureSPE, FeaturePerfMon]; - list ThunderX = [HasV8_0aOps, FeatureCRC, FeatureCrypto, + list ThunderX = [HasV8_0aOps, FeatureCRC, FeatureSHA2, FeatureAES, FeatureFPARMv8, FeaturePerfMon, FeatureNEON]; - list ThunderX2T99 = [HasV8_1aOps, FeatureCRC, FeatureCrypto, + list ThunderX2T99 = [HasV8_1aOps, FeatureCRC, FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureNEON, FeatureLSE]; - list ThunderX3T110 = [HasV8_3aOps, FeatureCRC, FeatureCrypto, + list ThunderX3T110 = [HasV8_3aOps, FeatureCRC, FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureNEON, FeatureLSE, FeaturePAuth, FeaturePerfMon]; - list TSV110 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, + list TSV110 = [HasV8_2aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureNEON, FeaturePerfMon, FeatureSPE, FeatureFullFP16, FeatureFP16FML, FeatureDotProd, FeatureJS, FeatureComplxNum]; From f854899b66948e03e6ed9d6af0710e2f0cf7970b Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Thu, 16 May 2024 19:08:26 +0100 Subject: [PATCH 10/19] combine Implies and DefaultExts for cpus Fold CPU default extensions into the list of SubtargetFeatures TargetParserTest fixes because Implies and DefaultExts are combined Now that they are combined, more things are accounted for in the targetparser, i.e. more extensions are listed as being enabled for the given CPUs. clang test fixes because Implies and DefaultExts are combined --- clang/test/CodeGen/aarch64-targetattr.c | 12 +- .../Preprocessor/aarch64-target-features.c | 36 +- llvm/lib/Target/AArch64/AArch64Processors.td | 300 ++++++-------- .../TargetParser/TargetParserTest.cpp | 370 ++++++++++-------- llvm/utils/TableGen/ARMTargetDefEmitter.cpp | 15 +- 5 files changed, 362 insertions(+), 371 deletions(-) diff --git a/clang/test/CodeGen/aarch64-targetattr.c b/clang/test/CodeGen/aarch64-targetattr.c index 966f8b4bc7482..0edecf1621dc4 100644 --- a/clang/test/CodeGen/aarch64-targetattr.c +++ b/clang/test/CodeGen/aarch64-targetattr.c @@ -98,18 +98,18 @@ void minusarch() {} // CHECK: attributes #1 = { {{.*}} "target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+v8.1a,+v8.2a,+v8a" } // CHECK: attributes #2 = { {{.*}} "target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8a" } // CHECK: attributes #3 = { {{.*}} "target-features"="+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+ras,+rcpc,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" } -// CHECK: attributes #4 = { {{.*}} "target-cpu"="cortex-a710" "target-features"="+bf16,+complxnum,+crc,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+mte,+neon,+pauth,+ras,+rcpc,+rdm,+sb,+sve,+sve2,+sve2-bitperm" } +// CHECK: attributes #4 = { {{.*}} "target-cpu"="cortex-a710" "target-features"="+bf16,+complxnum,+crc,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+mte,+neon,+pauth,+perfmon,+ras,+rcpc,+rdm,+sb,+sve,+sve2,+sve2-bitperm" } // CHECK: attributes #5 = { {{.*}} "tune-cpu"="cortex-a710" } // CHECK: attributes #6 = { {{.*}} "target-cpu"="generic" "target-features"="+fp-armv8,+neon" } // CHECK: attributes #7 = { {{.*}} "tune-cpu"="generic" } -// CHECK: attributes #8 = { {{.*}} "target-cpu"="neoverse-n1" "target-features"="+aes,+crc,+dotprod,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs" "tune-cpu"="cortex-a710" } +// CHECK: attributes #8 = { {{.*}} "target-cpu"="neoverse-n1" "target-features"="+aes,+crc,+dotprod,+fp-armv8,+fullfp16,+lse,+neon,+perfmon,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs" "tune-cpu"="cortex-a710" } // CHECK: attributes #9 = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+sve" "tune-cpu"="cortex-a710" } -// CHECK: attributes #10 = { {{.*}} "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+sve,+sve2" } -// CHECK: attributes #11 = { {{.*}} "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,-sve" } +// CHECK: attributes #10 = { {{.*}} "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+sve,+sve2" } +// CHECK: attributes #11 = { {{.*}} "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,-sve" } // CHECK: attributes #12 = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+sve" } // CHECK: attributes #13 = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+sve,-sve2" } // CHECK: attributes #14 = { {{.*}} "target-features"="+fullfp16" } -// CHECK: attributes #15 = { {{.*}} "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" } -// CHECK: attributes #16 = { {{.*}} "branch-target-enforcement"="true" "guarded-control-stack"="true" {{.*}} "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" } +// CHECK: attributes #15 = { {{.*}} "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" } +// CHECK: attributes #16 = { {{.*}} "branch-target-enforcement"="true" "guarded-control-stack"="true" {{.*}} "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" } // CHECK: attributes #17 = { {{.*}} "target-features"="-neon" } // CHECK: attributes #18 = { {{.*}} "target-features"="-v9.3a" } diff --git a/clang/test/Preprocessor/aarch64-target-features.c b/clang/test/Preprocessor/aarch64-target-features.c index 82304a15a04a3..a90a4326bbb57 100644 --- a/clang/test/Preprocessor/aarch64-target-features.c +++ b/clang/test/Preprocessor/aarch64-target-features.c @@ -315,30 +315,30 @@ // RUN: %clang -target aarch64 -mcpu=thunderx2t99 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-THUNDERX2T99 %s // RUN: %clang -target aarch64 -mcpu=a64fx -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-A64FX %s // RUN: %clang -target aarch64 -mcpu=carmel -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-CARMEL %s -// CHECK-MCPU-APPLE-A7: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8a" "-target-feature" "+aes"{{.*}} "-target-feature" "+fp-armv8" "-target-feature" "+sha2" "-target-feature" "+neon" -// CHECK-MCPU-APPLE-A10: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8a" "-target-feature" "+aes"{{.*}} "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+rdm" "-target-feature" "+sha2" "-target-feature" "+neon" -// CHECK-MCPU-APPLE-A11: "-cc1"{{.*}} "-triple" "aarch64{{.*}}"{{.*}}"-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.2a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+lse" "-target-feature" "+ras" "-target-feature" "+rdm" "-target-feature" "+sha2" "-target-feature" "+neon" -// CHECK-MCPU-APPLE-A12: "-cc1"{{.*}} "-triple" "aarch64"{{.*}} "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.3a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+complxnum" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+pauth" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sha2" "-target-feature" "+neon" -// CHECK-MCPU-A34: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+sha2" "-target-feature" "+neon" -// CHECK-MCPU-APPLE-A13: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "apple-a13" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.4a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" "+complxnum" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+fp16fml" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+pauth" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sha2" "-target-feature" "+sha3" "-target-feature" "+neon" -// CHECK-MCPU-A35: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+sha2" "-target-feature" "+neon" -// CHECK-MCPU-A53: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+sha2" "-target-feature" "+neon" -// CHECK-MCPU-A57: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+sha2" "-target-feature" "+neon" -// CHECK-MCPU-A72: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+sha2" "-target-feature" "+neon" -// CHECK-MCPU-CORTEX-A73: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+sha2" "-target-feature" "+neon" +// CHECK-MCPU-APPLE-A7: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8a" "-target-feature" "+aes"{{.*}} "-target-feature" "+fp-armv8" "-target-feature" "+perfmon" "-target-feature" "+sha2" "-target-feature" "+neon" +// CHECK-MCPU-APPLE-A10: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8a" "-target-feature" "+aes"{{.*}} "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+perfmon" "-target-feature" "+rdm" "-target-feature" "+sha2" "-target-feature" "+neon" +// CHECK-MCPU-APPLE-A11: "-cc1"{{.*}} "-triple" "aarch64{{.*}}"{{.*}}"-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.2a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+lse" "-target-feature" "+perfmon" "-target-feature" "+ras" "-target-feature" "+rdm" "-target-feature" "+sha2" "-target-feature" "+neon" +// CHECK-MCPU-APPLE-A12: "-cc1"{{.*}} "-triple" "aarch64"{{.*}} "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.3a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+complxnum" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+pauth" "-target-feature" "+perfmon" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sha2" "-target-feature" "+neon" +// CHECK-MCPU-A34: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+perfmon" "-target-feature" "+sha2" "-target-feature" "+neon" +// CHECK-MCPU-APPLE-A13: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "apple-a13" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.4a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" "+complxnum" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+fp16fml" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+pauth" "-target-feature" "+perfmon" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sha2" "-target-feature" "+sha3" "-target-feature" "+neon" +// CHECK-MCPU-A35: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+perfmon" "-target-feature" "+sha2" "-target-feature" "+neon" +// CHECK-MCPU-A53: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+perfmon" "-target-feature" "+sha2" "-target-feature" "+neon" +// CHECK-MCPU-A57: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+perfmon" "-target-feature" "+sha2" "-target-feature" "+neon" +// CHECK-MCPU-A72: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+perfmon" "-target-feature" "+sha2" "-target-feature" "+neon" +// CHECK-MCPU-CORTEX-A73: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+perfmon" "-target-feature" "+sha2" "-target-feature" "+neon" // CHECK-MCPU-CORTEX-R82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8r" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" "+complxnum" "-target-feature" "+flagm" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+fp16fml" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+pauth" "-target-feature" "+perfmon" "-target-feature" "+predres" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sb" "-target-feature" "+neon" "-target-feature" "+ssbs" -// CHECK-MCPU-M3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+sha2" "-target-feature" "+neon" -// CHECK-MCPU-M4: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8.2a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+lse" "-target-feature" "+ras" "-target-feature" "+rdm" "-target-feature" "+sha2" "-target-feature" "+neon" -// CHECK-MCPU-KRYO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+sha2" "-target-feature" "+neon" +// CHECK-MCPU-M3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+perfmon" "-target-feature" "+sha2" "-target-feature" "+neon" +// CHECK-MCPU-M4: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8.2a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+lse" "-target-feature" "+perfmon" "-target-feature" "+ras" "-target-feature" "+rdm" "-target-feature" "+sha2" "-target-feature" "+neon" +// CHECK-MCPU-KRYO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+perfmon" "-target-feature" "+sha2" "-target-feature" "+neon" // CHECK-MCPU-THUNDERX2T99: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8.1a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+lse" "-target-feature" "+rdm" "-target-feature" "+sha2" "-target-feature" "+neon" -// CHECK-MCPU-A64FX: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8.2a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+lse" "-target-feature" "+ras" "-target-feature" "+rdm" "-target-feature" "+sha2" "-target-feature" "+neon" "-target-feature" "+sve" +// CHECK-MCPU-A64FX: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8.2a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+complxnum" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+lse" "-target-feature" "+perfmon" "-target-feature" "+ras" "-target-feature" "+rdm" "-target-feature" "+sha2" "-target-feature" "+neon" "-target-feature" "+sve" // CHECK-MCPU-CARMEL: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8.2a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+lse" "-target-feature" "+ras" "-target-feature" "+rdm" "-target-feature" "+sha2" "-target-feature" "+neon" // RUN: %clang -target x86_64-apple-macosx -arch arm64 -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-ARCH-ARM64 %s -// CHECK-ARCH-ARM64: "-target-cpu" "apple-m1" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.5a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" "+complxnum" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+fp16fml" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+pauth" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sha2" "-target-feature" "+sha3" "-target-feature" "+neon" +// CHECK-ARCH-ARM64: "-target-cpu" "apple-m1" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.5a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" "+complxnum" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+fp16fml" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+pauth" "-target-feature" "+perfmon" "-target-feature" "+predres" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sb" "-target-feature" "+sha2" "-target-feature" "+sha3" "-target-feature" "+neon" "-target-feature" "+ssbs" // RUN: %clang -target x86_64-apple-macosx -arch arm64_32 -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-ARCH-ARM64_32 %s -// CHECK-ARCH-ARM64_32: "-target-cpu" "apple-s4" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.3a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+complxnum" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+pauth" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sha2" "-target-feature" "+neon" +// CHECK-ARCH-ARM64_32: "-target-cpu" "apple-s4" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.3a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+complxnum" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+pauth" "-target-feature" "+perfmon" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sha2" "-target-feature" "+neon" // RUN: %clang -target aarch64 -march=armv8-a+fp+simd+crc+crypto -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MARCH-1 %s // RUN: %clang -target aarch64 -march=armv8-a+nofp+nosimd+nocrc+nocrypto+fp+simd+crc+crypto -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MARCH-1 %s @@ -464,7 +464,7 @@ // RUN: %clang -target aarch64 -mcpu=cortex-a53+noSIMD -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-3 %s // CHECK-MCPU-1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "-aes"{{.*}} "-target-feature" "-sha2" // CHECK-MCPU-2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+neon" -// CHECK-MCPU-3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "-aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "-sha2" "-target-feature" "-neon" +// CHECK-MCPU-3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "-aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+perfmon" "-target-feature" "-sha2" "-target-feature" "-neon" // RUN: %clang -target aarch64 -mcpu=cyclone+nocrc+nocrypto -march=armv8-a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-MARCH %s // RUN: %clang -target aarch64 -march=armv8-a -mcpu=cyclone+nocrc+nocrypto -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-MARCH %s diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td index 669ef6c0d1d6a..9da3fc10ff160 100644 --- a/llvm/lib/Target/AArch64/AArch64Processors.td +++ b/llvm/lib/Target/AArch64/AArch64Processors.td @@ -626,13 +626,16 @@ def ProcessorFeatures { list A510 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon, FeatureMatMulInt8, FeatureBF16, FeatureAM, FeatureMTE, FeatureETE, FeatureSVE2BitPerm, - FeatureFP16FML]; + FeatureFP16FML, + FeatureSB, FeaturePAuth, FeatureSSBS, FeatureSVE, FeatureSVE2]; list A520 = [HasV9_2aOps, FeaturePerfMon, FeatureAM, FeatureMTE, FeatureETE, FeatureSVE2BitPerm, - FeatureFP16FML]; + FeatureFP16FML, + FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes]; list A520AE = [HasV9_2aOps, FeaturePerfMon, FeatureAM, FeatureMTE, FeatureETE, FeatureSVE2BitPerm, - FeatureFP16FML]; + FeatureFP16FML, + FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes]; list A65 = [HasV8_2aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureNEON, FeatureFullFP16, FeatureDotProd, FeatureRCPC, FeatureSSBS, FeatureRAS, @@ -658,27 +661,33 @@ def ProcessorFeatures { FeatureSSBS]; list A710 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon, FeatureETE, FeatureMTE, FeatureFP16FML, - FeatureSVE2BitPerm, FeatureBF16, FeatureMatMulInt8]; + FeatureSVE2BitPerm, FeatureBF16, FeatureMatMulInt8, + FeaturePAuth, FeatureFlagM, FeatureSB, FeatureSVE, FeatureSVE2]; list A715 = [HasV9_0aOps, FeatureNEON, FeatureMTE, FeatureFP16FML, FeatureSVE, FeatureTRBE, FeatureSVE2BitPerm, FeatureBF16, FeatureETE, - FeaturePerfMon, FeatureMatMulInt8, FeatureSPE]; + FeaturePerfMon, FeatureMatMulInt8, FeatureSPE, + FeatureSB, FeatureSSBS, FeatureFullFP16, FeaturePAuth, FeaturePredRes, FeatureFlagM]; list A720 = [HasV9_2aOps, FeatureMTE, FeatureFP16FML, FeatureTRBE, FeatureSVE2BitPerm, FeatureETE, - FeaturePerfMon, FeatureSPE, FeatureSPE_EEF]; + FeaturePerfMon, FeatureSPE, FeatureSPE_EEF, + FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes]; list A720AE = [HasV9_2aOps, FeatureMTE, FeatureFP16FML, FeatureTRBE, FeatureSVE2BitPerm, FeatureETE, - FeaturePerfMon, FeatureSPE, FeatureSPE_EEF]; + FeaturePerfMon, FeatureSPE, FeatureSPE_EEF, + FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes]; list R82 = [HasV8_0rOps, FeaturePerfMon, FeatureFullFP16, FeatureFP16FML, FeatureSSBS, FeaturePredRes, FeatureSB, FeatureRDM, FeatureDotProd, FeatureComplxNum, FeatureJS, - FeatureCacheDeepPersist]; + FeatureCacheDeepPersist, + FeatureLSE, FeatureFlagM]; list R82AE = [HasV8_0rOps, FeaturePerfMon, FeatureFullFP16, FeatureFP16FML, FeatureSSBS, FeaturePredRes, FeatureSB, FeatureRDM, FeatureDotProd, FeatureComplxNum, FeatureJS, - FeatureCacheDeepPersist]; + FeatureCacheDeepPersist, + FeatureLSE, FeatureFlagM]; list X1 = [HasV8_2aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureNEON, FeatureRCPC, FeaturePerfMon, FeatureSPE, FeatureFullFP16, FeatureDotProd, @@ -687,23 +696,28 @@ def ProcessorFeatures { FeatureNEON, FeatureRCPC_IMMO, FeaturePerfMon, FeatureSPE, FeatureFullFP16, FeatureDotProd, FeaturePAuth, FeatureSSBS, FeatureFlagM, - FeatureLSE2]; + FeatureLSE2, + FeatureRCPC]; list X2 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon, FeatureMatMulInt8, FeatureBF16, FeatureAM, FeatureMTE, FeatureETE, FeatureSVE2BitPerm, - FeatureFP16FML]; + FeatureFP16FML, + FeaturePAuth, FeatureSSBS, FeatureSB, FeatureSVE, FeatureSVE2, FeatureFlagM]; list X3 = [HasV9_0aOps, FeatureSVE, FeatureNEON, FeaturePerfMon, FeatureETE, FeatureTRBE, FeatureSPE, FeatureBF16, FeatureMatMulInt8, FeatureMTE, FeatureSVE2BitPerm, FeatureFullFP16, - FeatureFP16FML]; + FeatureFP16FML, + FeatureSB, FeaturePAuth, FeaturePredRes, FeatureFlagM, FeatureSSBS]; list X4 = [HasV9_2aOps, FeaturePerfMon, FeatureETE, FeatureTRBE, FeatureSPE, FeatureMTE, FeatureSVE2BitPerm, - FeatureFP16FML, FeatureSPE_EEF]; + FeatureFP16FML, FeatureSPE_EEF, + FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes]; list A64FX = [HasV8_2aOps, FeatureFPARMv8, FeatureNEON, FeatureSHA2, FeaturePerfMon, FeatureFullFP16, - FeatureSVE, FeatureComplxNum]; + FeatureSVE, FeatureComplxNum, + FeatureAES]; list Carmel = [HasV8_2aOps, FeatureNEON, FeatureSHA2, FeatureAES, FeatureFullFP16]; list AppleA7 = [HasV8_0aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8, @@ -752,33 +766,40 @@ def ProcessorFeatures { list NeoverseN2 = [HasV9_0aOps, FeatureBF16, FeatureETE, FeatureFP16FML, FeatureMatMulInt8, FeatureMTE, FeatureSVE2, FeatureSVE2BitPerm, FeatureTRBE, - FeaturePerfMon]; + FeaturePerfMon, + FeatureDotProd, FeatureFullFP16, FeatureSB, FeatureSSBS, FeatureSVE]; list NeoverseN3 = [HasV9_2aOps, FeatureETE, FeatureFP16FML, FeatureFullFP16, FeatureMTE, FeaturePerfMon, FeatureRandGen, FeatureSPE, FeatureSPE_EEF, - FeatureSVE2BitPerm]; + FeatureSVE2BitPerm, + FeatureSSBS, FeatureSB, FeaturePredRes, FeaturePAuth, FeatureFlagM]; list Neoverse512TVB = [HasV8_4aOps, FeatureBF16, FeatureCacheDeepPersist, FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureFP16FML, FeatureFullFP16, FeatureMatMulInt8, FeatureNEON, FeaturePerfMon, FeatureRandGen, FeatureSPE, - FeatureSSBS, FeatureSVE]; + FeatureSSBS, FeatureSVE, + FeatureSHA3, FeatureSM4, FeatureDotProd]; list NeoverseV1 = [HasV8_4aOps, FeatureBF16, FeatureCacheDeepPersist, FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureFP16FML, FeatureFullFP16, FeatureMatMulInt8, FeatureNEON, FeaturePerfMon, FeatureRandGen, FeatureSPE, - FeatureSSBS, FeatureSVE]; + FeatureSSBS, FeatureSVE, + FeatureSHA3, FeatureSM4, FeatureDotProd]; list NeoverseV2 = [HasV9_0aOps, FeatureBF16, FeatureSPE, FeaturePerfMon, FeatureETE, FeatureMatMulInt8, FeatureNEON, FeatureSVE2BitPerm, FeatureFP16FML, - FeatureMTE, FeatureRandGen]; + FeatureMTE, FeatureRandGen, + FeatureSVE, FeatureSVE2, FeatureSSBS, FeatureFullFP16, FeatureDotProd]; list NeoverseV3 = [HasV9_2aOps, FeatureETE, FeatureFP16FML, FeatureFullFP16, FeatureLS64, FeatureMTE, FeaturePerfMon, FeatureRandGen, FeatureSPE, - FeatureSPE_EEF, FeatureSVE2BitPerm, FeatureBRBE]; + FeatureSPE_EEF, FeatureSVE2BitPerm, FeatureBRBE, + FeatureSSBS, FeatureSB, FeaturePredRes, FeaturePAuth, FeatureFlagM]; list NeoverseV3AE = [HasV9_2aOps, FeatureETE, FeatureFP16FML, FeatureFullFP16, FeatureLS64, FeatureMTE, FeaturePerfMon, FeatureRandGen, FeatureSPE, - FeatureSPE_EEF, FeatureSVE2BitPerm, FeatureBRBE]; + FeatureSPE_EEF, FeatureSVE2BitPerm, FeatureBRBE, + FeatureSSBS, FeatureSB, FeaturePredRes, FeaturePAuth, FeatureFlagM]; list Saphira = [HasV8_4aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureNEON, FeatureSPE, FeaturePerfMon]; list ThunderX = [HasV8_0aOps, FeatureCRC, FeatureSHA2, FeatureAES, @@ -794,11 +815,13 @@ def ProcessorFeatures { FeatureJS, FeatureComplxNum]; list Ampere1 = [HasV8_6aOps, FeatureNEON, FeaturePerfMon, FeatureSSBS, FeatureRandGen, FeatureSB, - FeatureSHA2, FeatureSHA3, FeatureAES]; + FeatureSHA2, FeatureSHA3, FeatureAES, + FeatureFullFP16]; list Ampere1A = [HasV8_6aOps, FeatureNEON, FeaturePerfMon, FeatureMTE, FeatureSSBS, FeatureRandGen, FeatureSB, FeatureSM4, FeatureSHA2, - FeatureSHA3, FeatureAES]; + FeatureSHA3, FeatureAES, + FeatureFullFP16]; list Ampere1B = [HasV8_7aOps, FeatureNEON, FeaturePerfMon, FeatureMTE, FeatureSSBS, FeatureRandGen, FeatureSB, FeatureSM4, FeatureSHA2, @@ -817,266 +840,187 @@ class AArch64Processor< Architecture64 arch, SchedMachineModel m, list f, - list tunef, - list default_extensions + list tunef > : ProcessorModel { // The base architecture for this processor. Architecture64 Arch = arch; - - // The set of extensions enabled by default for this processor. - list DefaultExts = default_extensions; } // FeatureFuseAdrpAdd is enabled under Generic to allow linker merging // optimizations. def : AArch64Processor<"generic", HasV8_0aOps, CortexA510Model, ProcessorFeatures.Generic, [FeatureFuseAES, FeatureFuseAdrpAdd, FeaturePostRAScheduler, - FeatureEnableSelectOptimize], - [FeatureNEON]>; + FeatureEnableSelectOptimize]>; // Alias for the latest Apple processor model supported by LLVM. def : ProcessorModel<"apple-latest", CycloneModel, ProcessorFeatures.AppleA16, [TuneAppleA16]>; def : AArch64Processor<"cortex-a34", HasV8_0aOps, CortexA53Model, ProcessorFeatures.A53, - [TuneA35], - [FeatureAES, FeatureSHA2, FeatureCRC]>; + [TuneA35]>; def : AArch64Processor<"cortex-a35", HasV8_0aOps, CortexA53Model, ProcessorFeatures.A53, - [TuneA35], - [FeatureAES, FeatureSHA2, FeatureCRC]>; + [TuneA35]>; def : AArch64Processor<"cortex-a53", HasV8_0aOps, CortexA53Model, ProcessorFeatures.A53, - [TuneA53], - [FeatureAES, FeatureSHA2, FeatureCRC]>; + [TuneA53]>; def : AArch64Processor<"cortex-a55", HasV8_2aOps, CortexA55Model, ProcessorFeatures.A55, - [TuneA55], - [FeatureAES, FeatureSHA2, FeatureFullFP16, FeatureDotProd, FeatureRCPC]>; + [TuneA55]>; def : AArch64Processor<"cortex-a510", HasV9_0aOps, CortexA510Model, ProcessorFeatures.A510, - [TuneA510], - [FeatureBF16, FeatureMatMulInt8, FeatureSB, FeaturePAuth, FeatureMTE, FeatureSSBS, FeatureSVE, FeatureSVE2, FeatureSVE2BitPerm, FeatureFP16FML]>; + [TuneA510]>; def : AArch64Processor<"cortex-a520", HasV9_2aOps, CortexA510Model, ProcessorFeatures.A520, - [TuneA520], - [FeatureSB, FeatureSSBS, FeatureMTE, FeatureFP16FML, FeaturePAuth, FeatureSVE2BitPerm, FeatureFlagM, FeaturePerfMon, FeaturePredRes]>; + [TuneA520]>; def : AArch64Processor<"cortex-a520ae", HasV9_2aOps, CortexA510Model, ProcessorFeatures.A520AE, - [TuneA520AE], - [FeatureSB, FeatureSSBS, FeatureMTE, FeatureFP16FML, FeaturePAuth, FeatureSVE2BitPerm, FeatureFlagM, FeaturePerfMon, FeaturePredRes]>; + [TuneA520AE]>; def : AArch64Processor<"cortex-a57", HasV8_0aOps, CortexA57Model, ProcessorFeatures.A53, - [TuneA57], - [FeatureAES, FeatureSHA2, FeatureCRC]>; + [TuneA57]>; def : AArch64Processor<"cortex-a65", HasV8_2aOps, CortexA53Model, ProcessorFeatures.A65, - [TuneA65], - [FeatureAES, FeatureSHA2, FeatureDotProd, FeatureFullFP16, FeatureRCPC, FeatureSSBS]>; + [TuneA65]>; def : AArch64Processor<"cortex-a65ae", HasV8_2aOps, CortexA53Model, ProcessorFeatures.A65, - [TuneA65], - [FeatureAES, FeatureSHA2, FeatureDotProd, FeatureFullFP16, FeatureRCPC, FeatureSSBS]>; + [TuneA65]>; def : AArch64Processor<"cortex-a72", HasV8_0aOps, CortexA57Model, ProcessorFeatures.A53, - [TuneA72], - [FeatureAES, FeatureSHA2, FeatureCRC]>; + [TuneA72]>; def : AArch64Processor<"cortex-a73", HasV8_0aOps, CortexA57Model, ProcessorFeatures.A53, - [TuneA73], - [FeatureAES, FeatureSHA2, FeatureCRC]>; + [TuneA73]>; def : AArch64Processor<"cortex-a75", HasV8_2aOps, CortexA57Model, ProcessorFeatures.A55, - [TuneA75], - [FeatureAES, FeatureSHA2, FeatureFullFP16, FeatureDotProd, FeatureRCPC]>; + [TuneA75]>; def : AArch64Processor<"cortex-a76", HasV8_2aOps, CortexA57Model, ProcessorFeatures.A76, - [TuneA76], - [FeatureAES, FeatureSHA2, FeatureFullFP16, FeatureDotProd, FeatureRCPC, FeatureSSBS]>; + [TuneA76]>; def : AArch64Processor<"cortex-a76ae", HasV8_2aOps, CortexA57Model, ProcessorFeatures.A76, - [TuneA76], - [FeatureAES, FeatureSHA2, FeatureFullFP16, FeatureDotProd, FeatureRCPC, FeatureSSBS]>; + [TuneA76]>; def : AArch64Processor<"cortex-a77", HasV8_2aOps, CortexA57Model, ProcessorFeatures.A77, - [TuneA77], - [FeatureAES, FeatureSHA2, FeatureFullFP16, FeatureRCPC, FeatureDotProd, FeatureSSBS]>; + [TuneA77]>; def : AArch64Processor<"cortex-a78", HasV8_2aOps, CortexA57Model, ProcessorFeatures.A78, - [TuneA78], - [FeatureAES, FeatureSHA2, FeatureFullFP16, FeatureDotProd, FeatureRCPC, FeatureSSBS, FeatureSPE]>; + [TuneA78]>; def : AArch64Processor<"cortex-a78ae", HasV8_2aOps, CortexA57Model, ProcessorFeatures.A78AE, - [TuneA78AE], - [FeatureAES, FeatureSHA2, FeatureFullFP16, FeatureDotProd, FeatureRCPC, FeatureSSBS, FeatureSPE]>; + [TuneA78AE]>; def : AArch64Processor<"cortex-a78c", HasV8_2aOps, CortexA57Model, ProcessorFeatures.A78C, - [TuneA78C], - [FeatureAES, FeatureSHA2, FeatureFullFP16, FeatureDotProd, FeatureRCPC, FeatureSSBS, FeatureSPE, FeatureFlagM, FeaturePAuth]>; + [TuneA78C]>; def : AArch64Processor<"cortex-a710", HasV9_0aOps, NeoverseN2Model, ProcessorFeatures.A710, - [TuneA710], - [FeatureMTE, FeaturePAuth, FeatureFlagM, FeatureSB, FeatureMatMulInt8, FeatureFP16FML, FeatureSVE, FeatureSVE2, FeatureSVE2BitPerm, FeatureBF16]>; + [TuneA710]>; def : AArch64Processor<"cortex-a715", HasV9_0aOps, NeoverseN2Model, ProcessorFeatures.A715, - [TuneA715], - [FeatureSB, FeatureSSBS, FeatureMTE, FeatureFullFP16, FeatureFP16FML, FeaturePAuth, FeatureMatMulInt8, FeaturePredRes, FeaturePerfMon, FeatureSPE, FeatureSVE, FeatureSVE2BitPerm, FeatureBF16, FeatureFlagM]>; + [TuneA715]>; def : AArch64Processor<"cortex-a720", HasV9_2aOps, NeoverseN2Model, ProcessorFeatures.A720, - [TuneA720], - [FeatureSB, FeatureSSBS, FeatureMTE, FeatureFP16FML, FeaturePAuth, FeatureSVE2BitPerm, FeatureFlagM, FeaturePerfMon, FeaturePredRes, FeatureSPE]>; + [TuneA720]>; def : AArch64Processor<"cortex-a720ae", HasV9_2aOps, NeoverseN2Model, ProcessorFeatures.A720AE, - [TuneA720AE], - [FeatureSB, FeatureSSBS, FeatureMTE, FeatureFP16FML, FeaturePAuth, FeatureSVE2BitPerm, FeatureFlagM, FeaturePerfMon, FeaturePredRes, FeatureSPE]>; + [TuneA720AE]>; def : AArch64Processor<"cortex-r82", HasV8_0rOps, CortexA55Model, ProcessorFeatures.R82, - [TuneR82], - [FeatureLSE, FeatureFlagM, FeaturePerfMon, FeaturePredRes]>; + [TuneR82]>; def : AArch64Processor<"cortex-r82ae", HasV8_0rOps, CortexA55Model, ProcessorFeatures.R82AE, - [TuneR82AE], - [FeatureLSE, FeatureFlagM, FeaturePerfMon, FeaturePredRes]>; + [TuneR82AE]>; def : AArch64Processor<"cortex-x1", HasV8_2aOps, CortexA57Model, ProcessorFeatures.X1, - [TuneX1], - [FeatureAES, FeatureSHA2, FeatureFullFP16, FeatureDotProd, FeatureRCPC, FeatureSSBS, FeatureSPE]>; + [TuneX1]>; def : AArch64Processor<"cortex-x1c", HasV8_2aOps, CortexA57Model, ProcessorFeatures.X1C, - [TuneX1], - [FeatureAES, FeatureSHA2, FeatureFullFP16, FeatureDotProd, FeatureRCPC, FeatureSSBS, FeaturePAuth, FeatureSPE, FeatureFlagM]>; + [TuneX1]>; def : AArch64Processor<"cortex-x2", HasV9_0aOps, NeoverseN2Model, ProcessorFeatures.X2, - [TuneX2], - [FeatureMTE, FeatureBF16, FeatureMatMulInt8, FeaturePAuth, FeatureSSBS, FeatureSB, FeatureSVE, FeatureSVE2, FeatureSVE2BitPerm, FeatureFP16FML, FeatureFlagM]>; + [TuneX2]>; def : AArch64Processor<"cortex-x3", HasV9_0aOps, NeoverseN2Model, ProcessorFeatures.X3, - [TuneX3], - [FeatureSVE, FeaturePerfMon, FeatureSPE, FeatureBF16, FeatureMatMulInt8, FeatureMTE, FeatureSVE2BitPerm, FeatureSB, FeaturePAuth, FeatureFullFP16, FeatureFP16FML, FeaturePredRes, FeatureFlagM, FeatureSSBS]>; + [TuneX3]>; def : AArch64Processor<"cortex-x4", HasV9_2aOps, NeoverseN2Model, ProcessorFeatures.X4, - [TuneX4], - [FeatureSB, FeatureSSBS, FeatureMTE, FeatureFP16FML, FeaturePAuth, FeatureSVE2BitPerm, FeatureFlagM, FeaturePerfMon, FeaturePredRes, FeatureSPE]>; + [TuneX4]>; def : AArch64Processor<"neoverse-e1", HasV8_2aOps, CortexA53Model, ProcessorFeatures.NeoverseE1, - [TuneNeoverseE1], - [FeatureAES, FeatureSHA2, FeatureDotProd, FeatureFullFP16, FeatureRCPC, FeatureSSBS]>; + [TuneNeoverseE1]>; def : AArch64Processor<"neoverse-n1", HasV8_2aOps, NeoverseN1Model, ProcessorFeatures.NeoverseN1, - [TuneNeoverseN1], - [FeatureAES, FeatureSHA2, FeatureDotProd, FeatureFullFP16, FeatureSPE, FeatureRCPC, FeatureSSBS]>; + [TuneNeoverseN1]>; def : AArch64Processor<"neoverse-n2", HasV9_0aOps, NeoverseN2Model, ProcessorFeatures.NeoverseN2, - [TuneNeoverseN2], - [FeatureBF16, FeatureDotProd, FeatureFullFP16, FeatureFP16FML, FeatureMatMulInt8, FeatureMTE, FeatureSB, FeatureSSBS, FeatureSVE, FeatureSVE2, FeatureSVE2BitPerm]>; + [TuneNeoverseN2]>; def : AArch64Processor<"neoverse-n3", HasV9_2aOps, NeoverseN2Model, ProcessorFeatures.NeoverseN3, - [TuneNeoverseN3], - [FeatureMTE, FeatureSSBS, FeatureSB, FeaturePredRes, FeatureFP16FML, FeaturePAuth, FeatureFlagM, FeaturePerfMon, FeatureRandGen, FeatureSVE2BitPerm, FeatureSPE, FeaturePerfMon]>; + [TuneNeoverseN3]>; def : AArch64Processor<"neoverse-512tvb", HasV8_4aOps, NeoverseV1Model, ProcessorFeatures.Neoverse512TVB, - [TuneNeoverse512TVB], - [FeatureAES, FeatureSHA2, FeatureSHA3, FeatureSM4, FeatureSVE, FeatureSSBS, FeatureFullFP16, FeatureBF16, FeatureDotProd, FeatureSPE, FeatureRandGen, FeatureFP16FML, FeatureMatMulInt8]>; + [TuneNeoverse512TVB]>; def : AArch64Processor<"neoverse-v1", HasV8_4aOps, NeoverseV1Model, ProcessorFeatures.NeoverseV1, - [TuneNeoverseV1], - [FeatureAES, FeatureSHA2, FeatureSHA3, FeatureSM4, FeatureSVE, FeatureSSBS, FeatureFullFP16, FeatureBF16, FeatureDotProd, FeatureSPE, FeatureRandGen, FeatureFP16FML, FeatureMatMulInt8]>; + [TuneNeoverseV1]>; def : AArch64Processor<"neoverse-v2", HasV9_0aOps, NeoverseV2Model, ProcessorFeatures.NeoverseV2, - [TuneNeoverseV2], - [FeatureSVE, FeatureSVE2, FeatureSSBS, FeatureFullFP16, FeatureBF16, FeatureRandGen, FeatureDotProd, FeatureSPE, FeatureSVE2BitPerm, FeatureFP16FML, FeatureMatMulInt8, FeatureMTE]>; + [TuneNeoverseV2]>; def : AArch64Processor<"neoverse-v3", HasV9_2aOps, NeoverseV2Model, ProcessorFeatures.NeoverseV3, - [TuneNeoverseV3], - [FeatureSPE, FeatureMTE, FeatureSSBS, FeatureSB, FeaturePredRes, FeatureLS64, FeatureBRBE, FeaturePAuth, FeatureFlagM, FeaturePerfMon, FeatureRandGen, FeatureSVE2BitPerm, FeatureFP16FML]>; + [TuneNeoverseV3]>; def : AArch64Processor<"neoverse-v3ae", HasV9_2aOps, NeoverseV2Model, ProcessorFeatures.NeoverseV3AE, - [TuneNeoverseV3AE], - [FeatureSPE, FeatureMTE, FeatureSSBS, FeatureSB, FeaturePredRes, FeatureLS64, FeatureBRBE, FeaturePAuth, FeatureFlagM, FeaturePerfMon, FeatureRandGen, FeatureSVE2BitPerm, FeatureFP16FML]>; + [TuneNeoverseV3AE]>; def : AArch64Processor<"exynos-m3", HasV8_0aOps, ExynosM3Model, ProcessorFeatures.ExynosM3, - [TuneExynosM3], - [FeatureAES, FeatureSHA2, FeatureCRC]>; + [TuneExynosM3]>; def : AArch64Processor<"exynos-m4", HasV8_2aOps, ExynosM4Model, ProcessorFeatures.ExynosM4, - [TuneExynosM4], - [FeatureAES, FeatureSHA2, FeatureDotProd, FeatureFullFP16]>; + [TuneExynosM4]>; def : AArch64Processor<"exynos-m5", HasV8_2aOps, ExynosM5Model, ProcessorFeatures.ExynosM4, - [TuneExynosM4], - [FeatureAES, FeatureSHA2, FeatureDotProd, FeatureFullFP16]>; + [TuneExynosM4]>; def : AArch64Processor<"falkor", HasV8_0aOps, FalkorModel, ProcessorFeatures.Falkor, - [TuneFalkor], - [FeatureAES, FeatureSHA2, FeatureCRC, FeatureRDM]>; + [TuneFalkor]>; def : AArch64Processor<"saphira", HasV8_4aOps, FalkorModel, ProcessorFeatures.Saphira, - [TuneSaphira], - [FeatureAES, FeatureSHA2, FeatureSPE]>; + [TuneSaphira]>; def : AArch64Processor<"kryo", HasV8_0aOps, KryoModel, ProcessorFeatures.A53, - [TuneKryo], - [FeatureAES, FeatureSHA2, FeatureCRC]>; + [TuneKryo]>; // Cavium ThunderX/ThunderX T8X Processors def : AArch64Processor<"thunderx", HasV8_0aOps, ThunderXT8XModel, ProcessorFeatures.ThunderX, - [TuneThunderX], - [FeatureAES, FeatureSHA2, FeatureCRC]>; + [TuneThunderX]>; def : AArch64Processor<"thunderxt88", HasV8_0aOps, ThunderXT8XModel, ProcessorFeatures.ThunderX, - [TuneThunderXT88], - [FeatureAES, FeatureSHA2, FeatureCRC]>; + [TuneThunderXT88]>; def : AArch64Processor<"thunderxt81", HasV8_0aOps, ThunderXT8XModel, ProcessorFeatures.ThunderX, - [TuneThunderXT81], - [FeatureAES, FeatureSHA2, FeatureCRC]>; + [TuneThunderXT81]>; def : AArch64Processor<"thunderxt83", HasV8_0aOps, ThunderXT8XModel, ProcessorFeatures.ThunderX, - [TuneThunderXT83], - [FeatureAES, FeatureSHA2, FeatureCRC]>; + [TuneThunderXT83]>; // Cavium ThunderX2T9X Processors. Formerly Broadcom Vulcan. def : AArch64Processor<"thunderx2t99", HasV8_1aOps, ThunderX2T99Model, ProcessorFeatures.ThunderX2T99, - [TuneThunderX2T99], - [FeatureAES, FeatureSHA2]>; + [TuneThunderX2T99]>; // Marvell ThunderX3T110 Processors. def : AArch64Processor<"thunderx3t110", HasV8_3aOps, ThunderX3T110Model, ProcessorFeatures.ThunderX3T110, - [TuneThunderX3T110], - [FeatureAES, FeatureSHA2]>; + [TuneThunderX3T110]>; def : AArch64Processor<"tsv110", HasV8_2aOps, TSV110Model, ProcessorFeatures.TSV110, - [TuneTSV110], - [FeatureAES, FeatureSHA2, FeatureDotProd, FeatureFullFP16, FeatureFP16FML, FeatureSPE, FeatureJS, FeatureComplxNum]>; + [TuneTSV110]>; // Support cyclone as an alias for apple-a7 so we can still LTO old bitcode. def : AArch64Processor<"cyclone", HasV8_0aOps, CycloneModel, ProcessorFeatures.AppleA7, - [TuneAppleA7], - [FeatureAES, FeatureSHA2]>; + [TuneAppleA7]>; // iPhone and iPad CPUs def : AArch64Processor<"apple-a7", HasV8_0aOps, CycloneModel, ProcessorFeatures.AppleA7, - [TuneAppleA7], - [FeatureAES, FeatureSHA2]>; + [TuneAppleA7]>; def : AArch64Processor<"apple-a8", HasV8_0aOps, CycloneModel, ProcessorFeatures.AppleA7, - [TuneAppleA7], - [FeatureAES, FeatureSHA2]>; + [TuneAppleA7]>; def : AArch64Processor<"apple-a9", HasV8_0aOps, CycloneModel, ProcessorFeatures.AppleA7, - [TuneAppleA7], - [FeatureAES, FeatureSHA2]>; + [TuneAppleA7]>; def : AArch64Processor<"apple-a10", HasV8_0aOps, CycloneModel, ProcessorFeatures.AppleA10, - [TuneAppleA10], - [FeatureAES, FeatureSHA2, FeatureCRC, FeatureRDM]>; + [TuneAppleA10]>; def : AArch64Processor<"apple-a11", HasV8_2aOps, CycloneModel, ProcessorFeatures.AppleA11, - [TuneAppleA11], - [FeatureAES, FeatureSHA2, FeatureFullFP16]>; + [TuneAppleA11]>; def : AArch64Processor<"apple-a12", HasV8_3aOps, CycloneModel, ProcessorFeatures.AppleA12, - [TuneAppleA12], - [FeatureAES, FeatureSHA2, FeatureFullFP16]>; + [TuneAppleA12]>; def : AArch64Processor<"apple-a13", HasV8_4aOps, CycloneModel, ProcessorFeatures.AppleA13, - [TuneAppleA13], - [FeatureAES, FeatureSHA2, FeatureSHA3, FeatureFullFP16, FeatureFP16FML]>; + [TuneAppleA13]>; def : AArch64Processor<"apple-a14", HasV8_5aOps, CycloneModel, ProcessorFeatures.AppleA14, - [TuneAppleA14], - [FeatureAES, FeatureSHA2, FeatureSHA3, FeatureFullFP16, FeatureFP16FML]>; + [TuneAppleA14]>; def : AArch64Processor<"apple-a15", HasV8_6aOps, CycloneModel, ProcessorFeatures.AppleA15, - [TuneAppleA15], - [FeatureAES, FeatureSHA2, FeatureSHA3, FeatureFullFP16, FeatureFP16FML]>; + [TuneAppleA15]>; // Alias for the latest Apple processor model supported by LLVM. def : AArch64Processor<"apple-a16", HasV8_6aOps, CycloneModel, ProcessorFeatures.AppleA16, - [TuneAppleA16], - [FeatureAES, FeatureSHA2, FeatureSHA3, FeatureFullFP16, FeatureFP16FML]>; + [TuneAppleA16]>; def : AArch64Processor<"apple-a17", HasV8_6aOps, CycloneModel, ProcessorFeatures.AppleA17, - [TuneAppleA17], - [FeatureAES, FeatureSHA2, FeatureSHA3, FeatureFullFP16, FeatureFP16FML]>; + [TuneAppleA17]>; // Mac CPUs def : AArch64Processor<"apple-m1", HasV8_5aOps, CycloneModel, ProcessorFeatures.AppleA14, - [TuneAppleA14], - [FeatureAES, FeatureSHA2, FeatureSHA3, FeatureFullFP16, FeatureFP16FML]>; + [TuneAppleA14]>; def : AArch64Processor<"apple-m2", HasV8_6aOps, CycloneModel, ProcessorFeatures.AppleA15, - [TuneAppleA15], - [FeatureAES, FeatureSHA2, FeatureSHA3, FeatureFullFP16, FeatureFP16FML]>; + [TuneAppleA15]>; def : AArch64Processor<"apple-m3", HasV8_6aOps, CycloneModel, ProcessorFeatures.AppleA16, - [TuneAppleA16], - [FeatureAES, FeatureSHA2, FeatureSHA3, FeatureFullFP16, FeatureFP16FML]>; + [TuneAppleA16]>; // watch CPUs. def : AArch64Processor<"apple-s4", HasV8_3aOps, CycloneModel, ProcessorFeatures.AppleA12, - [TuneAppleA12], - [FeatureAES, FeatureSHA2, FeatureFullFP16]>; + [TuneAppleA12]>; def : AArch64Processor<"apple-s5", HasV8_3aOps, CycloneModel, ProcessorFeatures.AppleA12, - [TuneAppleA12], - [FeatureAES, FeatureSHA2, FeatureFullFP16]>; + [TuneAppleA12]>; // Fujitsu A64FX def : AArch64Processor<"a64fx", HasV8_2aOps, A64FXModel, ProcessorFeatures.A64FX, - [TuneA64FX], - [FeatureAES, FeatureSHA2, FeatureFullFP16, FeatureSVE]>; + [TuneA64FX]>; // Nvidia Carmel def : AArch64Processor<"carmel", HasV8_2aOps, NoSchedModel, ProcessorFeatures.Carmel, - [TuneCarmel], - [FeatureAES, FeatureSHA2, FeatureFullFP16]>; + [TuneCarmel]>; // Ampere Computing def : AArch64Processor<"ampere1", HasV8_6aOps, Ampere1Model, ProcessorFeatures.Ampere1, - [TuneAmpere1], - [FeatureAES, FeatureSHA2, FeatureSHA3, FeatureFullFP16, FeatureSB, FeatureSSBS, FeatureRandGen]>; + [TuneAmpere1]>; def : AArch64Processor<"ampere1a", HasV8_6aOps, Ampere1Model, ProcessorFeatures.Ampere1A, - [TuneAmpere1A], - [FeatureFullFP16, FeatureRandGen, FeatureSM4, FeatureSHA3, FeatureSHA2, FeatureAES, FeatureMTE, FeatureSB, FeatureSSBS]>; + [TuneAmpere1A]>; def : AArch64Processor<"ampere1b", HasV8_7aOps, Ampere1BModel, ProcessorFeatures.Ampere1B, - [TuneAmpere1B], - [FeatureFullFP16, FeatureRandGen, FeatureSM4, FeatureSHA3, FeatureSHA2, FeatureAES, FeatureMTE, FeatureSB, FeatureSSBS, FeatureCSSC]>; + [TuneAmpere1B]>; diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp index ef04a7c5bde8e..baa08383b22b4 100644 --- a/llvm/unittests/TargetParser/TargetParserTest.cpp +++ b/llvm/unittests/TargetParser/TargetParserTest.cpp @@ -1087,27 +1087,28 @@ INSTANTIATE_TEST_SUITE_P( "cortex-a34", "armv8-a", "crypto-neon-fp-armv8", AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP, - AArch64::AEK_SIMD}), + AArch64::AEK_SIMD, AArch64::AEK_PERFMON}), "8-A"), ARMCPUTestParams( "cortex-a35", "armv8-a", "crypto-neon-fp-armv8", AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP, - AArch64::AEK_SIMD}), + AArch64::AEK_SIMD, AArch64::AEK_PERFMON}), "8-A"), ARMCPUTestParams( "cortex-a53", "armv8-a", "crypto-neon-fp-armv8", AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP, - AArch64::AEK_SIMD}), + AArch64::AEK_SIMD, AArch64::AEK_PERFMON}), "8-A"), ARMCPUTestParams( "cortex-a55", "armv8.2-a", "crypto-neon-fp-armv8", - AArch64::ExtensionBitset( - {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_FP, AArch64::AEK_SIMD, AArch64::AEK_RAS, - AArch64::AEK_LSE, AArch64::AEK_RDM, AArch64::AEK_FP16, - AArch64::AEK_DOTPROD, AArch64::AEK_RCPC}), + AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES, + AArch64::AEK_SHA2, AArch64::AEK_FP, + AArch64::AEK_SIMD, AArch64::AEK_RAS, + AArch64::AEK_LSE, AArch64::AEK_RDM, + AArch64::AEK_FP16, AArch64::AEK_DOTPROD, + AArch64::AEK_RCPC, AArch64::AEK_PERFMON}), "8.2-A"), ARMCPUTestParams( "cortex-a510", "armv9-a", "neon-fp-armv8", @@ -1122,7 +1123,7 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_MTE, AArch64::AEK_SSBS, AArch64::AEK_FP16, AArch64::AEK_FP16FML, AArch64::AEK_SB, AArch64::AEK_JSCVT, - AArch64::AEK_FCMA}), + AArch64::AEK_FCMA, AArch64::AEK_PERFMON}), "9-A"), ARMCPUTestParams( "cortex-a520", "armv9.2-a", "crypto-neon-fp-armv8", @@ -1138,7 +1139,8 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_FP16FML, AArch64::AEK_PAUTH, AArch64::AEK_SVE2BITPERM, AArch64::AEK_FLAGM, AArch64::AEK_PERFMON, AArch64::AEK_PREDRES, - AArch64::AEK_JSCVT, AArch64::AEK_FCMA}), + AArch64::AEK_JSCVT, AArch64::AEK_FCMA, + AArch64::AEK_PERFMON}), "9.2-A"), ARMCPUTestParams( "cortex-a520ae", "armv9.2-a", "crypto-neon-fp-armv8", @@ -1154,13 +1156,14 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_FP16FML, AArch64::AEK_PAUTH, AArch64::AEK_SVE2BITPERM, AArch64::AEK_FLAGM, AArch64::AEK_PERFMON, AArch64::AEK_PREDRES, - AArch64::AEK_JSCVT, AArch64::AEK_FCMA}), + AArch64::AEK_JSCVT, AArch64::AEK_FCMA, + AArch64::AEK_PERFMON}), "9.2-A"), ARMCPUTestParams( "cortex-a57", "armv8-a", "crypto-neon-fp-armv8", AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP, - AArch64::AEK_SIMD}), + AArch64::AEK_SIMD, AArch64::AEK_PERFMON}), "8-A"), ARMCPUTestParams( "cortex-a65", "armv8.2-a", "crypto-neon-fp-armv8", @@ -1168,7 +1171,8 @@ INSTANTIATE_TEST_SUITE_P( {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_DOTPROD, AArch64::AEK_FP, AArch64::AEK_FP16, AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RCPC, - AArch64::AEK_RDM, AArch64::AEK_SIMD, AArch64::AEK_SSBS}), + AArch64::AEK_RDM, AArch64::AEK_SIMD, AArch64::AEK_SSBS, + AArch64::AEK_PERFMON}), "8.2-A"), ARMCPUTestParams( "cortex-a65ae", "armv8.2-a", "crypto-neon-fp-armv8", @@ -1176,27 +1180,29 @@ INSTANTIATE_TEST_SUITE_P( {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_DOTPROD, AArch64::AEK_FP, AArch64::AEK_FP16, AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RCPC, - AArch64::AEK_RDM, AArch64::AEK_SIMD, AArch64::AEK_SSBS}), + AArch64::AEK_RDM, AArch64::AEK_SIMD, AArch64::AEK_SSBS, + AArch64::AEK_PERFMON}), "8.2-A"), ARMCPUTestParams( "cortex-a72", "armv8-a", "crypto-neon-fp-armv8", AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP, - AArch64::AEK_SIMD}), + AArch64::AEK_SIMD, AArch64::AEK_PERFMON}), "8-A"), ARMCPUTestParams( "cortex-a73", "armv8-a", "crypto-neon-fp-armv8", AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP, - AArch64::AEK_SIMD}), + AArch64::AEK_SIMD, AArch64::AEK_PERFMON}), "8-A"), ARMCPUTestParams( "cortex-a75", "armv8.2-a", "crypto-neon-fp-armv8", - AArch64::ExtensionBitset( - {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_FP, AArch64::AEK_SIMD, AArch64::AEK_RAS, - AArch64::AEK_LSE, AArch64::AEK_RDM, AArch64::AEK_FP16, - AArch64::AEK_DOTPROD, AArch64::AEK_RCPC}), + AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES, + AArch64::AEK_SHA2, AArch64::AEK_FP, + AArch64::AEK_SIMD, AArch64::AEK_RAS, + AArch64::AEK_LSE, AArch64::AEK_RDM, + AArch64::AEK_FP16, AArch64::AEK_DOTPROD, + AArch64::AEK_RCPC, AArch64::AEK_PERFMON}), "8.2-A"), ARMCPUTestParams( "cortex-a76", "armv8.2-a", "crypto-neon-fp-armv8", @@ -1204,7 +1210,8 @@ INSTANTIATE_TEST_SUITE_P( {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP, AArch64::AEK_RDM, AArch64::AEK_SIMD, AArch64::AEK_RAS, AArch64::AEK_LSE, AArch64::AEK_FP16, - AArch64::AEK_DOTPROD, AArch64::AEK_RCPC, AArch64::AEK_SSBS}), + AArch64::AEK_DOTPROD, AArch64::AEK_RCPC, AArch64::AEK_SSBS, + AArch64::AEK_PERFMON}), "8.2-A"), ARMCPUTestParams( "cortex-a76ae", "armv8.2-a", "crypto-neon-fp-armv8", @@ -1212,7 +1219,8 @@ INSTANTIATE_TEST_SUITE_P( {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP, AArch64::AEK_RDM, AArch64::AEK_SIMD, AArch64::AEK_RAS, AArch64::AEK_LSE, AArch64::AEK_FP16, - AArch64::AEK_DOTPROD, AArch64::AEK_RCPC, AArch64::AEK_SSBS}), + AArch64::AEK_DOTPROD, AArch64::AEK_RCPC, AArch64::AEK_SSBS, + AArch64::AEK_PERFMON}), "8.2-A"), ARMCPUTestParams( "cortex-a77", "armv8.2-a", "crypto-neon-fp-armv8", @@ -1220,7 +1228,8 @@ INSTANTIATE_TEST_SUITE_P( {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP, AArch64::AEK_RDM, AArch64::AEK_SIMD, AArch64::AEK_RAS, AArch64::AEK_LSE, AArch64::AEK_FP16, - AArch64::AEK_DOTPROD, AArch64::AEK_RCPC, AArch64::AEK_SSBS}), + AArch64::AEK_DOTPROD, AArch64::AEK_RCPC, AArch64::AEK_SSBS, + AArch64::AEK_PERFMON}), "8.2-A"), ARMCPUTestParams( "cortex-a78", "armv8.2-a", "crypto-neon-fp-armv8", @@ -1229,7 +1238,7 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_FP, AArch64::AEK_RDM, AArch64::AEK_SIMD, AArch64::AEK_RAS, AArch64::AEK_LSE, AArch64::AEK_FP16, AArch64::AEK_DOTPROD, AArch64::AEK_RCPC, AArch64::AEK_SSBS, - AArch64::AEK_PROFILE}), + AArch64::AEK_PROFILE, AArch64::AEK_PERFMON}), "8.2-A"), ARMCPUTestParams( "cortex-a78ae", "armv8.2-a", "crypto-neon-fp-armv8", @@ -1238,7 +1247,7 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_FP, AArch64::AEK_RDM, AArch64::AEK_SIMD, AArch64::AEK_RAS, AArch64::AEK_LSE, AArch64::AEK_FP16, AArch64::AEK_DOTPROD, AArch64::AEK_RCPC, AArch64::AEK_SSBS, - AArch64::AEK_PROFILE}), + AArch64::AEK_PROFILE, AArch64::AEK_PERFMON}), "8.2-A"), ARMCPUTestParams( "cortex-a78c", "armv8.2-a", "crypto-neon-fp-armv8", @@ -1248,7 +1257,7 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_RAS, AArch64::AEK_LSE, AArch64::AEK_RDM, AArch64::AEK_FP16, AArch64::AEK_DOTPROD, AArch64::AEK_RCPC, AArch64::AEK_SSBS, AArch64::AEK_PROFILE, AArch64::AEK_FLAGM, - AArch64::AEK_PAUTH}), + AArch64::AEK_PAUTH, AArch64::AEK_PERFMON}), "8.2-A"), ARMCPUTestParams( "cortex-a710", "armv9-a", "neon-fp-armv8", @@ -1263,7 +1272,7 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_PAUTH, AArch64::AEK_FLAGM, AArch64::AEK_SB, AArch64::AEK_I8MM, AArch64::AEK_BF16, AArch64::AEK_JSCVT, - AArch64::AEK_FCMA}), + AArch64::AEK_FCMA, AArch64::AEK_PERFMON}), "9-A"), ARMCPUTestParams( "cortex-a715", "armv9-a", "neon-fp-armv8", @@ -1280,7 +1289,7 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_PREDRES, AArch64::AEK_PROFILE, AArch64::AEK_FP16FML, AArch64::AEK_FP16, AArch64::AEK_FLAGM, AArch64::AEK_JSCVT, - AArch64::AEK_FCMA}), + AArch64::AEK_FCMA, AArch64::AEK_PERFMON}), "9-A"), ARMCPUTestParams( "cortex-a720", "armv9.2-a", "crypto-neon-fp-armv8", @@ -1297,7 +1306,7 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_SVE2BITPERM, AArch64::AEK_FLAGM, AArch64::AEK_PERFMON, AArch64::AEK_PREDRES, AArch64::AEK_PROFILE, AArch64::AEK_JSCVT, - AArch64::AEK_FCMA}), + AArch64::AEK_FCMA, AArch64::AEK_PERFMON}), "9.2-A"), ARMCPUTestParams( "cortex-a720ae", "armv9.2-a", "crypto-neon-fp-armv8", @@ -1314,20 +1323,24 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_SVE2BITPERM, AArch64::AEK_FLAGM, AArch64::AEK_PERFMON, AArch64::AEK_PREDRES, AArch64::AEK_PROFILE, AArch64::AEK_JSCVT, - AArch64::AEK_FCMA}), + AArch64::AEK_FCMA, AArch64::AEK_PERFMON}), "9.2-A"), ARMCPUTestParams( "neoverse-v1", "armv8.4-a", "crypto-neon-fp-armv8", AArch64::ExtensionBitset( - {AArch64::AEK_RAS, AArch64::AEK_SVE, AArch64::AEK_SSBS, - AArch64::AEK_RCPC, AArch64::AEK_CRC, AArch64::AEK_FP, - AArch64::AEK_SIMD, AArch64::AEK_RAS, AArch64::AEK_LSE, - AArch64::AEK_RDM, AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, - AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_SHA3, - AArch64::AEK_SM4, AArch64::AEK_FP16, AArch64::AEK_BF16, - AArch64::AEK_PROFILE, AArch64::AEK_RAND, AArch64::AEK_FP16FML, - AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, - AArch64::AEK_PAUTH}), + {AArch64::AEK_RAS, AArch64::AEK_SVE, + AArch64::AEK_SSBS, AArch64::AEK_RCPC, + AArch64::AEK_CRC, AArch64::AEK_FP, + AArch64::AEK_SIMD, AArch64::AEK_RAS, + AArch64::AEK_LSE, AArch64::AEK_RDM, + AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, + AArch64::AEK_AES, AArch64::AEK_SHA2, + AArch64::AEK_SHA3, AArch64::AEK_SM4, + AArch64::AEK_FP16, AArch64::AEK_BF16, + AArch64::AEK_PROFILE, AArch64::AEK_RAND, + AArch64::AEK_FP16FML, AArch64::AEK_I8MM, + AArch64::AEK_JSCVT, AArch64::AEK_FCMA, + AArch64::AEK_PAUTH, AArch64::AEK_PERFMON}), "8.4-A"), ARMCPUTestParams( "neoverse-v2", "armv9-a", "neon-fp-armv8", @@ -1343,7 +1356,7 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_FP16FML, AArch64::AEK_I8MM, AArch64::AEK_SVE2BITPERM, AArch64::AEK_RAND, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, - AArch64::AEK_PAUTH}), + AArch64::AEK_PAUTH, AArch64::AEK_PERFMON}), "9-A"), ARMCPUTestParams( "neoverse-v3", "armv9.2-a", "neon-fp-armv8", @@ -1362,7 +1375,7 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_PERFMON, AArch64::AEK_RAND, AArch64::AEK_SVE2BITPERM, AArch64::AEK_FP16FML, AArch64::AEK_PROFILE, AArch64::AEK_JSCVT, - AArch64::AEK_FCMA}), + AArch64::AEK_FCMA, AArch64::AEK_PERFMON}), "9.2-A"), ARMCPUTestParams( "neoverse-v3ae", "armv9.2-a", "neon-fp-armv8", @@ -1381,7 +1394,7 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_PERFMON, AArch64::AEK_RAND, AArch64::AEK_SVE2BITPERM, AArch64::AEK_FP16FML, AArch64::AEK_PROFILE, AArch64::AEK_JSCVT, - AArch64::AEK_FCMA}), + AArch64::AEK_FCMA, AArch64::AEK_PERFMON}), "9.2-A"), ARMCPUTestParams( "cortex-r82", "armv8-r", "crypto-neon-fp-armv8", @@ -1391,8 +1404,8 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_FP16, AArch64::AEK_FP16FML, AArch64::AEK_RAS, AArch64::AEK_RCPC, AArch64::AEK_LSE, AArch64::AEK_SB, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, AArch64::AEK_PAUTH, - AArch64::AEK_FLAGM, AArch64::AEK_PERFMON, - AArch64::AEK_PREDRES}), + AArch64::AEK_FLAGM, AArch64::AEK_PERFMON, AArch64::AEK_PREDRES, + AArch64::AEK_PERFMON}), "8-R"), ARMCPUTestParams( "cortex-r82ae", "armv8-r", "crypto-neon-fp-armv8", @@ -1402,8 +1415,8 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_FP16, AArch64::AEK_FP16FML, AArch64::AEK_RAS, AArch64::AEK_RCPC, AArch64::AEK_LSE, AArch64::AEK_SB, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, AArch64::AEK_PAUTH, - AArch64::AEK_FLAGM, AArch64::AEK_PERFMON, - AArch64::AEK_PREDRES}), + AArch64::AEK_FLAGM, AArch64::AEK_PERFMON, AArch64::AEK_PREDRES, + AArch64::AEK_PERFMON}), "8-R"), ARMCPUTestParams( "cortex-x1", "armv8.2-a", "crypto-neon-fp-armv8", @@ -1412,7 +1425,7 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_FP, AArch64::AEK_RDM, AArch64::AEK_SIMD, AArch64::AEK_RAS, AArch64::AEK_LSE, AArch64::AEK_FP16, AArch64::AEK_DOTPROD, AArch64::AEK_RCPC, AArch64::AEK_SSBS, - AArch64::AEK_PROFILE}), + AArch64::AEK_PROFILE, AArch64::AEK_PERFMON}), "8.2-A"), ARMCPUTestParams( "cortex-x1c", "armv8.2-a", "crypto-neon-fp-armv8", @@ -1421,7 +1434,8 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_FP, AArch64::AEK_RDM, AArch64::AEK_SIMD, AArch64::AEK_RAS, AArch64::AEK_LSE, AArch64::AEK_FP16, AArch64::AEK_DOTPROD, AArch64::AEK_RCPC, AArch64::AEK_SSBS, - AArch64::AEK_PAUTH, AArch64::AEK_PROFILE, AArch64::AEK_FLAGM}), + AArch64::AEK_PAUTH, AArch64::AEK_PROFILE, AArch64::AEK_FLAGM, + AArch64::AEK_PERFMON}), "8.2-A"), ARMCPUTestParams( "cortex-x2", "armv9-a", "neon-fp-armv8", @@ -1436,7 +1450,8 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_SVE2BITPERM, AArch64::AEK_SSBS, AArch64::AEK_SB, AArch64::AEK_FP16, AArch64::AEK_FP16FML, AArch64::AEK_FLAGM, - AArch64::AEK_JSCVT, AArch64::AEK_FCMA}), + AArch64::AEK_JSCVT, AArch64::AEK_FCMA, + AArch64::AEK_PERFMON}), "9-A"), ARMCPUTestParams( "cortex-x3", "armv9-a", "neon-fp-armv8", @@ -1453,7 +1468,7 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_FP16, AArch64::AEK_FP16FML, AArch64::AEK_PREDRES, AArch64::AEK_FLAGM, AArch64::AEK_SSBS, AArch64::AEK_JSCVT, - AArch64::AEK_FCMA}), + AArch64::AEK_FCMA, AArch64::AEK_PERFMON}), "9-A"), ARMCPUTestParams( "cortex-x4", "armv9.2-a", "crypto-neon-fp-armv8", @@ -1470,40 +1485,46 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_SVE2BITPERM, AArch64::AEK_FLAGM, AArch64::AEK_PERFMON, AArch64::AEK_PREDRES, AArch64::AEK_PROFILE, AArch64::AEK_JSCVT, - AArch64::AEK_FCMA}), + AArch64::AEK_FCMA, AArch64::AEK_PERFMON}), "9.2-A"), ARMCPUTestParams( "cyclone", "armv8-a", "crypto-neon-fp-armv8", AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_FP, AArch64::AEK_SIMD}), + AArch64::AEK_FP, AArch64::AEK_SIMD, + AArch64::AEK_PERFMON}), "8-A"), ARMCPUTestParams( "apple-a7", "armv8-a", "crypto-neon-fp-armv8", AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_FP, AArch64::AEK_SIMD}), + AArch64::AEK_FP, AArch64::AEK_SIMD, + AArch64::AEK_PERFMON}), "8-A"), ARMCPUTestParams( "apple-a8", "armv8-a", "crypto-neon-fp-armv8", AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_FP, AArch64::AEK_SIMD}), + AArch64::AEK_FP, AArch64::AEK_SIMD, + AArch64::AEK_PERFMON}), "8-A"), ARMCPUTestParams( "apple-a9", "armv8-a", "crypto-neon-fp-armv8", AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_FP, AArch64::AEK_SIMD}), + AArch64::AEK_FP, AArch64::AEK_SIMD, + AArch64::AEK_PERFMON}), "8-A"), ARMCPUTestParams( "apple-a10", "armv8-a", "crypto-neon-fp-armv8", AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP, - AArch64::AEK_RDM, AArch64::AEK_SIMD}), + AArch64::AEK_RDM, AArch64::AEK_SIMD, + AArch64::AEK_PERFMON}), "8-A"), ARMCPUTestParams( "apple-a11", "armv8.2-a", "crypto-neon-fp-armv8", - AArch64::ExtensionBitset( - {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_FP, AArch64::AEK_LSE, AArch64::AEK_RAS, - AArch64::AEK_RDM, AArch64::AEK_SIMD, AArch64::AEK_FP16}), + AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES, + AArch64::AEK_SHA2, AArch64::AEK_FP, + AArch64::AEK_LSE, AArch64::AEK_RAS, + AArch64::AEK_RDM, AArch64::AEK_SIMD, + AArch64::AEK_FP16, AArch64::AEK_PERFMON}), "8.2-A"), ARMCPUTestParams( "apple-a12", "armv8.3-a", "crypto-neon-fp-armv8", @@ -1512,7 +1533,7 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_FP, AArch64::AEK_SIMD, AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RDM, AArch64::AEK_RCPC, AArch64::AEK_FP16, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, - AArch64::AEK_PAUTH}), + AArch64::AEK_PAUTH, AArch64::AEK_PERFMON}), "8.3-A"), ARMCPUTestParams( "apple-a13", "armv8.4-a", "crypto-neon-fp-armv8", @@ -1522,82 +1543,92 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RDM, AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16, AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_JSCVT, - AArch64::AEK_FCMA, AArch64::AEK_PAUTH}), + AArch64::AEK_FCMA, AArch64::AEK_PAUTH, AArch64::AEK_PERFMON}), "8.4-A"), ARMCPUTestParams( "apple-a14", "armv8.5-a", "crypto-neon-fp-armv8", AArch64::ExtensionBitset( - {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_SHA3, AArch64::AEK_FP, AArch64::AEK_SIMD, - AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RDM, - AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16, - AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_JSCVT, - AArch64::AEK_FCMA, AArch64::AEK_PAUTH}), + {AArch64::AEK_CRC, AArch64::AEK_AES, + AArch64::AEK_SHA2, AArch64::AEK_SHA3, + AArch64::AEK_FP, AArch64::AEK_SIMD, + AArch64::AEK_LSE, AArch64::AEK_RAS, + AArch64::AEK_RDM, AArch64::AEK_RCPC, + AArch64::AEK_DOTPROD, AArch64::AEK_FP16, + AArch64::AEK_FP16FML, AArch64::AEK_SHA3, + AArch64::AEK_JSCVT, AArch64::AEK_FCMA, + AArch64::AEK_PAUTH, AArch64::AEK_PERFMON, + AArch64::AEK_PREDRES, AArch64::AEK_SB, + AArch64::AEK_SSBS}), "8.5-A"), ARMCPUTestParams( "apple-a15", "armv8.6-a", "crypto-neon-fp-armv8", AArch64::ExtensionBitset( - {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_SHA3, AArch64::AEK_FP, AArch64::AEK_SIMD, - AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RDM, - AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16, - AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_BF16, - AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, - AArch64::AEK_PAUTH}), + {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, + AArch64::AEK_SHA3, AArch64::AEK_FP, AArch64::AEK_SIMD, + AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RDM, + AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16, + AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_BF16, + AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, + AArch64::AEK_PAUTH, AArch64::AEK_PERFMON}), "8.6-A"), ARMCPUTestParams( "apple-a16", "armv8.6-a", "crypto-neon-fp-armv8", AArch64::ExtensionBitset( - {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_SHA3, AArch64::AEK_FP, AArch64::AEK_SIMD, - AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RDM, - AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16, - AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_BF16, - AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, - AArch64::AEK_PAUTH}), + {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, + AArch64::AEK_SHA3, AArch64::AEK_FP, AArch64::AEK_SIMD, + AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RDM, + AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16, + AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_BF16, + AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, + AArch64::AEK_PAUTH, AArch64::AEK_PERFMON}), "8.6-A"), ARMCPUTestParams( "apple-a17", "armv8.6-a", "crypto-neon-fp-armv8", AArch64::ExtensionBitset( - {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_SHA3, AArch64::AEK_FP, AArch64::AEK_SIMD, - AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RDM, - AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16, - AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_BF16, - AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, - AArch64::AEK_PAUTH}), + {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, + AArch64::AEK_SHA3, AArch64::AEK_FP, AArch64::AEK_SIMD, + AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RDM, + AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16, + AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_BF16, + AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, + AArch64::AEK_PAUTH, AArch64::AEK_PERFMON}), "8.6-A"), ARMCPUTestParams( "apple-m1", "armv8.5-a", "crypto-neon-fp-armv8", AArch64::ExtensionBitset( - {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_SHA3, AArch64::AEK_FP, AArch64::AEK_SIMD, - AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RDM, - AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16, - AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_JSCVT, - AArch64::AEK_FCMA, AArch64::AEK_PAUTH}), + {AArch64::AEK_CRC, AArch64::AEK_AES, + AArch64::AEK_SHA2, AArch64::AEK_SHA3, + AArch64::AEK_FP, AArch64::AEK_SIMD, + AArch64::AEK_LSE, AArch64::AEK_RAS, + AArch64::AEK_RDM, AArch64::AEK_RCPC, + AArch64::AEK_DOTPROD, AArch64::AEK_FP16, + AArch64::AEK_FP16FML, AArch64::AEK_SHA3, + AArch64::AEK_JSCVT, AArch64::AEK_FCMA, + AArch64::AEK_PAUTH, AArch64::AEK_PERFMON, + AArch64::AEK_PREDRES, AArch64::AEK_SB, + AArch64::AEK_SSBS}), "8.5-A"), ARMCPUTestParams( "apple-m2", "armv8.6-a", "crypto-neon-fp-armv8", AArch64::ExtensionBitset( - {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_SHA3, AArch64::AEK_FP, AArch64::AEK_SIMD, - AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RDM, - AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16, - AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_BF16, - AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, - AArch64::AEK_PAUTH}), + {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, + AArch64::AEK_SHA3, AArch64::AEK_FP, AArch64::AEK_SIMD, + AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RDM, + AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16, + AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_BF16, + AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, + AArch64::AEK_PAUTH, AArch64::AEK_PERFMON}), "8.6-A"), ARMCPUTestParams( "apple-m3", "armv8.6-a", "crypto-neon-fp-armv8", AArch64::ExtensionBitset( - {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_SHA3, AArch64::AEK_FP, AArch64::AEK_SIMD, - AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RDM, - AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16, - AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_BF16, - AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, - AArch64::AEK_PAUTH}), + {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, + AArch64::AEK_SHA3, AArch64::AEK_FP, AArch64::AEK_SIMD, + AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RDM, + AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16, + AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_BF16, + AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, + AArch64::AEK_PAUTH, AArch64::AEK_PERFMON}), "8.6-A"), ARMCPUTestParams( "apple-s4", "armv8.3-a", "crypto-neon-fp-armv8", @@ -1606,7 +1637,7 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_FP, AArch64::AEK_SIMD, AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RDM, AArch64::AEK_RCPC, AArch64::AEK_FP16, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, - AArch64::AEK_PAUTH}), + AArch64::AEK_PAUTH, AArch64::AEK_PERFMON}), "8.3-A"), ARMCPUTestParams( "apple-s5", "armv8.3-a", "crypto-neon-fp-armv8", @@ -1615,41 +1646,42 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_FP, AArch64::AEK_SIMD, AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RDM, AArch64::AEK_RCPC, AArch64::AEK_FP16, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, - AArch64::AEK_PAUTH}), + AArch64::AEK_PAUTH, AArch64::AEK_PERFMON}), "8.3-A"), ARMCPUTestParams( "exynos-m3", "armv8-a", "crypto-neon-fp-armv8", AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP, - AArch64::AEK_SIMD}), + AArch64::AEK_SIMD, AArch64::AEK_PERFMON}), "8-A"), ARMCPUTestParams( "exynos-m4", "armv8.2-a", "crypto-neon-fp-armv8", - AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES, - AArch64::AEK_SHA2, AArch64::AEK_DOTPROD, - AArch64::AEK_FP, AArch64::AEK_FP16, - AArch64::AEK_LSE, AArch64::AEK_RAS, - AArch64::AEK_RDM, AArch64::AEK_SIMD}), + AArch64::ExtensionBitset( + {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, + AArch64::AEK_DOTPROD, AArch64::AEK_FP, AArch64::AEK_FP16, + AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RDM, + AArch64::AEK_SIMD, AArch64::AEK_PERFMON}), "8.2-A"), ARMCPUTestParams( "exynos-m5", "armv8.2-a", "crypto-neon-fp-armv8", - AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES, - AArch64::AEK_SHA2, AArch64::AEK_DOTPROD, - AArch64::AEK_FP, AArch64::AEK_FP16, - AArch64::AEK_LSE, AArch64::AEK_RAS, - AArch64::AEK_RDM, AArch64::AEK_SIMD}), + AArch64::ExtensionBitset( + {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, + AArch64::AEK_DOTPROD, AArch64::AEK_FP, AArch64::AEK_FP16, + AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RDM, + AArch64::AEK_SIMD, AArch64::AEK_PERFMON}), "8.2-A"), ARMCPUTestParams( "falkor", "armv8-a", "crypto-neon-fp-armv8", AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP, - AArch64::AEK_SIMD, AArch64::AEK_RDM}), + AArch64::AEK_SIMD, AArch64::AEK_RDM, + AArch64::AEK_PERFMON}), "8-A"), ARMCPUTestParams( "kryo", "armv8-a", "crypto-neon-fp-armv8", AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP, - AArch64::AEK_SIMD}), + AArch64::AEK_SIMD, AArch64::AEK_PERFMON}), "8-A"), ARMCPUTestParams( "neoverse-e1", "armv8.2-a", "crypto-neon-fp-armv8", @@ -1657,7 +1689,8 @@ INSTANTIATE_TEST_SUITE_P( {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_DOTPROD, AArch64::AEK_FP, AArch64::AEK_FP16, AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RCPC, - AArch64::AEK_RDM, AArch64::AEK_SIMD, AArch64::AEK_SSBS}), + AArch64::AEK_RDM, AArch64::AEK_SIMD, AArch64::AEK_SSBS, + AArch64::AEK_PERFMON}), "8.2-A"), ARMCPUTestParams( "neoverse-n1", "armv8.2-a", "crypto-neon-fp-armv8", @@ -1666,7 +1699,7 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_DOTPROD, AArch64::AEK_FP, AArch64::AEK_FP16, AArch64::AEK_LSE, AArch64::AEK_PROFILE, AArch64::AEK_RAS, AArch64::AEK_RCPC, AArch64::AEK_RDM, AArch64::AEK_SIMD, - AArch64::AEK_SSBS}), + AArch64::AEK_SSBS, AArch64::AEK_PERFMON}), "8.2-A"), ARMCPUTestParams( "neoverse-n2", "armv9-a", "crypto-neon-fp-armv8", @@ -1681,7 +1714,7 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_SVE2BITPERM, AArch64::AEK_BF16, AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, AArch64::AEK_PAUTH, - AArch64::AEK_FP16FML}), + AArch64::AEK_FP16FML, AArch64::AEK_PERFMON}), "9-A"), ARMCPUTestParams( "neoverse-n3", "armv9.2-a", "neon-fp-armv8", @@ -1699,30 +1732,30 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_FLAGM, AArch64::AEK_PERFMON, AArch64::AEK_RAND, AArch64::AEK_SVE2BITPERM, AArch64::AEK_FP16FML, AArch64::AEK_PROFILE, - AArch64::AEK_JSCVT}), + AArch64::AEK_JSCVT, AArch64::AEK_PERFMON}), "9.2-A"), ARMCPUTestParams( "ampere1", "armv8.6-a", "crypto-neon-fp-armv8", AArch64::ExtensionBitset( - {AArch64::AEK_CRC, AArch64::AEK_FP, AArch64::AEK_FP16, - AArch64::AEK_SIMD, AArch64::AEK_RAS, AArch64::AEK_LSE, - AArch64::AEK_RDM, AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, - AArch64::AEK_SHA3, AArch64::AEK_BF16, AArch64::AEK_SHA2, - AArch64::AEK_AES, AArch64::AEK_I8MM, AArch64::AEK_SSBS, - AArch64::AEK_SB, AArch64::AEK_RAND, AArch64::AEK_JSCVT, - AArch64::AEK_FCMA, AArch64::AEK_PAUTH}), + {AArch64::AEK_CRC, AArch64::AEK_FP, AArch64::AEK_FP16, + AArch64::AEK_SIMD, AArch64::AEK_RAS, AArch64::AEK_LSE, + AArch64::AEK_RDM, AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, + AArch64::AEK_SHA3, AArch64::AEK_BF16, AArch64::AEK_SHA2, + AArch64::AEK_AES, AArch64::AEK_I8MM, AArch64::AEK_SSBS, + AArch64::AEK_SB, AArch64::AEK_RAND, AArch64::AEK_JSCVT, + AArch64::AEK_FCMA, AArch64::AEK_PAUTH, AArch64::AEK_PERFMON}), "8.6-A"), ARMCPUTestParams( "ampere1a", "armv8.6-a", "crypto-neon-fp-armv8", AArch64::ExtensionBitset( - {AArch64::AEK_CRC, AArch64::AEK_FP, AArch64::AEK_FP16, - AArch64::AEK_SIMD, AArch64::AEK_RAS, AArch64::AEK_LSE, - AArch64::AEK_RDM, AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, - AArch64::AEK_SM4, AArch64::AEK_SHA3, AArch64::AEK_BF16, - AArch64::AEK_SHA2, AArch64::AEK_AES, AArch64::AEK_I8MM, - AArch64::AEK_SSBS, AArch64::AEK_SB, AArch64::AEK_RAND, - AArch64::AEK_MTE, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, - AArch64::AEK_PAUTH}), + {AArch64::AEK_CRC, AArch64::AEK_FP, AArch64::AEK_FP16, + AArch64::AEK_SIMD, AArch64::AEK_RAS, AArch64::AEK_LSE, + AArch64::AEK_RDM, AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, + AArch64::AEK_SM4, AArch64::AEK_SHA3, AArch64::AEK_BF16, + AArch64::AEK_SHA2, AArch64::AEK_AES, AArch64::AEK_I8MM, + AArch64::AEK_SSBS, AArch64::AEK_SB, AArch64::AEK_RAND, + AArch64::AEK_MTE, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, + AArch64::AEK_PAUTH, AArch64::AEK_PERFMON}), "8.6-A"), ARMCPUTestParams( "ampere1b", "armv8.7-a", "crypto-neon-fp-armv8", @@ -1734,20 +1767,25 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_SHA2, AArch64::AEK_AES, AArch64::AEK_I8MM, AArch64::AEK_SSBS, AArch64::AEK_SB, AArch64::AEK_RAND, AArch64::AEK_MTE, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, - AArch64::AEK_PAUTH, AArch64::AEK_CSSC}), + AArch64::AEK_PAUTH, AArch64::AEK_CSSC, AArch64::AEK_PERFMON, + AArch64::AEK_WFXT}), "8.7-A"), ARMCPUTestParams( "neoverse-512tvb", "armv8.4-a", "crypto-neon-fp-armv8", AArch64::ExtensionBitset( - {AArch64::AEK_RAS, AArch64::AEK_SVE, AArch64::AEK_SSBS, - AArch64::AEK_RCPC, AArch64::AEK_CRC, AArch64::AEK_FP, - AArch64::AEK_SIMD, AArch64::AEK_RAS, AArch64::AEK_LSE, - AArch64::AEK_RDM, AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, - AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_SHA3, - AArch64::AEK_SM4, AArch64::AEK_FP16, AArch64::AEK_BF16, - AArch64::AEK_PROFILE, AArch64::AEK_RAND, AArch64::AEK_FP16FML, - AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, - AArch64::AEK_PAUTH}), + {AArch64::AEK_RAS, AArch64::AEK_SVE, + AArch64::AEK_SSBS, AArch64::AEK_RCPC, + AArch64::AEK_CRC, AArch64::AEK_FP, + AArch64::AEK_SIMD, AArch64::AEK_RAS, + AArch64::AEK_LSE, AArch64::AEK_RDM, + AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, + AArch64::AEK_AES, AArch64::AEK_SHA2, + AArch64::AEK_SHA3, AArch64::AEK_SM4, + AArch64::AEK_FP16, AArch64::AEK_BF16, + AArch64::AEK_PROFILE, AArch64::AEK_RAND, + AArch64::AEK_FP16FML, AArch64::AEK_I8MM, + AArch64::AEK_JSCVT, AArch64::AEK_FCMA, + AArch64::AEK_PAUTH, AArch64::AEK_PERFMON}), "8.4-A"), ARMCPUTestParams( "thunderx2t99", "armv8.1-a", "crypto-neon-fp-armv8", @@ -1762,31 +1800,32 @@ INSTANTIATE_TEST_SUITE_P( {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_LSE, AArch64::AEK_RDM, AArch64::AEK_FP, AArch64::AEK_SIMD, AArch64::AEK_RAS, AArch64::AEK_RCPC, - AArch64::AEK_JSCVT, AArch64::AEK_FCMA, AArch64::AEK_PAUTH}), + AArch64::AEK_JSCVT, AArch64::AEK_FCMA, AArch64::AEK_PAUTH, + AArch64::AEK_PERFMON}), "8.3-A"), ARMCPUTestParams( "thunderx", "armv8-a", "crypto-neon-fp-armv8", AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_SIMD, - AArch64::AEK_FP}), + AArch64::AEK_FP, AArch64::AEK_PERFMON}), "8-A"), ARMCPUTestParams( "thunderxt81", "armv8-a", "crypto-neon-fp-armv8", AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_SIMD, - AArch64::AEK_FP}), + AArch64::AEK_FP, AArch64::AEK_PERFMON}), "8-A"), ARMCPUTestParams( "thunderxt83", "armv8-a", "crypto-neon-fp-armv8", AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_SIMD, - AArch64::AEK_FP}), + AArch64::AEK_FP, AArch64::AEK_PERFMON}), "8-A"), ARMCPUTestParams( "thunderxt88", "armv8-a", "crypto-neon-fp-armv8", AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_SIMD, - AArch64::AEK_FP}), + AArch64::AEK_FP, AArch64::AEK_PERFMON}), "8-A"), ARMCPUTestParams( "tsv110", "armv8.2-a", "crypto-neon-fp-armv8", @@ -1795,15 +1834,16 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_FP, AArch64::AEK_SIMD, AArch64::AEK_RAS, AArch64::AEK_LSE, AArch64::AEK_RDM, AArch64::AEK_PROFILE, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, AArch64::AEK_FP16, - AArch64::AEK_FP16FML, AArch64::AEK_DOTPROD}), + AArch64::AEK_FP16FML, AArch64::AEK_DOTPROD, + AArch64::AEK_PERFMON}), "8.2-A"), ARMCPUTestParams( "a64fx", "armv8.2-a", "crypto-neon-fp-armv8", - AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES, - AArch64::AEK_SHA2, AArch64::AEK_FP, - AArch64::AEK_SIMD, AArch64::AEK_FP16, - AArch64::AEK_RAS, AArch64::AEK_LSE, - AArch64::AEK_SVE, AArch64::AEK_RDM}), + AArch64::ExtensionBitset( + {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, + AArch64::AEK_FP, AArch64::AEK_SIMD, AArch64::AEK_FP16, + AArch64::AEK_RAS, AArch64::AEK_LSE, AArch64::AEK_SVE, + AArch64::AEK_RDM, AArch64::AEK_PERFMON, AArch64::AEK_FCMA}), "8.2-A"), ARMCPUTestParams( "carmel", "armv8.2-a", "crypto-neon-fp-armv8", diff --git a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp index 8bf4e7ee0978f..39d8c16d82f44 100644 --- a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp +++ b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp @@ -158,7 +158,6 @@ static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream &OS) { // Construct the list of default extensions OS << " (AArch64::ExtensionBitset({"; for (auto *E : Rec->getValueAsListOfDefs("DefaultExts")) { - // Only process subclasses of Extension OS << "AArch64::" << E->getValueAsString("ArchExtKindSpelling").upper() << ", "; } @@ -196,9 +195,17 @@ static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream &OS) { << " \"" << Name << "\",\n" << " " << ArchInfo << ",\n" << " AArch64::ExtensionBitset({\n"; - for (auto E : Rec->getValueAsListOfDefs("DefaultExts")) - OS << " AArch64::" - << E->getValueAsString("ArchExtKindSpelling").upper() << ",\n"; + + // Keep track of extensions we have seen + StringSet<> SeenExts; + for (auto *E : Rec->getValueAsListOfDefs("Features")) + // Only process subclasses of Extension + if (E->isSubClassOf("Extension")) { + const auto AEK = E->getValueAsString("ArchExtKindSpelling").upper(); + if (!SeenExts.insert(AEK).second) + PrintError(Rec, "feature already added: " + E->getName()); + OS << " AArch64::" << AEK << ",\n"; + } OS << " })\n" << " },\n"; } From 727e71a292b68c848aa0fd321c11f507bcf5979b Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Fri, 17 May 2024 10:37:58 +0100 Subject: [PATCH 11/19] remove unnecessary AEK_PERFMON additions --- llvm/unittests/TargetParser/TargetParserTest.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp index baa08383b22b4..b0af53afffe18 100644 --- a/llvm/unittests/TargetParser/TargetParserTest.cpp +++ b/llvm/unittests/TargetParser/TargetParserTest.cpp @@ -1404,8 +1404,8 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_FP16, AArch64::AEK_FP16FML, AArch64::AEK_RAS, AArch64::AEK_RCPC, AArch64::AEK_LSE, AArch64::AEK_SB, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, AArch64::AEK_PAUTH, - AArch64::AEK_FLAGM, AArch64::AEK_PERFMON, AArch64::AEK_PREDRES, - AArch64::AEK_PERFMON}), + AArch64::AEK_FLAGM, AArch64::AEK_PERFMON, + AArch64::AEK_PREDRES}), "8-R"), ARMCPUTestParams( "cortex-r82ae", "armv8-r", "crypto-neon-fp-armv8", @@ -1415,8 +1415,8 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_FP16, AArch64::AEK_FP16FML, AArch64::AEK_RAS, AArch64::AEK_RCPC, AArch64::AEK_LSE, AArch64::AEK_SB, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, AArch64::AEK_PAUTH, - AArch64::AEK_FLAGM, AArch64::AEK_PERFMON, AArch64::AEK_PREDRES, - AArch64::AEK_PERFMON}), + AArch64::AEK_FLAGM, AArch64::AEK_PERFMON, + AArch64::AEK_PREDRES}), "8-R"), ARMCPUTestParams( "cortex-x1", "armv8.2-a", "crypto-neon-fp-armv8", From 75711655d75c79403d339604d919dccba2460559 Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Fri, 17 May 2024 16:07:23 +0100 Subject: [PATCH 12/19] Remove extra comment about apple-latest alias --- llvm/lib/Target/AArch64/AArch64Processors.td | 1 - 1 file changed, 1 deletion(-) diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td index 9da3fc10ff160..4e6ca7cb2503c 100644 --- a/llvm/lib/Target/AArch64/AArch64Processors.td +++ b/llvm/lib/Target/AArch64/AArch64Processors.td @@ -988,7 +988,6 @@ def : AArch64Processor<"apple-a14", HasV8_5aOps, CycloneModel, ProcessorFeatures [TuneAppleA14]>; def : AArch64Processor<"apple-a15", HasV8_6aOps, CycloneModel, ProcessorFeatures.AppleA15, [TuneAppleA15]>; -// Alias for the latest Apple processor model supported by LLVM. def : AArch64Processor<"apple-a16", HasV8_6aOps, CycloneModel, ProcessorFeatures.AppleA16, [TuneAppleA16]>; def : AArch64Processor<"apple-a17", HasV8_6aOps, CycloneModel, ProcessorFeatures.AppleA17, From 51701f25e30aea995a8a38127f0e80cb37e85f8d Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Fri, 17 May 2024 15:52:56 +0100 Subject: [PATCH 13/19] Remove AArch64Processor class The only thing this added over ProcModel was the Architecture field. Instead, search the list of Features to find the architecture for each processor. Since the "generic" processor does not have an Architecture, it needs special treatment in the emitter. --- llvm/lib/Target/AArch64/AArch64Processors.td | 161 +++++++++---------- llvm/utils/TableGen/ARMTargetDefEmitter.cpp | 39 ++++- 2 files changed, 110 insertions(+), 90 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td index 4e6ca7cb2503c..648fe4b6cc2e1 100644 --- a/llvm/lib/Target/AArch64/AArch64Processors.td +++ b/llvm/lib/Target/AArch64/AArch64Processors.td @@ -835,20 +835,9 @@ def ProcessorFeatures { list Generic = [FeatureFPARMv8, FeatureNEON, FeatureETE]; } -class AArch64Processor< - string n, - Architecture64 arch, - SchedMachineModel m, - list f, - list tunef -> : ProcessorModel { - // The base architecture for this processor. - Architecture64 Arch = arch; -} - // FeatureFuseAdrpAdd is enabled under Generic to allow linker merging // optimizations. -def : AArch64Processor<"generic", HasV8_0aOps, CortexA510Model, ProcessorFeatures.Generic, +def : ProcessorModel<"generic", CortexA510Model, ProcessorFeatures.Generic, [FeatureFuseAES, FeatureFuseAdrpAdd, FeaturePostRAScheduler, FeatureEnableSelectOptimize]>; @@ -856,170 +845,170 @@ def : AArch64Processor<"generic", HasV8_0aOps, CortexA510Model, ProcessorFeature def : ProcessorModel<"apple-latest", CycloneModel, ProcessorFeatures.AppleA16, [TuneAppleA16]>; -def : AArch64Processor<"cortex-a34", HasV8_0aOps, CortexA53Model, ProcessorFeatures.A53, +def : ProcessorModel<"cortex-a34", CortexA53Model, ProcessorFeatures.A53, [TuneA35]>; -def : AArch64Processor<"cortex-a35", HasV8_0aOps, CortexA53Model, ProcessorFeatures.A53, +def : ProcessorModel<"cortex-a35", CortexA53Model, ProcessorFeatures.A53, [TuneA35]>; -def : AArch64Processor<"cortex-a53", HasV8_0aOps, CortexA53Model, ProcessorFeatures.A53, +def : ProcessorModel<"cortex-a53", CortexA53Model, ProcessorFeatures.A53, [TuneA53]>; -def : AArch64Processor<"cortex-a55", HasV8_2aOps, CortexA55Model, ProcessorFeatures.A55, +def : ProcessorModel<"cortex-a55", CortexA55Model, ProcessorFeatures.A55, [TuneA55]>; -def : AArch64Processor<"cortex-a510", HasV9_0aOps, CortexA510Model, ProcessorFeatures.A510, +def : ProcessorModel<"cortex-a510", CortexA510Model, ProcessorFeatures.A510, [TuneA510]>; -def : AArch64Processor<"cortex-a520", HasV9_2aOps, CortexA510Model, ProcessorFeatures.A520, +def : ProcessorModel<"cortex-a520", CortexA510Model, ProcessorFeatures.A520, [TuneA520]>; -def : AArch64Processor<"cortex-a520ae", HasV9_2aOps, CortexA510Model, ProcessorFeatures.A520AE, +def : ProcessorModel<"cortex-a520ae", CortexA510Model, ProcessorFeatures.A520AE, [TuneA520AE]>; -def : AArch64Processor<"cortex-a57", HasV8_0aOps, CortexA57Model, ProcessorFeatures.A53, +def : ProcessorModel<"cortex-a57", CortexA57Model, ProcessorFeatures.A53, [TuneA57]>; -def : AArch64Processor<"cortex-a65", HasV8_2aOps, CortexA53Model, ProcessorFeatures.A65, +def : ProcessorModel<"cortex-a65", CortexA53Model, ProcessorFeatures.A65, [TuneA65]>; -def : AArch64Processor<"cortex-a65ae", HasV8_2aOps, CortexA53Model, ProcessorFeatures.A65, +def : ProcessorModel<"cortex-a65ae", CortexA53Model, ProcessorFeatures.A65, [TuneA65]>; -def : AArch64Processor<"cortex-a72", HasV8_0aOps, CortexA57Model, ProcessorFeatures.A53, +def : ProcessorModel<"cortex-a72", CortexA57Model, ProcessorFeatures.A53, [TuneA72]>; -def : AArch64Processor<"cortex-a73", HasV8_0aOps, CortexA57Model, ProcessorFeatures.A53, +def : ProcessorModel<"cortex-a73", CortexA57Model, ProcessorFeatures.A53, [TuneA73]>; -def : AArch64Processor<"cortex-a75", HasV8_2aOps, CortexA57Model, ProcessorFeatures.A55, +def : ProcessorModel<"cortex-a75", CortexA57Model, ProcessorFeatures.A55, [TuneA75]>; -def : AArch64Processor<"cortex-a76", HasV8_2aOps, CortexA57Model, ProcessorFeatures.A76, +def : ProcessorModel<"cortex-a76", CortexA57Model, ProcessorFeatures.A76, [TuneA76]>; -def : AArch64Processor<"cortex-a76ae", HasV8_2aOps, CortexA57Model, ProcessorFeatures.A76, +def : ProcessorModel<"cortex-a76ae", CortexA57Model, ProcessorFeatures.A76, [TuneA76]>; -def : AArch64Processor<"cortex-a77", HasV8_2aOps, CortexA57Model, ProcessorFeatures.A77, +def : ProcessorModel<"cortex-a77", CortexA57Model, ProcessorFeatures.A77, [TuneA77]>; -def : AArch64Processor<"cortex-a78", HasV8_2aOps, CortexA57Model, ProcessorFeatures.A78, +def : ProcessorModel<"cortex-a78", CortexA57Model, ProcessorFeatures.A78, [TuneA78]>; -def : AArch64Processor<"cortex-a78ae", HasV8_2aOps, CortexA57Model, ProcessorFeatures.A78AE, +def : ProcessorModel<"cortex-a78ae", CortexA57Model, ProcessorFeatures.A78AE, [TuneA78AE]>; -def : AArch64Processor<"cortex-a78c", HasV8_2aOps, CortexA57Model, ProcessorFeatures.A78C, +def : ProcessorModel<"cortex-a78c", CortexA57Model, ProcessorFeatures.A78C, [TuneA78C]>; -def : AArch64Processor<"cortex-a710", HasV9_0aOps, NeoverseN2Model, ProcessorFeatures.A710, +def : ProcessorModel<"cortex-a710", NeoverseN2Model, ProcessorFeatures.A710, [TuneA710]>; -def : AArch64Processor<"cortex-a715", HasV9_0aOps, NeoverseN2Model, ProcessorFeatures.A715, +def : ProcessorModel<"cortex-a715", NeoverseN2Model, ProcessorFeatures.A715, [TuneA715]>; -def : AArch64Processor<"cortex-a720", HasV9_2aOps, NeoverseN2Model, ProcessorFeatures.A720, +def : ProcessorModel<"cortex-a720", NeoverseN2Model, ProcessorFeatures.A720, [TuneA720]>; -def : AArch64Processor<"cortex-a720ae", HasV9_2aOps, NeoverseN2Model, ProcessorFeatures.A720AE, +def : ProcessorModel<"cortex-a720ae", NeoverseN2Model, ProcessorFeatures.A720AE, [TuneA720AE]>; -def : AArch64Processor<"cortex-r82", HasV8_0rOps, CortexA55Model, ProcessorFeatures.R82, +def : ProcessorModel<"cortex-r82", CortexA55Model, ProcessorFeatures.R82, [TuneR82]>; -def : AArch64Processor<"cortex-r82ae", HasV8_0rOps, CortexA55Model, ProcessorFeatures.R82AE, +def : ProcessorModel<"cortex-r82ae", CortexA55Model, ProcessorFeatures.R82AE, [TuneR82AE]>; -def : AArch64Processor<"cortex-x1", HasV8_2aOps, CortexA57Model, ProcessorFeatures.X1, +def : ProcessorModel<"cortex-x1", CortexA57Model, ProcessorFeatures.X1, [TuneX1]>; -def : AArch64Processor<"cortex-x1c", HasV8_2aOps, CortexA57Model, ProcessorFeatures.X1C, +def : ProcessorModel<"cortex-x1c", CortexA57Model, ProcessorFeatures.X1C, [TuneX1]>; -def : AArch64Processor<"cortex-x2", HasV9_0aOps, NeoverseN2Model, ProcessorFeatures.X2, +def : ProcessorModel<"cortex-x2", NeoverseN2Model, ProcessorFeatures.X2, [TuneX2]>; -def : AArch64Processor<"cortex-x3", HasV9_0aOps, NeoverseN2Model, ProcessorFeatures.X3, +def : ProcessorModel<"cortex-x3", NeoverseN2Model, ProcessorFeatures.X3, [TuneX3]>; -def : AArch64Processor<"cortex-x4", HasV9_2aOps, NeoverseN2Model, ProcessorFeatures.X4, +def : ProcessorModel<"cortex-x4", NeoverseN2Model, ProcessorFeatures.X4, [TuneX4]>; -def : AArch64Processor<"neoverse-e1", HasV8_2aOps, CortexA53Model, ProcessorFeatures.NeoverseE1, +def : ProcessorModel<"neoverse-e1", CortexA53Model, ProcessorFeatures.NeoverseE1, [TuneNeoverseE1]>; -def : AArch64Processor<"neoverse-n1", HasV8_2aOps, NeoverseN1Model, ProcessorFeatures.NeoverseN1, +def : ProcessorModel<"neoverse-n1", NeoverseN1Model, ProcessorFeatures.NeoverseN1, [TuneNeoverseN1]>; -def : AArch64Processor<"neoverse-n2", HasV9_0aOps, NeoverseN2Model, ProcessorFeatures.NeoverseN2, +def : ProcessorModel<"neoverse-n2", NeoverseN2Model, ProcessorFeatures.NeoverseN2, [TuneNeoverseN2]>; -def : AArch64Processor<"neoverse-n3", HasV9_2aOps, NeoverseN2Model, ProcessorFeatures.NeoverseN3, +def : ProcessorModel<"neoverse-n3", NeoverseN2Model, ProcessorFeatures.NeoverseN3, [TuneNeoverseN3]>; -def : AArch64Processor<"neoverse-512tvb", HasV8_4aOps, NeoverseV1Model, ProcessorFeatures.Neoverse512TVB, +def : ProcessorModel<"neoverse-512tvb", NeoverseV1Model, ProcessorFeatures.Neoverse512TVB, [TuneNeoverse512TVB]>; -def : AArch64Processor<"neoverse-v1", HasV8_4aOps, NeoverseV1Model, ProcessorFeatures.NeoverseV1, +def : ProcessorModel<"neoverse-v1", NeoverseV1Model, ProcessorFeatures.NeoverseV1, [TuneNeoverseV1]>; -def : AArch64Processor<"neoverse-v2", HasV9_0aOps, NeoverseV2Model, ProcessorFeatures.NeoverseV2, +def : ProcessorModel<"neoverse-v2", NeoverseV2Model, ProcessorFeatures.NeoverseV2, [TuneNeoverseV2]>; -def : AArch64Processor<"neoverse-v3", HasV9_2aOps, NeoverseV2Model, ProcessorFeatures.NeoverseV3, +def : ProcessorModel<"neoverse-v3", NeoverseV2Model, ProcessorFeatures.NeoverseV3, [TuneNeoverseV3]>; -def : AArch64Processor<"neoverse-v3ae", HasV9_2aOps, NeoverseV2Model, ProcessorFeatures.NeoverseV3AE, +def : ProcessorModel<"neoverse-v3ae", NeoverseV2Model, ProcessorFeatures.NeoverseV3AE, [TuneNeoverseV3AE]>; -def : AArch64Processor<"exynos-m3", HasV8_0aOps, ExynosM3Model, ProcessorFeatures.ExynosM3, +def : ProcessorModel<"exynos-m3", ExynosM3Model, ProcessorFeatures.ExynosM3, [TuneExynosM3]>; -def : AArch64Processor<"exynos-m4", HasV8_2aOps, ExynosM4Model, ProcessorFeatures.ExynosM4, +def : ProcessorModel<"exynos-m4", ExynosM4Model, ProcessorFeatures.ExynosM4, [TuneExynosM4]>; -def : AArch64Processor<"exynos-m5", HasV8_2aOps, ExynosM5Model, ProcessorFeatures.ExynosM4, +def : ProcessorModel<"exynos-m5", ExynosM5Model, ProcessorFeatures.ExynosM4, [TuneExynosM4]>; -def : AArch64Processor<"falkor", HasV8_0aOps, FalkorModel, ProcessorFeatures.Falkor, +def : ProcessorModel<"falkor", FalkorModel, ProcessorFeatures.Falkor, [TuneFalkor]>; -def : AArch64Processor<"saphira", HasV8_4aOps, FalkorModel, ProcessorFeatures.Saphira, +def : ProcessorModel<"saphira", FalkorModel, ProcessorFeatures.Saphira, [TuneSaphira]>; -def : AArch64Processor<"kryo", HasV8_0aOps, KryoModel, ProcessorFeatures.A53, +def : ProcessorModel<"kryo", KryoModel, ProcessorFeatures.A53, [TuneKryo]>; // Cavium ThunderX/ThunderX T8X Processors -def : AArch64Processor<"thunderx", HasV8_0aOps, ThunderXT8XModel, ProcessorFeatures.ThunderX, +def : ProcessorModel<"thunderx", ThunderXT8XModel, ProcessorFeatures.ThunderX, [TuneThunderX]>; -def : AArch64Processor<"thunderxt88", HasV8_0aOps, ThunderXT8XModel, ProcessorFeatures.ThunderX, +def : ProcessorModel<"thunderxt88", ThunderXT8XModel, ProcessorFeatures.ThunderX, [TuneThunderXT88]>; -def : AArch64Processor<"thunderxt81", HasV8_0aOps, ThunderXT8XModel, ProcessorFeatures.ThunderX, +def : ProcessorModel<"thunderxt81", ThunderXT8XModel, ProcessorFeatures.ThunderX, [TuneThunderXT81]>; -def : AArch64Processor<"thunderxt83", HasV8_0aOps, ThunderXT8XModel, ProcessorFeatures.ThunderX, +def : ProcessorModel<"thunderxt83", ThunderXT8XModel, ProcessorFeatures.ThunderX, [TuneThunderXT83]>; // Cavium ThunderX2T9X Processors. Formerly Broadcom Vulcan. -def : AArch64Processor<"thunderx2t99", HasV8_1aOps, ThunderX2T99Model, ProcessorFeatures.ThunderX2T99, +def : ProcessorModel<"thunderx2t99", ThunderX2T99Model, ProcessorFeatures.ThunderX2T99, [TuneThunderX2T99]>; // Marvell ThunderX3T110 Processors. -def : AArch64Processor<"thunderx3t110", HasV8_3aOps, ThunderX3T110Model, ProcessorFeatures.ThunderX3T110, +def : ProcessorModel<"thunderx3t110", ThunderX3T110Model, ProcessorFeatures.ThunderX3T110, [TuneThunderX3T110]>; -def : AArch64Processor<"tsv110", HasV8_2aOps, TSV110Model, ProcessorFeatures.TSV110, +def : ProcessorModel<"tsv110", TSV110Model, ProcessorFeatures.TSV110, [TuneTSV110]>; // Support cyclone as an alias for apple-a7 so we can still LTO old bitcode. -def : AArch64Processor<"cyclone", HasV8_0aOps, CycloneModel, ProcessorFeatures.AppleA7, +def : ProcessorModel<"cyclone", CycloneModel, ProcessorFeatures.AppleA7, [TuneAppleA7]>; // iPhone and iPad CPUs -def : AArch64Processor<"apple-a7", HasV8_0aOps, CycloneModel, ProcessorFeatures.AppleA7, +def : ProcessorModel<"apple-a7", CycloneModel, ProcessorFeatures.AppleA7, [TuneAppleA7]>; -def : AArch64Processor<"apple-a8", HasV8_0aOps, CycloneModel, ProcessorFeatures.AppleA7, +def : ProcessorModel<"apple-a8", CycloneModel, ProcessorFeatures.AppleA7, [TuneAppleA7]>; -def : AArch64Processor<"apple-a9", HasV8_0aOps, CycloneModel, ProcessorFeatures.AppleA7, +def : ProcessorModel<"apple-a9", CycloneModel, ProcessorFeatures.AppleA7, [TuneAppleA7]>; -def : AArch64Processor<"apple-a10", HasV8_0aOps, CycloneModel, ProcessorFeatures.AppleA10, +def : ProcessorModel<"apple-a10", CycloneModel, ProcessorFeatures.AppleA10, [TuneAppleA10]>; -def : AArch64Processor<"apple-a11", HasV8_2aOps, CycloneModel, ProcessorFeatures.AppleA11, +def : ProcessorModel<"apple-a11", CycloneModel, ProcessorFeatures.AppleA11, [TuneAppleA11]>; -def : AArch64Processor<"apple-a12", HasV8_3aOps, CycloneModel, ProcessorFeatures.AppleA12, +def : ProcessorModel<"apple-a12", CycloneModel, ProcessorFeatures.AppleA12, [TuneAppleA12]>; -def : AArch64Processor<"apple-a13", HasV8_4aOps, CycloneModel, ProcessorFeatures.AppleA13, +def : ProcessorModel<"apple-a13", CycloneModel, ProcessorFeatures.AppleA13, [TuneAppleA13]>; -def : AArch64Processor<"apple-a14", HasV8_5aOps, CycloneModel, ProcessorFeatures.AppleA14, +def : ProcessorModel<"apple-a14", CycloneModel, ProcessorFeatures.AppleA14, [TuneAppleA14]>; -def : AArch64Processor<"apple-a15", HasV8_6aOps, CycloneModel, ProcessorFeatures.AppleA15, +def : ProcessorModel<"apple-a15", CycloneModel, ProcessorFeatures.AppleA15, [TuneAppleA15]>; -def : AArch64Processor<"apple-a16", HasV8_6aOps, CycloneModel, ProcessorFeatures.AppleA16, +def : ProcessorModel<"apple-a16", CycloneModel, ProcessorFeatures.AppleA16, [TuneAppleA16]>; -def : AArch64Processor<"apple-a17", HasV8_6aOps, CycloneModel, ProcessorFeatures.AppleA17, +def : ProcessorModel<"apple-a17", CycloneModel, ProcessorFeatures.AppleA17, [TuneAppleA17]>; // Mac CPUs -def : AArch64Processor<"apple-m1", HasV8_5aOps, CycloneModel, ProcessorFeatures.AppleA14, +def : ProcessorModel<"apple-m1", CycloneModel, ProcessorFeatures.AppleA14, [TuneAppleA14]>; -def : AArch64Processor<"apple-m2", HasV8_6aOps, CycloneModel, ProcessorFeatures.AppleA15, +def : ProcessorModel<"apple-m2", CycloneModel, ProcessorFeatures.AppleA15, [TuneAppleA15]>; -def : AArch64Processor<"apple-m3", HasV8_6aOps, CycloneModel, ProcessorFeatures.AppleA16, +def : ProcessorModel<"apple-m3", CycloneModel, ProcessorFeatures.AppleA16, [TuneAppleA16]>; // watch CPUs. -def : AArch64Processor<"apple-s4", HasV8_3aOps, CycloneModel, ProcessorFeatures.AppleA12, +def : ProcessorModel<"apple-s4", CycloneModel, ProcessorFeatures.AppleA12, [TuneAppleA12]>; -def : AArch64Processor<"apple-s5", HasV8_3aOps, CycloneModel, ProcessorFeatures.AppleA12, +def : ProcessorModel<"apple-s5", CycloneModel, ProcessorFeatures.AppleA12, [TuneAppleA12]>; // Fujitsu A64FX -def : AArch64Processor<"a64fx", HasV8_2aOps, A64FXModel, ProcessorFeatures.A64FX, +def : ProcessorModel<"a64fx", A64FXModel, ProcessorFeatures.A64FX, [TuneA64FX]>; // Nvidia Carmel -def : AArch64Processor<"carmel", HasV8_2aOps, NoSchedModel, ProcessorFeatures.Carmel, +def : ProcessorModel<"carmel", NoSchedModel, ProcessorFeatures.Carmel, [TuneCarmel]>; // Ampere Computing -def : AArch64Processor<"ampere1", HasV8_6aOps, Ampere1Model, ProcessorFeatures.Ampere1, +def : ProcessorModel<"ampere1", Ampere1Model, ProcessorFeatures.Ampere1, [TuneAmpere1]>; -def : AArch64Processor<"ampere1a", HasV8_6aOps, Ampere1Model, ProcessorFeatures.Ampere1A, +def : ProcessorModel<"ampere1a", Ampere1Model, ProcessorFeatures.Ampere1A, [TuneAmpere1A]>; -def : AArch64Processor<"ampere1b", HasV8_7aOps, Ampere1BModel, ProcessorFeatures.Ampere1B, +def : ProcessorModel<"ampere1b", Ampere1BModel, ProcessorFeatures.Ampere1B, [TuneAmpere1B]>; diff --git a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp index c5468bd58de3f..3f4b960dda804 100644 --- a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp +++ b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp @@ -71,6 +71,10 @@ static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream &OS) { OS << "ARM_ARCHITECTURE(" << Arch << ")\n"; OS << "\n#undef ARM_ARCHITECTURE\n\n"; + // Currently only AArch64 (not ARM) is handled beyond this point. + if(!RK.getClass("Architecture64")) + return; + // Emit the ArchExtKind enum OS << "#ifdef EMIT_ARCHEXTKIND_ENUM\n" << "enum ArchExtKind : unsigned {\n" @@ -186,15 +190,42 @@ static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream &OS) { OS << "#ifdef EMIT_CPU_INFO\n" << "inline constexpr CpuInfo CpuInfos[] = {\n"; - for (const Record *Rec : - RK.getAllDerivedDefinitionsIfDefined("AArch64Processor")) { + for (const Record *Rec : RK.getAllDerivedDefinitions("ProcessorModel")) { auto Name = Rec->getValueAsString("Name"); - auto Arch = Rec->getValueAsDef("Arch"); + auto Features = Rec->getValueAsListOfDefs("Features"); + + // "apple-latest" is backend-only, should not be accepted by TargetParser. + if (Name == "apple-latest") + continue; + + Record *Arch; + if (Name == "generic") { + // "generic" is an exception. It does not have an architecture, and there + // are tests that depend on e.g. -mattr=-v8.4a meaning HasV8_0aOps==false. + // However, in TargetParser CPUInfo, it is written as 8.0-A. + Arch = RK.getDef("HasV8_0aOps"); + } else { + // Search for an Architecture64 in the list of features. + auto IsArch = [](Record *F) { return F->isSubClassOf("Architecture64"); }; + auto ArchIter = llvm::find_if(Features, IsArch); + if (ArchIter == Features.end()) + PrintFatalError(Rec, "Features must include an Architecture64."); + Arch = *ArchIter; + + // Check there is only one Architecture in the list. + if (llvm::count_if(Features, IsArch) > 1) + PrintFatalError(Rec, "Features has multiple Architecture64 entries"); + } + auto Major = Arch->getValueAsInt("Major"); auto Minor = Arch->getValueAsInt("Minor"); auto Profile = Arch->getValueAsString("Profile"); auto ArchInfo = ArchInfoName(Major, Minor, Profile); + // The apple-latest alias is backend only, do not expose it to -mcpu. + if (Name == "apple-latest") + continue; + OS << " {\n" << " \"" << Name << "\",\n" << " " << ArchInfo << ",\n" @@ -207,7 +238,7 @@ static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream &OS) { if (E->isSubClassOf("Extension")) { const auto AEK = E->getValueAsString("ArchExtKindSpelling").upper(); if (!SeenExts.insert(AEK).second) - PrintError(Rec, "feature already added: " + E->getName()); + PrintFatalError(Rec, "feature already added: " + E->getName()); OS << " AArch64::" << AEK << ",\n"; } OS << " })\n" From cb67ec964557cbe8ada61f3502771ba378f257f2 Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Fri, 17 May 2024 18:06:27 +0100 Subject: [PATCH 14/19] clang-format --- llvm/utils/TableGen/ARMTargetDefEmitter.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp index 3f4b960dda804..2eca57a796e2d 100644 --- a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp +++ b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp @@ -72,7 +72,7 @@ static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream &OS) { OS << "\n#undef ARM_ARCHITECTURE\n\n"; // Currently only AArch64 (not ARM) is handled beyond this point. - if(!RK.getClass("Architecture64")) + if (!RK.getClass("Architecture64")) return; // Emit the ArchExtKind enum From d087433c945cd01f45550f6d9d2be64e3f750940 Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Mon, 20 May 2024 18:19:58 +0100 Subject: [PATCH 15/19] remove whitespace only changes --- llvm/lib/Target/AArch64/AArch64Processors.td | 72 ++++++++++---------- 1 file changed, 35 insertions(+), 37 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td index 648fe4b6cc2e1..2cfffebdb24f1 100644 --- a/llvm/lib/Target/AArch64/AArch64Processors.td +++ b/llvm/lib/Target/AArch64/AArch64Processors.td @@ -840,15 +840,10 @@ def ProcessorFeatures { def : ProcessorModel<"generic", CortexA510Model, ProcessorFeatures.Generic, [FeatureFuseAES, FeatureFuseAdrpAdd, FeaturePostRAScheduler, FeatureEnableSelectOptimize]>; - -// Alias for the latest Apple processor model supported by LLVM. -def : ProcessorModel<"apple-latest", CycloneModel, ProcessorFeatures.AppleA16, - [TuneAppleA16]>; - -def : ProcessorModel<"cortex-a34", CortexA53Model, ProcessorFeatures.A53, - [TuneA35]>; def : ProcessorModel<"cortex-a35", CortexA53Model, ProcessorFeatures.A53, [TuneA35]>; +def : ProcessorModel<"cortex-a34", CortexA53Model, ProcessorFeatures.A53, + [TuneA35]>; def : ProcessorModel<"cortex-a53", CortexA53Model, ProcessorFeatures.A53, [TuneA53]>; def : ProcessorModel<"cortex-a55", CortexA55Model, ProcessorFeatures.A55, @@ -905,24 +900,24 @@ def : ProcessorModel<"cortex-x3", NeoverseN2Model, ProcessorFeatures.X3, [TuneX3]>; def : ProcessorModel<"cortex-x4", NeoverseN2Model, ProcessorFeatures.X4, [TuneX4]>; -def : ProcessorModel<"neoverse-e1", CortexA53Model, ProcessorFeatures.NeoverseE1, - [TuneNeoverseE1]>; -def : ProcessorModel<"neoverse-n1", NeoverseN1Model, ProcessorFeatures.NeoverseN1, - [TuneNeoverseN1]>; -def : ProcessorModel<"neoverse-n2", NeoverseN2Model, ProcessorFeatures.NeoverseN2, - [TuneNeoverseN2]>; -def : ProcessorModel<"neoverse-n3", NeoverseN2Model, ProcessorFeatures.NeoverseN3, - [TuneNeoverseN3]>; -def : ProcessorModel<"neoverse-512tvb", NeoverseV1Model, ProcessorFeatures.Neoverse512TVB, - [TuneNeoverse512TVB]>; -def : ProcessorModel<"neoverse-v1", NeoverseV1Model, ProcessorFeatures.NeoverseV1, - [TuneNeoverseV1]>; -def : ProcessorModel<"neoverse-v2", NeoverseV2Model, ProcessorFeatures.NeoverseV2, - [TuneNeoverseV2]>; -def : ProcessorModel<"neoverse-v3", NeoverseV2Model, ProcessorFeatures.NeoverseV3, - [TuneNeoverseV3]>; -def : ProcessorModel<"neoverse-v3ae", NeoverseV2Model, ProcessorFeatures.NeoverseV3AE, - [TuneNeoverseV3AE]>; +def : ProcessorModel<"neoverse-e1", CortexA53Model, + ProcessorFeatures.NeoverseE1, [TuneNeoverseE1]>; +def : ProcessorModel<"neoverse-n1", NeoverseN1Model, + ProcessorFeatures.NeoverseN1, [TuneNeoverseN1]>; +def : ProcessorModel<"neoverse-n2", NeoverseN2Model, + ProcessorFeatures.NeoverseN2, [TuneNeoverseN2]>; +def : ProcessorModel<"neoverse-n3", NeoverseN2Model, + ProcessorFeatures.NeoverseN3, [TuneNeoverseN3]>; +def : ProcessorModel<"neoverse-512tvb", NeoverseV1Model, + ProcessorFeatures.Neoverse512TVB, [TuneNeoverse512TVB]>; +def : ProcessorModel<"neoverse-v1", NeoverseV1Model, + ProcessorFeatures.NeoverseV1, [TuneNeoverseV1]>; +def : ProcessorModel<"neoverse-v2", NeoverseV2Model, + ProcessorFeatures.NeoverseV2, [TuneNeoverseV2]>; +def : ProcessorModel<"neoverse-v3", NeoverseV2Model, + ProcessorFeatures.NeoverseV3, [TuneNeoverseV3]>; +def : ProcessorModel<"neoverse-v3ae", NeoverseV2Model, + ProcessorFeatures.NeoverseV3AE, [TuneNeoverseV3AE]>; def : ProcessorModel<"exynos-m3", ExynosM3Model, ProcessorFeatures.ExynosM3, [TuneExynosM3]>; def : ProcessorModel<"exynos-m4", ExynosM4Model, ProcessorFeatures.ExynosM4, @@ -933,24 +928,23 @@ def : ProcessorModel<"falkor", FalkorModel, ProcessorFeatures.Falkor, [TuneFalkor]>; def : ProcessorModel<"saphira", FalkorModel, ProcessorFeatures.Saphira, [TuneSaphira]>; -def : ProcessorModel<"kryo", KryoModel, ProcessorFeatures.A53, - [TuneKryo]>; +def : ProcessorModel<"kryo", KryoModel, ProcessorFeatures.A53, [TuneKryo]>; // Cavium ThunderX/ThunderX T8X Processors def : ProcessorModel<"thunderx", ThunderXT8XModel, ProcessorFeatures.ThunderX, [TuneThunderX]>; -def : ProcessorModel<"thunderxt88", ThunderXT8XModel, ProcessorFeatures.ThunderX, - [TuneThunderXT88]>; -def : ProcessorModel<"thunderxt81", ThunderXT8XModel, ProcessorFeatures.ThunderX, - [TuneThunderXT81]>; -def : ProcessorModel<"thunderxt83", ThunderXT8XModel, ProcessorFeatures.ThunderX, - [TuneThunderXT83]>; +def : ProcessorModel<"thunderxt88", ThunderXT8XModel, + ProcessorFeatures.ThunderX, [TuneThunderXT88]>; +def : ProcessorModel<"thunderxt81", ThunderXT8XModel, + ProcessorFeatures.ThunderX, [TuneThunderXT81]>; +def : ProcessorModel<"thunderxt83", ThunderXT8XModel, + ProcessorFeatures.ThunderX, [TuneThunderXT83]>; // Cavium ThunderX2T9X Processors. Formerly Broadcom Vulcan. -def : ProcessorModel<"thunderx2t99", ThunderX2T99Model, ProcessorFeatures.ThunderX2T99, - [TuneThunderX2T99]>; +def : ProcessorModel<"thunderx2t99", ThunderX2T99Model, + ProcessorFeatures.ThunderX2T99, [TuneThunderX2T99]>; // Marvell ThunderX3T110 Processors. -def : ProcessorModel<"thunderx3t110", ThunderX3T110Model, ProcessorFeatures.ThunderX3T110, - [TuneThunderX3T110]>; +def : ProcessorModel<"thunderx3t110", ThunderX3T110Model, + ProcessorFeatures.ThunderX3T110, [TuneThunderX3T110]>; def : ProcessorModel<"tsv110", TSV110Model, ProcessorFeatures.TSV110, [TuneTSV110]>; @@ -995,6 +989,10 @@ def : ProcessorModel<"apple-s4", CycloneModel, ProcessorFeatures.AppleA12, def : ProcessorModel<"apple-s5", CycloneModel, ProcessorFeatures.AppleA12, [TuneAppleA12]>; +// Alias for the latest Apple processor model supported by LLVM. +def : ProcessorModel<"apple-latest", CycloneModel, ProcessorFeatures.AppleA16, + [TuneAppleA16]>; + // Fujitsu A64FX def : ProcessorModel<"a64fx", A64FXModel, ProcessorFeatures.A64FX, [TuneA64FX]>; From c293325437bab9c046bcba0251e3567f35530f9c Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Wed, 12 Jun 2024 16:18:35 +0100 Subject: [PATCH 16/19] fix clang/test/Misc/target-invalid-cpu-note.c --- clang/test/Misc/target-invalid-cpu-note.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c index 656b3bfa40c2f..e0a678f3129cf 100644 --- a/clang/test/Misc/target-invalid-cpu-note.c +++ b/clang/test/Misc/target-invalid-cpu-note.c @@ -5,11 +5,11 @@ // RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix AARCH64 // AARCH64: error: unknown target CPU 'not-a-cpu' -// AARCH64-NEXT: note: valid target CPU values are: generic, cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-r82ae, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, neoverse-v3, neoverse-v3ae, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx, thunderxt88, thunderxt81, thunderxt83, thunderx2t99, thunderx3t110, tsv110, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, a64fx, carmel, ampere1, ampere1a, ampere1b, oryon-1, cobalt-100, grace{{$}} +// AARCH64-NEXT: note: valid target CPU values are: generic, cortex-a35, cortex-a34, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-r82ae, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, neoverse-v3, neoverse-v3ae, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx, thunderxt88, thunderxt81, thunderxt83, thunderx2t99, thunderx3t110, tsv110, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, a64fx, carmel, ampere1, ampere1a, ampere1b, oryon-1, cobalt-100, grace{{$}} // RUN: not %clang_cc1 -triple arm64--- -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE_AARCH64 // TUNE_AARCH64: error: unknown target CPU 'not-a-cpu' -// TUNE_AARCH64-NEXT: note: valid target CPU values are: generic, cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-r82ae, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, neoverse-v3, neoverse-v3ae, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx, thunderxt88, thunderxt81, thunderxt83, thunderx2t99, thunderx3t110, tsv110, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, a64fx, carmel, ampere1, ampere1a, ampere1b, oryon-1, cobalt-100, grace{{$}} +// TUNE_AARCH64-NEXT: note: valid target CPU values are: generic, cortex-a35, cortex-a34, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-r82ae, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, neoverse-v3, neoverse-v3ae, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx, thunderxt88, thunderxt81, thunderxt83, thunderx2t99, thunderx3t110, tsv110, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, a64fx, carmel, ampere1, ampere1a, ampere1b, oryon-1, cobalt-100, grace{{$}} // RUN: not %clang_cc1 -triple i386--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix X86 // X86: error: unknown target CPU 'not-a-cpu' From ee97551ccb7c10a61d76fa01cdab79f3ed2e07d4 Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Mon, 17 Jun 2024 16:57:50 +0100 Subject: [PATCH 17/19] Move commit --- llvm/lib/Target/AArch64/AArch64Processors.td | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td index 0fdebd2e3a88f..af2244456b29a 100644 --- a/llvm/lib/Target/AArch64/AArch64Processors.td +++ b/llvm/lib/Target/AArch64/AArch64Processors.td @@ -817,8 +817,9 @@ def ProcessorFeatures { FeatureNEON, FeaturePerfMon, FeatureSHA3, FeatureFullFP16, FeatureFP16FML, FeatureHCX]; - // Technically apple-m4 is ARMv9.2. See the corresponding comment in - // AArch64TargetParser.h. + // Technically apple-m4 is ARMv9.2a, but a quirk of LLVM defines v9.0 as + // requiring SVE, which is optional according to the Arm ARM and not + // supported by the core. ARMv8.7a is the next closest choice. list AppleM4 = [HasV8_7aOps, FeatureSHA2, FeatureFPARMv8, FeatureNEON, FeaturePerfMon, FeatureSHA3, FeatureFullFP16, FeatureFP16FML, From 13326807a1ecbb33b53346b919d08aa12ebf9d8c Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Mon, 17 Jun 2024 16:58:22 +0100 Subject: [PATCH 18/19] Fix TargetParserTest --- llvm/lib/Target/AArch64/AArch64Processors.td | 2 +- .../TargetParser/TargetParserTest.cpp | 80 +++++++------------ 2 files changed, 29 insertions(+), 53 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td index af2244456b29a..e32ca629721ff 100644 --- a/llvm/lib/Target/AArch64/AArch64Processors.td +++ b/llvm/lib/Target/AArch64/AArch64Processors.td @@ -824,7 +824,7 @@ def ProcessorFeatures { FeatureNEON, FeaturePerfMon, FeatureSHA3, FeatureFullFP16, FeatureFP16FML, FeatureAES, FeatureBF16, - FeatureSME2, + FeatureSME, FeatureSME2, FeatureSMEF64F64, FeatureSMEI16I64]; list ExynosM3 = [HasV8_0aOps, FeatureCRC, FeatureSHA2, FeatureAES, FeaturePerfMon]; diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp index 3ff144776808d..93d5d32d9132a 100644 --- a/llvm/unittests/TargetParser/TargetParserTest.cpp +++ b/llvm/unittests/TargetParser/TargetParserTest.cpp @@ -1578,15 +1578,6 @@ INSTANTIATE_TEST_SUITE_P( "8.3-A"), ARMCPUTestParams( "apple-s4", "armv8.3-a", "crypto-neon-fp-armv8", - AArch64::ExtensionBitset( - {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_FP, AArch64::AEK_SIMD, AArch64::AEK_LSE, - AArch64::AEK_RAS, AArch64::AEK_RDM, AArch64::AEK_RCPC, - AArch64::AEK_FP16, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, - AArch64::AEK_PAUTH}), - "8.3-A"), - ARMCPUTestParams( - "apple-s5", "armv8.3-a", "crypto-neon-fp-armv8", AArch64::ExtensionBitset( {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP, AArch64::AEK_SIMD, AArch64::AEK_LSE, @@ -1594,15 +1585,6 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_FP16, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, AArch64::AEK_PAUTH, AArch64::AEK_PERFMON}), "8.3-A"), - ARMCPUTestParams( - "apple-s4", "armv8.3-a", "crypto-neon-fp-armv8", - AArch64::ExtensionBitset( - {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_FP, AArch64::AEK_SIMD, AArch64::AEK_LSE, - AArch64::AEK_RAS, AArch64::AEK_RDM, AArch64::AEK_RCPC, - AArch64::AEK_FP16, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, - AArch64::AEK_PAUTH}), - "8.3-A"), ARMCPUTestParams( "apple-s5", "armv8.3-a", "crypto-neon-fp-armv8", AArch64::ExtensionBitset( @@ -1610,7 +1592,7 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_FP, AArch64::AEK_SIMD, AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RDM, AArch64::AEK_RCPC, AArch64::AEK_FP16, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, - AArch64::AEK_PAUTH}), + AArch64::AEK_PAUTH, AArch64::AEK_PERFMON}), "8.3-A"), ARMCPUTestParams( "apple-a13", "armv8.4-a", "crypto-neon-fp-armv8", @@ -1640,13 +1622,13 @@ INSTANTIATE_TEST_SUITE_P( ARMCPUTestParams( "apple-m1", "armv8.4-a", "crypto-neon-fp-armv8", AArch64::ExtensionBitset( - {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_SHA3, AArch64::AEK_FP, AArch64::AEK_SIMD, - AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RDM, - AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16, - AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_BF16, - AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, - AArch64::AEK_PAUTH, AArch64::AEK_PERFMON}), + {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, + AArch64::AEK_SHA3, AArch64::AEK_FP, AArch64::AEK_SIMD, + AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RDM, + AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16, + AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_JSCVT, + AArch64::AEK_FCMA, AArch64::AEK_PAUTH, AArch64::AEK_PERFMON, + AArch64::AEK_PREDRES, AArch64::AEK_SB, AArch64::AEK_SSBS}), "8.6-A"), ARMCPUTestParams( "apple-a15", "armv8.6-a", "crypto-neon-fp-armv8", @@ -1673,17 +1655,13 @@ INSTANTIATE_TEST_SUITE_P( ARMCPUTestParams( "apple-a16", "armv8.6-a", "crypto-neon-fp-armv8", AArch64::ExtensionBitset( - {AArch64::AEK_CRC, AArch64::AEK_AES, - AArch64::AEK_SHA2, AArch64::AEK_SHA3, - AArch64::AEK_FP, AArch64::AEK_SIMD, - AArch64::AEK_LSE, AArch64::AEK_RAS, - AArch64::AEK_RDM, AArch64::AEK_RCPC, - AArch64::AEK_DOTPROD, AArch64::AEK_FP16, - AArch64::AEK_FP16FML, AArch64::AEK_SHA3, - AArch64::AEK_JSCVT, AArch64::AEK_FCMA, - AArch64::AEK_PAUTH, AArch64::AEK_PERFMON, - AArch64::AEK_PREDRES, AArch64::AEK_SB, - AArch64::AEK_SSBS}), + {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, + AArch64::AEK_SHA3, AArch64::AEK_FP, AArch64::AEK_SIMD, + AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RDM, + AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16, + AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_BF16, + AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, + AArch64::AEK_PAUTH, AArch64::AEK_PERFMON}), "8.4-A"), ARMCPUTestParams( "apple-m3", "armv8.6-a", "crypto-neon-fp-armv8", @@ -1710,20 +1688,18 @@ INSTANTIATE_TEST_SUITE_P( ARMCPUTestParams( "apple-m4", "armv8.7-a", "crypto-neon-fp-armv8", AArch64::ExtensionBitset( - {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_FP, AArch64::AEK_SIMD, AArch64::AEK_LSE, - AArch64::AEK_RAS, AArch64::AEK_RDM, AArch64::AEK_RCPC, - AArch64::AEK_FP16, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, - AArch64::AEK_PAUTH, AArch64::AEK_PERFMON}), - "8.3-A"), - ARMCPUTestParams( - "apple-s5", "armv8.3-a", "crypto-neon-fp-armv8", - AArch64::ExtensionBitset( - {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_FP, AArch64::AEK_SIMD, AArch64::AEK_LSE, - AArch64::AEK_RAS, AArch64::AEK_RDM, AArch64::AEK_RCPC, - AArch64::AEK_FP16, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, - AArch64::AEK_PAUTH, AArch64::AEK_PERFMON}), + {AArch64::AEK_CRC, AArch64::AEK_AES, + AArch64::AEK_SHA2, AArch64::AEK_SHA3, + AArch64::AEK_FP, AArch64::AEK_SIMD, + AArch64::AEK_LSE, AArch64::AEK_RAS, + AArch64::AEK_RDM, AArch64::AEK_RCPC, + AArch64::AEK_DOTPROD, AArch64::AEK_FP16, + AArch64::AEK_FP16FML, AArch64::AEK_BF16, + AArch64::AEK_I8MM, AArch64::AEK_JSCVT, + AArch64::AEK_FCMA, AArch64::AEK_PAUTH, + AArch64::AEK_SME, AArch64::AEK_SME2, + AArch64::AEK_SMEF64F64, AArch64::AEK_SMEI16I64, + AArch64::AEK_PERFMON}), "8.3-A"), ARMCPUTestParams( "exynos-m3", "armv8-a", "crypto-neon-fp-armv8", @@ -1944,7 +1920,7 @@ INSTANTIATE_TEST_SUITE_P( ARMCPUTestParams::PrintToStringParamName); // Note: number of CPUs includes aliases. -static constexpr unsigned NumAArch64CPUArchs = 80; +static constexpr unsigned NumAArch64CPUArchs = 81; TEST(TargetParserTest, testAArch64CPUArchList) { SmallVector List; From 1acb3179f58a0ee5f720b9137e8fe9202be66f4b Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Mon, 17 Jun 2024 17:07:58 +0100 Subject: [PATCH 19/19] clang-format --- .../TargetParser/TargetParserTest.cpp | 30 +++++++++++-------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp index 93d5d32d9132a..a99ef85fbfc81 100644 --- a/llvm/unittests/TargetParser/TargetParserTest.cpp +++ b/llvm/unittests/TargetParser/TargetParserTest.cpp @@ -1622,13 +1622,17 @@ INSTANTIATE_TEST_SUITE_P( ARMCPUTestParams( "apple-m1", "armv8.4-a", "crypto-neon-fp-armv8", AArch64::ExtensionBitset( - {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_SHA3, AArch64::AEK_FP, AArch64::AEK_SIMD, - AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RDM, - AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16, - AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_JSCVT, - AArch64::AEK_FCMA, AArch64::AEK_PAUTH, AArch64::AEK_PERFMON, - AArch64::AEK_PREDRES, AArch64::AEK_SB, AArch64::AEK_SSBS}), + {AArch64::AEK_CRC, AArch64::AEK_AES, + AArch64::AEK_SHA2, AArch64::AEK_SHA3, + AArch64::AEK_FP, AArch64::AEK_SIMD, + AArch64::AEK_LSE, AArch64::AEK_RAS, + AArch64::AEK_RDM, AArch64::AEK_RCPC, + AArch64::AEK_DOTPROD, AArch64::AEK_FP16, + AArch64::AEK_FP16FML, AArch64::AEK_SHA3, + AArch64::AEK_JSCVT, AArch64::AEK_FCMA, + AArch64::AEK_PAUTH, AArch64::AEK_PERFMON, + AArch64::AEK_PREDRES, AArch64::AEK_SB, + AArch64::AEK_SSBS}), "8.6-A"), ARMCPUTestParams( "apple-a15", "armv8.6-a", "crypto-neon-fp-armv8", @@ -1655,12 +1659,12 @@ INSTANTIATE_TEST_SUITE_P( ARMCPUTestParams( "apple-a16", "armv8.6-a", "crypto-neon-fp-armv8", AArch64::ExtensionBitset( - {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, - AArch64::AEK_SHA3, AArch64::AEK_FP, AArch64::AEK_SIMD, - AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RDM, - AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16, - AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_BF16, - AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, + {AArch64::AEK_CRC, AArch64::AEK_AES, AArch64::AEK_SHA2, + AArch64::AEK_SHA3, AArch64::AEK_FP, AArch64::AEK_SIMD, + AArch64::AEK_LSE, AArch64::AEK_RAS, AArch64::AEK_RDM, + AArch64::AEK_RCPC, AArch64::AEK_DOTPROD, AArch64::AEK_FP16, + AArch64::AEK_FP16FML, AArch64::AEK_SHA3, AArch64::AEK_BF16, + AArch64::AEK_I8MM, AArch64::AEK_JSCVT, AArch64::AEK_FCMA, AArch64::AEK_PAUTH, AArch64::AEK_PERFMON}), "8.4-A"), ARMCPUTestParams(