From 7802640092ba413559b4dc170454c59f1be2da41 Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Thu, 5 Jun 2025 02:51:08 -0700 Subject: [PATCH 1/3] [RISCV] Add XSfmm pseudo instruction and vset* insertion support This patch supports the naive vset* insertion. If the state(tm, tn, tk, sew, widen) changes, it emits all of the vset* instructions that are needed, partial compatibility is not supported yet. Co-authored-by: Piyou Chen --- .../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 4 + .../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h | 66 ++- llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 210 ++++++- llvm/lib/Target/RISCV/RISCVInstrFormats.td | 19 + llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 3 + .../Target/RISCV/RISCVInstrInfoVPseudos.td | 22 +- llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td | 9 +- llvm/lib/Target/RISCV/RISCVInstrInfoXSfmm.td | 138 +++++ llvm/lib/Target/RISCV/RISCVInstrPredicates.td | 33 +- llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 4 + .../RISCV/rvv/sifive-xsfmm-vset-insert.mir | 523 ++++++++++++++++++ 11 files changed, 1008 insertions(+), 23 deletions(-) create mode 100644 llvm/test/CodeGen/RISCV/rvv/sifive-xsfmm-vset-insert.mir diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index 1f434beca5388..8a18221832ecb 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -1616,6 +1616,10 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, "operand must be a valid system register " "name or an integer in the range"); } + case Match_InvalidXSfmmVType: { + SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); + return generateXSfmmVTypeError(ErrorLoc); + } case Match_InvalidVTypeI: { SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); return generateVTypeError(ErrorLoc); diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h index 6ef94fb5e93da..e470d51c6c5fa 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h @@ -138,6 +138,25 @@ enum { // 3 -> SEW * 4 DestEEWShift = ElementsDependOnMaskShift + 1, DestEEWMask = 3ULL << DestEEWShift, + + // 0 -> Don't care about altfmt bit in VTYPE. + // 1 -> Is not altfmt. + // 2 -> Is altfmt(BF16). + AltFmtTypeShift = DestEEWShift + 2, + AltFmtTypeMask = 3ULL << AltFmtTypeShift, + + IsWidenShift = AltFmtTypeShift + 2, + IsWidenMask = 1ULL << IsWidenShift, + + // XSfmmbase + HasTWidenOpShift = IsWidenShift + 1, + HasTWidenOpMask = 1ULL << HasTWidenOpShift, + + HasTMOpShift = HasTWidenOpShift + 1, + HasTMOpMask = 1ULL << HasTMOpShift, + + HasTKOpShift = HasTMOpShift + 1, + HasTKOpMask = 1ULL << HasTKOpShift, }; // Helper functions to read TSFlags. @@ -179,6 +198,11 @@ static inline bool hasRoundModeOp(uint64_t TSFlags) { return TSFlags & HasRoundModeOpMask; } +enum class AltFmtType { DontCare, NotAltFmt, AltFmt }; +static inline AltFmtType getAltFmtType(uint64_t TSFlags) { + return static_cast((TSFlags & AltFmtTypeMask) >> AltFmtTypeShift); +} + /// \returns true if this instruction uses vxrm static inline bool usesVXRM(uint64_t TSFlags) { return TSFlags & UsesVXRMMask; } @@ -194,11 +218,47 @@ static inline bool elementsDependOnMask(uint64_t TSFlags) { return TSFlags & ElementsDependOnMaskMask; } +// XSfmmbase +static inline bool hasTWidenOp(uint64_t TSFlags) { + return TSFlags & HasTWidenOpMask; +} + +static inline bool hasTMOp(uint64_t TSFlags) { return TSFlags & HasTMOpMask; } + +static inline bool hasTKOp(uint64_t TSFlags) { return TSFlags & HasTKOpMask; } + +static inline unsigned getTNOpNum(const MCInstrDesc &Desc) { + const uint64_t TSFlags = Desc.TSFlags; + assert(hasTWidenOp(TSFlags) && hasVLOp(TSFlags)); + unsigned Offset = 3; + if (hasTKOp(TSFlags)) + Offset = 4; + return Desc.getNumOperands() - Offset; +} + +static inline unsigned getTMOpNum(const MCInstrDesc &Desc) { + const uint64_t TSFlags = Desc.TSFlags; + assert(hasTWidenOp(TSFlags) && hasTMOp(TSFlags)); + if (hasTKOp(TSFlags)) + return Desc.getNumOperands() - 5; + // vtzero.t + return Desc.getNumOperands() - 4; +} + +static inline unsigned getTKOpNum(const MCInstrDesc &Desc) { + const uint64_t TSFlags = Desc.TSFlags; + assert(hasTWidenOp(TSFlags) && hasTKOp(TSFlags)); + return Desc.getNumOperands() - 3; +} + static inline unsigned getVLOpNum(const MCInstrDesc &Desc) { const uint64_t TSFlags = Desc.TSFlags; // This method is only called if we expect to have a VL operand, and all // instructions with VL also have SEW. assert(hasSEWOp(TSFlags) && hasVLOp(TSFlags)); + // In Xsfmmbase, TN is alias for VL, so here we use the same TSFlags bit. + if (hasTWidenOp(TSFlags)) + return getTNOpNum(Desc); unsigned Offset = 2; if (hasVecPolicyOp(TSFlags)) Offset = 3; @@ -216,7 +276,7 @@ static inline unsigned getSEWOpNum(const MCInstrDesc &Desc) { const uint64_t TSFlags = Desc.TSFlags; assert(hasSEWOp(TSFlags)); unsigned Offset = 1; - if (hasVecPolicyOp(TSFlags)) + if (hasVecPolicyOp(TSFlags) || hasTWidenOp(TSFlags)) Offset = 2; return Desc.getNumOperands() - Offset; } @@ -233,6 +293,9 @@ static inline int getFRMOpNum(const MCInstrDesc &Desc) { if (!hasRoundModeOp(TSFlags) || usesVXRM(TSFlags)) return -1; + if (hasTWidenOp(TSFlags) && hasTMOp(TSFlags)) + return getTMOpNum(Desc) - 1; + // The operand order // -------------------------------------- // | n-1 (if any) | n-2 | n-3 | n-4 | @@ -375,6 +438,7 @@ enum OperandType : unsigned { // instructions to represent a value that be passed as AVL to either vsetvli // or vsetivli. OPERAND_AVL, + OPERAND_XSFMM_VTYPE, }; } // namespace RISCVOp diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp index e1c69c69a99ca..88d1178eba9b1 100644 --- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp +++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp @@ -164,10 +164,13 @@ struct DemandedFields { // If this is true, we demand that VTYPE is set to some legal state, i.e. that // vill is unset. bool VILL = false; + bool UseTWiden = false; + bool UseAltFmt = false; // Return true if any part of VTYPE was used bool usedVTYPE() const { - return SEW || LMUL || SEWLMULRatio || TailPolicy || MaskPolicy || VILL; + return SEW || LMUL || SEWLMULRatio || TailPolicy || MaskPolicy || VILL || + UseTWiden || UseAltFmt; } // Return true if any property of VL was used @@ -183,6 +186,8 @@ struct DemandedFields { TailPolicy = true; MaskPolicy = true; VILL = true; + UseTWiden = true; + UseAltFmt = true; } // Mark all VL properties as demanded @@ -208,6 +213,8 @@ struct DemandedFields { TailPolicy |= B.TailPolicy; MaskPolicy |= B.MaskPolicy; VILL |= B.VILL; + UseAltFmt |= B.UseAltFmt; + UseTWiden |= B.UseTWiden; } #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) @@ -255,6 +262,8 @@ struct DemandedFields { OS << "TailPolicy=" << TailPolicy << ", "; OS << "MaskPolicy=" << MaskPolicy << ", "; OS << "VILL=" << VILL; + OS << "UseAltFmt=" << UseAltFmt << ", "; + OS << "UseTWiden=" << UseTWiden; OS << "}"; } #endif @@ -324,6 +333,15 @@ static bool areCompatibleVTYPEs(uint64_t CurVType, uint64_t NewVType, if (Used.MaskPolicy && RISCVVType::isMaskAgnostic(CurVType) != RISCVVType::isMaskAgnostic(NewVType)) return false; + if (Used.UseTWiden && (RISCVVType::hasXSfmmWiden(CurVType) != + RISCVVType::hasXSfmmWiden(NewVType) || + (RISCVVType::hasXSfmmWiden(CurVType) && + RISCVVType::getXSfmmWiden(CurVType) != + RISCVVType::getXSfmmWiden(NewVType)))) + return false; + if (Used.UseAltFmt && + RISCVVType::isAltFmt(CurVType) != RISCVVType::isAltFmt(NewVType)) + return false; return true; } @@ -472,6 +490,11 @@ DemandedFields getDemanded(const MachineInstr &MI, const RISCVSubtarget *ST) { Res.TailPolicy = false; } + Res.UseAltFmt = RISCVII::getAltFmtType(MI.getDesc().TSFlags) != + RISCVII::AltFmtType::DontCare; + Res.UseTWiden = RISCVII::hasTWidenOp(MI.getDesc().TSFlags) || + RISCVInstrInfo::isXSfmmVectorConfigInstr(MI); + return Res; } @@ -503,6 +526,8 @@ class VSETVLIInfo { uint8_t TailAgnostic : 1; uint8_t MaskAgnostic : 1; uint8_t SEWLMULRatioOnly : 1; + uint8_t AltFmt : 1; + uint8_t TWiden = 0; public: VSETVLIInfo() @@ -579,6 +604,8 @@ class VSETVLIInfo { RISCVVType::VLMUL getVLMUL() const { return VLMul; } bool getTailAgnostic() const { return TailAgnostic; } bool getMaskAgnostic() const { return MaskAgnostic; } + bool getAltFmt() const { return AltFmt; } + unsigned getTWiden() const { return TWiden; } bool hasNonZeroAVL(const LiveIntervals *LIS) const { if (hasAVLImm()) @@ -640,21 +667,31 @@ class VSETVLIInfo { SEW = RISCVVType::getSEW(VType); TailAgnostic = RISCVVType::isTailAgnostic(VType); MaskAgnostic = RISCVVType::isMaskAgnostic(VType); + AltFmt = RISCVVType::isAltFmt(VType); + TWiden = + RISCVVType::hasXSfmmWiden(VType) ? RISCVVType::getXSfmmWiden(VType) : 0; } - void setVTYPE(RISCVVType::VLMUL L, unsigned S, bool TA, bool MA) { + void setVTYPE(RISCVVType::VLMUL L, unsigned S, bool TA, bool MA, bool Altfmt, + unsigned W) { assert(isValid() && !isUnknown() && "Can't set VTYPE for uninitialized or unknown"); VLMul = L; SEW = S; TailAgnostic = TA; MaskAgnostic = MA; + AltFmt = Altfmt; + TWiden = W; } + void setAltFmt(bool AF) { AltFmt = AF; } + void setVLMul(RISCVVType::VLMUL VLMul) { this->VLMul = VLMul; } unsigned encodeVTYPE() const { assert(isValid() && !isUnknown() && !SEWLMULRatioOnly && "Can't encode VTYPE for uninitialized or unknown"); + if (TWiden != 0) + return RISCVVType::encodeXSfmmVType(SEW, TWiden, AltFmt); return RISCVVType::encodeVTYPE(VLMul, SEW, TailAgnostic, MaskAgnostic); } @@ -667,9 +704,9 @@ class VSETVLIInfo { "Can't compare VTYPE in unknown state"); assert(!SEWLMULRatioOnly && !Other.SEWLMULRatioOnly && "Can't compare when only LMUL/SEW ratio is valid."); - return std::tie(VLMul, SEW, TailAgnostic, MaskAgnostic) == + return std::tie(VLMul, SEW, TailAgnostic, MaskAgnostic, AltFmt, TWiden) == std::tie(Other.VLMul, Other.SEW, Other.TailAgnostic, - Other.MaskAgnostic); + Other.MaskAgnostic, Other.AltFmt, Other.TWiden); } unsigned getSEWLMULRatio() const { @@ -819,6 +856,8 @@ class VSETVLIInfo { << "TailAgnostic=" << (bool)TailAgnostic << ", " << "MaskAgnostic=" << (bool)MaskAgnostic << ", " << "SEWLMULRatioOnly=" << (bool)SEWLMULRatioOnly << "}"; + OS << "TWiden=" << (bool)TWiden << ", "; + OS << "AltFmt=" << (bool)AltFmt << "}"; } #endif }; @@ -846,6 +885,11 @@ struct BlockData { BlockData() = default; }; +enum TKTMMode { + VSETTK = 0, + VSETTM = 1, +}; + class RISCVInsertVSETVLI : public MachineFunctionPass { const RISCVSubtarget *ST; const TargetInstrInfo *TII; @@ -901,6 +945,7 @@ class RISCVInsertVSETVLI : public MachineFunctionPass { VSETVLIInfo getInfoForVSETVLI(const MachineInstr &MI) const; VSETVLIInfo computeInfoForInstr(const MachineInstr &MI) const; void forwardVSETVLIAVL(VSETVLIInfo &Info) const; + bool insertVSETMTK(MachineBasicBlock &MBB, TKTMMode Mode) const; }; } // end anonymous namespace @@ -938,6 +983,16 @@ RISCVInsertVSETVLI::getInfoForVSETVLI(const MachineInstr &MI) const { VSETVLIInfo NewInfo; if (MI.getOpcode() == RISCV::PseudoVSETIVLI) { NewInfo.setAVLImm(MI.getOperand(1).getImm()); + } else if (RISCVInstrInfo::isXSfmmVectorTNConfigInstr(MI)) { + Register ATReg = MI.getOperand(1).getReg(); + switch (MI.getOpcode()) { + case RISCV::PseudoSF_VSETTNTX0: + NewInfo.setAVLVLMAX(); + break; + case RISCV::PseudoSF_VSETTNT: + NewInfo.setAVLRegDef(getVNInfoFromReg(ATReg, MI, LIS), ATReg); + break; + } } else { assert(MI.getOpcode() == RISCV::PseudoVSETVLI || MI.getOpcode() == RISCV::PseudoVSETVLIX0); @@ -998,11 +1053,36 @@ RISCVInsertVSETVLI::computeInfoForInstr(const MachineInstr &MI) const { RISCVVType::VLMUL VLMul = RISCVII::getLMul(TSFlags); + bool AltFmt = RISCVII::getAltFmtType(TSFlags) == RISCVII::AltFmtType::AltFmt; + InstrInfo.setAltFmt(AltFmt); + unsigned Log2SEW = MI.getOperand(getSEWOpNum(MI)).getImm(); // A Log2SEW of 0 is an operation on mask registers only. unsigned SEW = Log2SEW ? 1 << Log2SEW : 8; assert(RISCVVType::isValidSEW(SEW) && "Unexpected SEW"); + if (RISCVII::hasTWidenOp(TSFlags)) { + assert(RISCVVType::isValidSEW(SEW) && "Unexpected SEW"); + + const MachineOperand &TWidenOp = + MI.getOperand(MI.getNumExplicitOperands() - 1); + unsigned TWiden = TWidenOp.getImm(); + + InstrInfo.setAVLVLMAX(); + if (RISCVII::hasVLOp(TSFlags)) { + const MachineOperand &TnOp = + MI.getOperand(RISCVII::getTNOpNum(MI.getDesc())); + + if (TnOp.getReg().isVirtual()) + InstrInfo.setAVLRegDef(getVNInfoFromReg(TnOp.getReg(), MI, LIS), + TnOp.getReg()); + } + + InstrInfo.setVTYPE(VLMul, SEW, TailAgnostic, MaskAgnostic, AltFmt, TWiden); + + return InstrInfo; + } + if (RISCVII::hasVLOp(TSFlags)) { const MachineOperand &VLOp = MI.getOperand(getVLOpNum(MI)); if (VLOp.isImm()) { @@ -1038,7 +1118,9 @@ RISCVInsertVSETVLI::computeInfoForInstr(const MachineInstr &MI) const { assert(SEW == EEW && "Initial SEW doesn't match expected EEW"); } #endif - InstrInfo.setVTYPE(VLMul, SEW, TailAgnostic, MaskAgnostic); + // TODO: Propagate the twiden from previous vtype for potential reuse. + InstrInfo.setVTYPE(VLMul, SEW, TailAgnostic, MaskAgnostic, AltFmt, + /*TWiden*/ 0); forwardVSETVLIAVL(InstrInfo); @@ -1048,8 +1130,30 @@ RISCVInsertVSETVLI::computeInfoForInstr(const MachineInstr &MI) const { void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertPt, DebugLoc DL, const VSETVLIInfo &Info, const VSETVLIInfo &PrevInfo) { - ++NumInsertedVSETVL; + + if (Info.getTWiden()) { + if (Info.hasAVLVLMAX()) { + Register DestReg = MRI->createVirtualRegister(&RISCV::GPRRegClass); + auto MI = BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoSF_VSETTNTX0)) + .addReg(DestReg, RegState::Define | RegState::Dead) + .addReg(RISCV::X0, RegState::Kill) + .addImm(Info.encodeVTYPE()); + if (LIS) { + LIS->InsertMachineInstrInMaps(*MI); + LIS->createAndComputeVirtRegInterval(DestReg); + } + } else { + auto MI = BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoSF_VSETTNT)) + .addReg(RISCV::X0, RegState::Define | RegState::Dead) + .addReg(Info.getAVLReg()) + .addImm(Info.encodeVTYPE()); + if (LIS) + LIS->InsertMachineInstrInMaps(*MI); + } + return; + } + if (PrevInfo.isValid() && !PrevInfo.isUnknown()) { // Use X0, X0 form if the AVL is the same and the SEW+LMUL gives the same // VLMAX. @@ -1190,7 +1294,8 @@ void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info, // be coalesced into another vsetvli since we won't demand any fields. VSETVLIInfo NewInfo; // Need a new VSETVLIInfo to clear SEWLMULRatioOnly NewInfo.setAVLImm(1); - NewInfo.setVTYPE(RISCVVType::LMUL_1, /*sew*/ 8, /*ta*/ true, /*ma*/ true); + NewInfo.setVTYPE(RISCVVType::LMUL_1, /*sew*/ 8, /*ta*/ true, /*ma*/ true, + /*AltFmt*/ false, /*W*/ 0); Info = NewInfo; return; } @@ -1232,7 +1337,9 @@ void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info, (Demanded.TailPolicy ? IncomingInfo : Info).getTailAgnostic() || IncomingInfo.getTailAgnostic(), (Demanded.MaskPolicy ? IncomingInfo : Info).getMaskAgnostic() || - IncomingInfo.getMaskAgnostic()); + IncomingInfo.getMaskAgnostic(), + (Demanded.UseAltFmt ? IncomingInfo : Info).getAltFmt(), + Demanded.UseTWiden ? IncomingInfo.getTWiden() : 0); // If we only knew the sew/lmul ratio previously, replace the VTYPE but keep // the AVL. @@ -1285,7 +1392,8 @@ bool RISCVInsertVSETVLI::computeVLVTYPEChanges(const MachineBasicBlock &MBB, if (RISCVInstrInfo::isVectorConfigInstr(MI) || RISCVII::hasSEWOp(MI.getDesc().TSFlags) || - isVectorCopy(ST->getRegisterInfo(), MI)) + isVectorCopy(ST->getRegisterInfo(), MI) || + RISCVInstrInfo::isXSfmmVectorConfigInstr(MI)) HadVectorOp = true; transferAfter(Info, MI); @@ -1667,6 +1775,10 @@ void RISCVInsertVSETVLI::coalesceVSETVLIs(MachineBasicBlock &MBB) const { }; for (MachineInstr &MI : make_early_inc_range(reverse(MBB))) { + // TODO: Support XSfmm. + if (RISCVII::hasTWidenOp(MI.getDesc().TSFlags) || + RISCVInstrInfo::isXSfmmVectorConfigInstr(MI)) + continue; if (!RISCVInstrInfo::isVectorConfigInstr(MI)) { Used.doUnion(getDemanded(MI, ST)); @@ -1774,6 +1886,80 @@ void RISCVInsertVSETVLI::insertReadVL(MachineBasicBlock &MBB) { } } +static void shrinkIntervalAndRemoveDeadMI(MachineOperand &MO, + LiveIntervals *LIS) { + Register Reg = MO.getReg(); + MO.setReg(RISCV::NoRegister); + MO.setIsKill(false); + + if (!LIS) + return; + + LiveInterval &LI = LIS->getInterval(Reg); + + // Erase the AVL operand from the instruction. + SmallVector DeadMIs; + LIS->shrinkToUses(&LI, &DeadMIs); + // TODO: Enable this once needVSETVLIPHI is supported. + // SmallVector SplitLIs; + // LIS->splitSeparateComponents(LI, SplitLIs); + + for (MachineInstr *DeadMI : DeadMIs) { + LIS->RemoveMachineInstrFromMaps(*DeadMI); + DeadMI->eraseFromParent(); + } +} + +bool RISCVInsertVSETVLI::insertVSETMTK(MachineBasicBlock &MBB, + TKTMMode Mode) const { + + bool Changed = false; + for (auto &MI : MBB) { + uint64_t TSFlags = MI.getDesc().TSFlags; + if (RISCVInstrInfo::isXSfmmVectorConfigTMTKInstr(MI) || + !RISCVII::hasSEWOp(TSFlags) || !RISCVII::hasTWidenOp(TSFlags)) + continue; + + VSETVLIInfo CurrInfo = computeInfoForInstr(MI); + + if (Mode == VSETTK && !RISCVII::hasTKOp(TSFlags)) + continue; + + if (Mode == VSETTM && !RISCVII::hasTMOp(TSFlags)) + continue; + + unsigned OpNum = 0; + unsigned Opcode = 0; + switch (Mode) { + case VSETTK: + OpNum = RISCVII::getTKOpNum(MI.getDesc()); + Opcode = RISCV::PseudoSF_VSETTK; + break; + case VSETTM: + OpNum = RISCVII::getTMOpNum(MI.getDesc()); + Opcode = RISCV::PseudoSF_VSETTM; + break; + } + + assert(OpNum && Opcode && "Invalid OpNum or Opcode"); + + const MachineOperand &Op = MI.getOperand(OpNum); + + auto TmpMI = BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(Opcode)) + .addReg(RISCV::X0, RegState::Define | RegState::Dead) + .addReg(Op.getReg()) + .addImm(Log2_32(CurrInfo.getSEW())) + .addImm((CurrInfo.getTWiden() >> 1) + 1); + + Changed = true; + if (LIS) + LIS->InsertMachineInstrInMaps(*TmpMI); + + shrinkIntervalAndRemoveDeadMI(MI.getOperand(OpNum), LIS); + } + return Changed; +} + bool RISCVInsertVSETVLI::runOnMachineFunction(MachineFunction &MF) { // Skip if the vector extension is not enabled. ST = &MF.getSubtarget(); @@ -1851,6 +2037,12 @@ bool RISCVInsertVSETVLI::runOnMachineFunction(MachineFunction &MF) { for (MachineBasicBlock &MBB : MF) insertReadVL(MBB); + for (MachineBasicBlock &MBB : MF) + insertVSETMTK(MBB, VSETTM); + + for (MachineBasicBlock &MBB : MF) + insertVSETMTK(MBB, VSETTK); + BlockInfo.clear(); return HaveVectorOp; } diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td index 088a6923fadb1..81105b7815838 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td +++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td @@ -257,6 +257,25 @@ class RVInstCommon Don't care about altfmt bit in VTYPE. + // 1 -> Is not altfmt. + // 2 -> Is altfmt(BF16). + bits<2> AltFmtType = 0; + let TSFlags{27-26} = AltFmtType; + + bit IsWiden = 0; + let TSFlags{28} = IsWiden; + + // XSfmmbase + bit HasTWidenOp = 0; + let TSFlags{29} = HasTWidenOp; + + bit HasTmOp = 0; + let TSFlags{30} = HasTmOp; + + bit HasTkOp = 0; + let TSFlags{31} = HasTkOp; } class RVInst { ["_M4", ""], ["_M8", ""], ["_SE", ""], - ["_RM", ""] + ["_RM", ""], + ["_ALT", ""] ]; string VInst = !foldl(PseudoInst, AffixSubsts, Acc, AffixSubst, !subst(AffixSubst[0], AffixSubst[1], Acc)); @@ -6436,7 +6440,7 @@ let Defs = [VXSAT] in { // 13. Vector Floating-Point Instructions //===----------------------------------------------------------------------===// -let Predicates = [HasVInstructionsAnyF] in { +let Predicates = [HasVInstructionsAnyF], AltFmtType = IS_NOT_ALTFMT in { //===----------------------------------------------------------------------===// // 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions //===----------------------------------------------------------------------===// @@ -6609,7 +6613,7 @@ defm PseudoVFNCVTBF16_F_F : VPseudoVNCVTD_W_RM; defm PseudoVFNCVT_ROD_F_F : VPseudoVNCVTD_W; } // mayRaiseFPException = true -} // Predicates = [HasVInstructionsAnyF] +} // Predicates = [HasVInstructionsAnyF], AltFmtType = IS_NOT_ALTFMT //===----------------------------------------------------------------------===// // 14. Vector Reduction Operations @@ -6637,7 +6641,7 @@ defm PseudoVWREDSUM : VPseudoVWRED_VS; } } // Predicates = [HasVInstructions] -let Predicates = [HasVInstructionsAnyF] in { +let Predicates = [HasVInstructionsAnyF], AltFmtType = IS_NOT_ALTFMT in { //===----------------------------------------------------------------------===// // 14.3. Vector Single-Width Floating-Point Reduction Instructions //===----------------------------------------------------------------------===// @@ -6656,7 +6660,7 @@ defm PseudoVFWREDUSUM : VPseudoVFWRED_VS_RM; defm PseudoVFWREDOSUM : VPseudoVFWREDO_VS_RM; } -} // Predicates = [HasVInstructionsAnyF] +} // Predicates = [HasVInstructionsAnyF], AltFmtType = IS_NOT_ALTFMT //===----------------------------------------------------------------------===// // 15. Vector Mask Instructions @@ -6749,7 +6753,7 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { // 16.2. Floating-Point Scalar Move Instructions //===----------------------------------------------------------------------===// -let Predicates = [HasVInstructionsAnyF] in { +let Predicates = [HasVInstructionsAnyF], AltFmtType = IS_NOT_ALTFMT in { let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { foreach f = FPList in { let HasSEWOp = 1, BaseInstr = VFMV_F_S in @@ -6768,7 +6772,7 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { RISCVVPseudo; } } -} // Predicates = [HasVInstructionsAnyF] +} // Predicates = [HasVInstructionsAnyF], AltFmtType = IS_NOT_ALTFMT //===----------------------------------------------------------------------===// // 16.3. Vector Slide Instructions @@ -6780,10 +6784,10 @@ let Predicates = [HasVInstructions] in { defm PseudoVSLIDE1DOWN : VPseudoVSLD1_VX; } // Predicates = [HasVInstructions] -let Predicates = [HasVInstructionsAnyF] in { +let Predicates = [HasVInstructionsAnyF], AltFmtType = IS_NOT_ALTFMT in { defm PseudoVFSLIDE1UP : VPseudoVSLD1_VF<"@earlyclobber $rd">; defm PseudoVFSLIDE1DOWN : VPseudoVSLD1_VF; -} // Predicates = [HasVInstructionsAnyF] +} // Predicates = [HasVInstructionsAnyF], AltFmtType = IS_NOT_ALTFMT //===----------------------------------------------------------------------===// // 16.4. Vector Register Gather Instructions diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td index affe3a8476753..c715373386d50 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td @@ -419,8 +419,10 @@ let Predicates = [HasVendorXSfvcp] in { } foreach f = FPList in { foreach m = f.MxList in { - defm f.FX # "V" : VPseudoVC_XV; - defm f.FX # "VV" : VPseudoVC_XVV; + let AltFmtType = IS_NOT_ALTFMT in { + defm f.FX # "V" : VPseudoVC_XV; + defm f.FX # "VV" : VPseudoVC_XVV; + } } } foreach m = MxListW in { @@ -430,7 +432,8 @@ let Predicates = [HasVendorXSfvcp] in { } foreach f = FPListW in { foreach m = f.MxList in - defm f.FX # "VW" : VPseudoVC_XVW; + let AltFmtType = IS_NOT_ALTFMT in + defm f.FX # "VW" : VPseudoVC_XVW; } } diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXSfmm.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXSfmm.td index 66cb2d53da960..750cd89fb5eb8 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXSfmm.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXSfmm.td @@ -272,3 +272,141 @@ let Uses = [FRM], mayRaiseFPException = true in { } // Predicates = [HasVendorXSfmm32a8f] } // DecoderNamespace = "XSfvector" + +class VPseudoSF_VTileLoad + : Pseudo<(outs), (ins GPR:$rs2, GPR:$rs1, AVL:$atn, ixlenimm:$sew, + ixlenimm:$twiden), []>, + RISCVVPseudo { + let mayLoad = 1; + let mayStore = 0; + let HasVLOp = 1; // Tn + let HasSEWOp = 1; + let HasTWidenOp = 1; + let hasSideEffects = 1; +} + +class VPseudoSF_VTileStore + : Pseudo<(outs), (ins GPR:$rs2, GPR:$rs1, AVL:$atn, ixlenimm:$sew, + ixlenimm:$twiden), []>, + RISCVVPseudo { + let mayLoad = 0; + let mayStore = 1; + let HasVLOp = 1; // Tn + let HasSEWOp = 1; + let HasTWidenOp = 1; + let hasSideEffects = 1; +} + +class VPseudoSF_VTileMove_V_T + : Pseudo<(outs VRM8:$vd), (ins GPR:$rs1, AVL:$atn, ixlenimm:$sew, + ixlenimm:$twiden), []>, + RISCVVPseudo { + let mayLoad = 0; + let mayStore = 0; + let HasVLOp = 1; // Tn + let HasSEWOp = 1; + let HasTWidenOp = 1; + let hasSideEffects = 1; +} + +class VPseudoSF_VTileMove_T_V + : Pseudo<(outs), (ins GPR:$rs1, VRM8:$vs2, AVL:$atn, ixlenimm:$sew, + ixlenimm:$twiden), []>, + RISCVVPseudo { + let mayLoad = 0; + let mayStore = 0; + let HasVLOp = 1; // Tn + let HasSEWOp = 1; + let HasTWidenOp = 1; + let hasSideEffects = 1; +} + +class VPseudoSF_MatMul + : Pseudo<(outs), + (ins mtd_class:$rd, VRM8:$vs2, VRM8:$vs1, AVL:$atm, AVL:$atn, + AVL:$atk, ixlenimm:$sew, ixlenimm:$twiden), []>, + RISCVVPseudo { + let mayLoad = 0; + let mayStore = 0; + let HasTmOp = 1; + let HasVLOp = 1; // Tn + let HasTkOp = 1; + let HasSEWOp = 1; + let HasTWidenOp = 1; + let hasSideEffects = 1; +} + +class VPseudoSF_MatMul_FRM + : Pseudo<(outs), + (ins mtd_class:$rd, VRM8:$vs2, VRM8:$vs1, ixlenimm:$frm, + AVL:$atm, AVL:$atn, AVL:$atk, ixlenimm:$sew, + ixlenimm:$twiden), []>, + RISCVVPseudo { + let mayLoad = 0; + let mayStore = 0; + let HasTmOp = 1; + let HasVLOp = 1; // Tn + let HasTkOp = 1; + let HasSEWOp = 1; + let HasRoundModeOp = 1; + let hasPostISelHook = 1; + let HasTWidenOp = 1; + let hasSideEffects = 1; + let BaseInstr = !cast(PseudoToVInst.VInst); +} + +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { +let Defs = [VL, VTYPE] in { + def PseudoSF_VSETTNT + : Pseudo<(outs GPR:$rd), + (ins GPRNoX0:$rs1, XSfmmVTypeOp:$vtypei), []>, + PseudoInstExpansion<(VSETVLI GPR:$rd, GPR:$rs1, VTypeIOp11:$vtypei)>, + Sched<[WriteVSETVLI, ReadVSETVLI]>; + def PseudoSF_VSETTNTX0 + : Pseudo<(outs GPR:$rd), + (ins GPRX0:$rs1, XSfmmVTypeOp:$vtypei), []>, + PseudoInstExpansion<(VSETVLI GPR:$rd, GPR:$rs1, VTypeIOp11:$vtypei)>, + Sched<[WriteVSETVLI, ReadVSETVLI]>; +} + +let Defs = [VTYPE], Uses = [VTYPE], HasTWidenOp = 1, HasSEWOp = 1 in { + def PseudoSF_VSETTM + : Pseudo<(outs GPR:$rd), (ins GPR:$rs1, ixlenimm:$log2sew, ixlenimm:$twiden), []>, + PseudoInstExpansion<(SF_VSETTM GPR:$rd, GPR:$rs1)>, + Sched<[WriteVSETVLI, ReadVSETVLI]>; + def PseudoSF_VSETTK + : Pseudo<(outs GPR:$rd), (ins GPR:$rs1, ixlenimm:$logwsew, ixlenimm:$twiden), []>, + PseudoInstExpansion<(SF_VSETTK GPR:$rd, GPR:$rs1)>, + Sched<[WriteVSETVLI, ReadVSETVLI]>; +} +} + +foreach eew = [8, 16, 32, 64] in { + def PseudoSF_VLTE # eew : VPseudoSF_VTileLoad; + def PseudoSF_VSTE # eew : VPseudoSF_VTileStore; +} + +def PseudoSF_VTMV_T_V : VPseudoSF_VTileMove_T_V; +def PseudoSF_VTMV_V_T : VPseudoSF_VTileMove_V_T; + +foreach a = I8Encodes in + foreach b = I8Encodes in + def PseudoSF_MM_ # !toupper(a.Name) # _ # !toupper(b.Name) + : VPseudoSF_MatMul; + +let AltFmtType = IS_NOT_ALTFMT in + def PseudoSF_MM_F_F : VPseudoSF_MatMul_FRM; +let AltFmtType = IS_ALTFMT in + def PseudoSF_MM_F_F_ALT : VPseudoSF_MatMul_FRM; + +foreach e1 = [5, 4] in + foreach e2 = [5, 4] in + def PseudoSF_MM_E # e1 # M # !sub(7, e1) # _E # e2 # M # !sub(7, e2) + : VPseudoSF_MatMul_FRM; + +let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in { + let HasVLOp = 1, HasTmOp = 1, HasTWidenOp = 1, HasSEWOp = 1 in + def PseudoSF_VTZERO_T + : Pseudo<(outs), (ins TR:$rd, AVL:$atm, AVL:$atn, ixlenimm:$sew, ixlenimm:$twiden), []>, RISCVVPseudo; + def PseudoSF_VTDISCARD : Pseudo<(outs), (ins), []>, RISCVVPseudo; +} diff --git a/llvm/lib/Target/RISCV/RISCVInstrPredicates.td b/llvm/lib/Target/RISCV/RISCVInstrPredicates.td index 4c37cb7e393bf..1a5c6167ee80a 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrPredicates.td +++ b/llvm/lib/Target/RISCV/RISCVInstrPredicates.td @@ -71,7 +71,38 @@ def isVectorConfigInstr PseudoVSETVLI, PseudoVSETVLIX0, PseudoVSETVLIX0X0, - PseudoVSETIVLI + PseudoVSETIVLI, + PseudoSF_VSETTNT, + PseudoSF_VSETTNTX0 + ]>>>; + +// Returns true if this is a PseudoSF_VSETTNT* instructions. +def isXSfmmVectorTNConfigInstr + : TIIPredicate<"isXSfmmVectorTNConfigInstr", + MCReturnStatement< + CheckOpcode<[ + PseudoSF_VSETTNT, + PseudoSF_VSETTNTX0 + ]>>>; + +// Returns true if this is PseudoSF_VSETTM or PseudoSF_VSETTK. +def isXSfmmVectorConfigTMTKInstr + : TIIPredicate<"isXSfmmVectorConfigTMTKInstr", + MCReturnStatement< + CheckOpcode<[ + PseudoSF_VSETTM, + PseudoSF_VSETTK + ]>>>; + +// Returns true if this is a XSfmm vector configuration instruction. +def isXSfmmVectorConfigInstr + : TIIPredicate<"isXSfmmVectorConfigInstr", + MCReturnStatement< + CheckOpcode<[ + PseudoSF_VSETTNT, + PseudoSF_VSETTNTX0, + PseudoSF_VSETTM, + PseudoSF_VSETTK ]>>>; // Return true if this is 'vsetvli x0, x0, vtype' which preserves diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp index 112142e1ef2f2..6888f74da244f 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp @@ -165,6 +165,10 @@ BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const { // Shadow stack pointer. markSuperRegs(Reserved, RISCV::SSP); + // XSfmmbase + for (MCPhysReg Reg = RISCV::T0; Reg <= RISCV::T15; Reg++) + markSuperRegs(Reserved, Reg); + assert(checkAllSuperRegsMarked(Reserved)); return Reserved; } diff --git a/llvm/test/CodeGen/RISCV/rvv/sifive-xsfmm-vset-insert.mir b/llvm/test/CodeGen/RISCV/rvv/sifive-xsfmm-vset-insert.mir new file mode 100644 index 0000000000000..9b0b0c41581bc --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/sifive-xsfmm-vset-insert.mir @@ -0,0 +1,523 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v \ +# RUN: -run-pass=phi-node-elimination,register-coalescer,riscv-insert-vsetvli | FileCheck %s + +--- | + define void @xsfmm_same_state( %tile1, %tile2, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) { + entry: + tail call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 2, %tile1, %tile2, i64 %tm, i64 %tn, i64 %tk, i64 2) + tail call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 2, %tile1, %tile2, i64 %tm, i64 %tn, i64 %tk, i64 2) + ret void + } + + define void @xsfmm_different_state( %tile1, %tile2, i64 %tm, i64 %tn, i64 %tk) { + entry: + tail call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 2, %tile1, %tile2, i64 %tm, i64 %tn, i64 %tk, i64 2) + tail call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 2, %tile1, %tile2, i64 %tm, i64 %tn, i64 %tk, i64 4) + ret void + } + + define void @xsfmm_different_state_bf( %tile1, %tile2, i64 %tm, i64 %tn, i64 %tk) { + entry: + tail call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 2, %tile1, %tile1, i64 %tm, i64 %tn, i64 %tk, i64 2) + tail call void @llvm.riscv.sf.mm.f.f.i64.nxv32bf16(i64 2, %tile2, %tile2, i64 %tm, i64 %tn, i64 %tk, i64 2) + tail call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 2, %tile1, %tile1, i64 %tm, i64 %tn, i64 %tk, i64 2) + ret void + } + + define @interleave_rvv_and_xsfmm( %tile, i64 %vl, ptr %base) { + entry: + %0 = call @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 1, i64 %vl) + %1 = call @llvm.riscv.vadd.nxv64i8.nxv64i8.i64( poison, %tile, %0, i64 %vl) + call void @llvm.riscv.sf.vste16.i64(i64 1, ptr %base, i64 %vl) + ret %1 + } + + define @interleave_rvv_and_xsfmm2( %tile, i64 %vl, ptr %base) { + entry: + %0 = call @llvm.riscv.vadd.nxv64i8.nxv64i8.i64( poison, %tile, %tile, i64 %vl) + %1 = call @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 1, i64 %vl) + %2 = call @llvm.riscv.vadd.nxv64i8.nxv64i8.i64( poison, %tile, %0, i64 %vl) + call void @llvm.riscv.sf.vste16.i64(i64 1, ptr %base, i64 %vl) + ret %2 + } + + define void @consecutive_xsfmm( %tile, i64 %tm, i64 %tn, i64 %tk, ptr %base) { + entry: + tail call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 0, %tile, %tile, i64 %tm, i64 %tn, i64 %tk, i64 2) + call void @llvm.riscv.sf.vste16.i64(i64 0, ptr %base, i64 %tn) + ret void + } + + define i64 @vsettnt_max(i64 %vl) { + entry: + %0 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %vl, i64 1, i64 2) + %1 = call i64 @llvm.riscv.sf.vsettnt_max.i64(i64 1, i64 2) + ret i64 %0 + } + + define i64 @single_vsettm(i64 %vl) { + entry: + %0 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %vl, i64 1, i64 2) + ret i64 %0 + } + + define i64 @single_vsettn(i64 %vl) { + entry: + %0 = call i64 @llvm.riscv.sf.vsettn.i64(i64 %vl, i64 1, i64 2) + ret i64 %0 + } + + define i64 @single_vsettk(i64 %vl) { + entry: + %0 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %vl, i64 1, i64 2) + ret i64 %0 + } + + define void @sf_vtzero(i64 %tm, i64 %tn) { + entry: + call void @llvm.riscv.sf.vtzero.i64(i64 1, i64 %tm, i64 %tn, i64 3, i64 4) + ret void + } + + declare void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64, , , i64, i64, i64, i64) + declare void @llvm.riscv.sf.mm.f.f.i64.nxv32bf16(i64, , , i64, i64, i64, i64) + declare @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64, i64) + declare @llvm.riscv.vadd.nxv64i8.nxv64i8.i64(, , , i64) + declare void @llvm.riscv.sf.vste16.i64(i64, ptr, i64) + declare i64 @llvm.riscv.sf.vsettnt_max.i64(i64, i64) + declare i64 @llvm.riscv.sf.vsettm.i64(i64, i64, i64) + declare i64 @llvm.riscv.sf.vsettn.i64(i64, i64, i64) + declare i64 @llvm.riscv.sf.vsettk.i64(i64, i64, i64) + declare void @llvm.riscv.sf.vtzero.i64(i64, i64, i64, i64, i64) +... +--- +name: xsfmm_same_state +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: vrm8 } + - { id: 1, class: vrm8 } + - { id: 2, class: gprnox0 } + - { id: 3, class: gprnox0 } + - { id: 4, class: gprnox0 } +liveins: + - { reg: '$v8m8', virtual-reg: '%0' } + - { reg: '$v8m8', virtual-reg: '%1' } + - { reg: '$x10', virtual-reg: '%2' } + - { reg: '$x11', virtual-reg: '%3' } + - { reg: '$x12', virtual-reg: '%4' } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: {} +body: | + bb.0.entry: + liveins: $v8m8, $v16m8, $x10, $x11, $x12 + ; CHECK-LABEL: name: xsfmm_same_state + ; CHECK: liveins: $v8m8, $v16m8, $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x12 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gprnox0 = COPY $x10 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vrm8 = COPY $v16m8 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vrm8 = COPY $v8m8 + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1032, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4, 2, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4, 2, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY3]], 7, $noreg, $noreg, $noreg, 4, 2, implicit $frm, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4, 2, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4, 2, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY3]], 7, $noreg, $noreg, $noreg, 4, 2, implicit $frm, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoRET + %4:gprnox0 = COPY $x12 + %3:gprnox0 = COPY $x11 + %2:gprnox0 = COPY $x10 + %1:vrm8 = COPY $v16m8 + %0:vrm8 = COPY $v8m8 + PseudoSF_MM_F_F $t2, %0:vrm8, %1:vrm8, 7, %2:gprnox0, %3:gprnox0, %4:gprnox0, 4, 2, implicit $frm + PseudoSF_MM_F_F $t2, %0:vrm8, %1:vrm8, 7, %2:gprnox0, %3:gprnox0, %4:gprnox0, 4, 2, implicit $frm + PseudoRET +... +--- +name: xsfmm_different_state +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: vrm8 } + - { id: 1, class: vrm8 } + - { id: 2, class: gprnox0 } + - { id: 3, class: gprnox0 } + - { id: 4, class: gprnox0 } +liveins: + - { reg: '$v8m8', virtual-reg: '%0' } + - { reg: '$v8m8', virtual-reg: '%1' } + - { reg: '$x10', virtual-reg: '%2' } + - { reg: '$x11', virtual-reg: '%3' } + - { reg: '$x12', virtual-reg: '%4' } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: {} +body: | + bb.0.entry: + liveins: $v8m8, $v16m8, $x10, $x11, $x12 + ; CHECK-LABEL: name: xsfmm_different_state + ; CHECK: liveins: $v8m8, $v16m8, $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x12 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gprnox0 = COPY $x10 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vrm8 = COPY $v16m8 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vrm8 = COPY $v8m8 + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1032, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4, 2, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4, 2, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY3]], 7, $noreg, $noreg, $noreg, 4, 2, implicit $frm, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1544, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4, 3, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4, 3, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY3]], 7, $noreg, $noreg, $noreg, 4, 4, implicit $frm, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoRET + %4:gprnox0 = COPY $x12 + %3:gprnox0 = COPY $x11 + %2:gprnox0 = COPY $x10 + %1:vrm8 = COPY $v16m8 + %0:vrm8 = COPY $v8m8 + PseudoSF_MM_F_F $t2, %0:vrm8, %1:vrm8, 7, %2:gprnox0, %3:gprnox0, %4:gprnox0, 4, 2, implicit $frm + PseudoSF_MM_F_F $t2, %0:vrm8, %1:vrm8, 7, %2:gprnox0, %3:gprnox0, %4:gprnox0, 4, 4, implicit $frm + PseudoRET +... +--- +name: xsfmm_different_state_bf +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: vrm8 } + - { id: 1, class: vrm8 } + - { id: 2, class: gprnox0 } + - { id: 3, class: gprnox0 } + - { id: 4, class: gprnox0 } +liveins: + - { reg: '$v8m8', virtual-reg: '%0' } + - { reg: '$v8m8', virtual-reg: '%1' } + - { reg: '$x10', virtual-reg: '%2' } + - { reg: '$x11', virtual-reg: '%3' } + - { reg: '$x12', virtual-reg: '%4' } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: {} +body: | + bb.0.entry: + liveins: $v8m8, $v16m8, $x10, $x11, $x12 + ; CHECK-LABEL: name: xsfmm_different_state_bf + ; CHECK: liveins: $v8m8, $v16m8, $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x12 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gprnox0 = COPY $x10 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vrm8 = COPY $v16m8 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vrm8 = COPY $v8m8 + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1032, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4, 2, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4, 2, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY4]], 7, $noreg, $noreg, $noreg, 4, 2, implicit $frm, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1288, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4, 2, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4, 2, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: PseudoSF_MM_F_F_ALT $t2, [[COPY3]], [[COPY3]], 7, $noreg, $noreg, $noreg, 4, 2, implicit $frm, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1032, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4, 2, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4, 2, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY4]], 7, $noreg, $noreg, $noreg, 4, 2, implicit $frm, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoRET + %4:gprnox0 = COPY $x12 + %3:gprnox0 = COPY $x11 + %2:gprnox0 = COPY $x10 + %1:vrm8 = COPY $v16m8 + %0:vrm8 = COPY $v8m8 + PseudoSF_MM_F_F $t2, %0:vrm8, %0:vrm8, 7, %2:gprnox0, %3:gprnox0, %4:gprnox0, 4, 2, implicit $frm + PseudoSF_MM_F_F_ALT $t2, %1:vrm8, %1:vrm8, 7, %2:gprnox0, %3:gprnox0, %4:gprnox0, 4, 2, implicit $frm + PseudoSF_MM_F_F $t2, %0:vrm8, %0:vrm8, 7, %2:gprnox0, %3:gprnox0, %4:gprnox0, 4, 2, implicit $frm + PseudoRET +... +--- +name: interleave_rvv_and_xsfmm +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: vrm8 } + - { id: 1, class: gprnox0 } + - { id: 2, class: gpr } + - { id: 3, class: gpr } + - { id: 4, class: vrm8 } + - { id: 5, class: vrm8 } +liveins: + - { reg: '$v8m8', virtual-reg: '%0' } + - { reg: '$x10', virtual-reg: '%1' } + - { reg: '$x11', virtual-reg: '%2' } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: {} +body: | + bb.0.entry: + liveins: $v8m8, $x10, $x11 + ; CHECK-LABEL: name: interleave_rvv_and_xsfmm + ; CHECK: liveins: $v8m8, $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x10 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrm8 = COPY $v8m8 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1 + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 512, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: [[PseudoSF_VTMV_V_T:%[0-9]+]]:vrm8 = PseudoSF_VTMV_V_T [[ADDI]], $noreg, 3, 1, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY1]], 195 /* e8, m8, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: [[PseudoVADD_VV_M8_:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 $noreg, [[COPY2]], [[PseudoSF_VTMV_V_T]], $noreg, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 520, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: PseudoSF_VSTE16 [[ADDI]], [[COPY]], $noreg, 4, 1, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v8m8 = COPY [[PseudoVADD_VV_M8_]], implicit $vtype + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %2:gpr = COPY $x11 + %1:gprnox0 = COPY $x10 + %0:vrm8 = COPY $v8m8 + %3:gpr = ADDI $x0, 1 + %4:vrm8 = PseudoSF_VTMV_V_T %3:gpr, %1:gprnox0, 3, 1 + %5:vrm8 = PseudoVADD_VV_M8 $noreg, %0:vrm8, killed %4:vrm8, %1:gprnox0, 3, 0 + PseudoSF_VSTE16 %3:gpr, %2:gpr, %1:gprnox0, 4, 1 + $v8m8 = COPY %5:vrm8 + PseudoRET implicit $v8m8 +... +--- +name: interleave_rvv_and_xsfmm2 +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: vrm8 } + - { id: 1, class: gprnox0 } + - { id: 2, class: gpr } + - { id: 3, class: gpr } + - { id: 4, class: vrm8 } + - { id: 5, class: vrm8 } +liveins: + - { reg: '$v8m8', virtual-reg: '%0' } + - { reg: '$x10', virtual-reg: '%1' } + - { reg: '$x11', virtual-reg: '%2' } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: {} +body: | + bb.0.entry: + liveins: $v8m8, $x10, $x11 + ; CHECK-LABEL: name: interleave_rvv_and_xsfmm2 + ; CHECK: liveins: $v8m8, $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x10 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrm8 = COPY $v8m8 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1 + ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY1]], 195 /* e8, m8, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: [[PseudoVADD_VV_M8_:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 $noreg, [[COPY2]], [[COPY2]], $noreg, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 512, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: dead [[PseudoSF_VTMV_V_T:%[0-9]+]]:vrm8 = PseudoSF_VTMV_V_T [[ADDI]], $noreg, 3, 1, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY1]], 195 /* e8, m8, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: [[PseudoVADD_VV_M8_1:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 $noreg, [[PseudoVADD_VV_M8_]], [[PseudoVADD_VV_M8_]], $noreg, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 520, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: PseudoSF_VSTE16 [[ADDI]], [[COPY]], $noreg, 4, 1, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v8m8 = COPY [[PseudoVADD_VV_M8_1]], implicit $vtype + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %2:gpr = COPY $x11 + %1:gprnox0 = COPY $x10 + %0:vrm8 = COPY $v8m8 + %3:gpr = ADDI $x0, 1 + %4:vrm8 = PseudoVADD_VV_M8 $noreg, %0:vrm8, killed %0:vrm8, %1:gprnox0, 3, 0 + %5:vrm8 = PseudoSF_VTMV_V_T %3:gpr, %1:gprnox0, 3, 1 + %6:vrm8 = PseudoVADD_VV_M8 $noreg, %4:vrm8, killed %4:vrm8, %1:gprnox0, 3, 0 + PseudoSF_VSTE16 %3:gpr, %2:gpr, %1:gprnox0, 4, 1 + $v8m8 = COPY %6:vrm8 + PseudoRET implicit $v8m8 +... +--- +name: consecutive_xsfmm +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: vrm8 } + - { id: 1, class: gprnox0 } + - { id: 2, class: gprnox0 } + - { id: 3, class: gprnox0 } + - { id: 4, class: gprnox0 } +liveins: + - { reg: '$v8m8', virtual-reg: '%0' } + - { reg: '$x10', virtual-reg: '%1' } + - { reg: '$x11', virtual-reg: '%2' } + - { reg: '$x12', virtual-reg: '%3' } + - { reg: '$x13', virtual-reg: '%4' } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: {} +body: | + bb.0.entry: + liveins: $v8m8, $x10, $x11, $x12, $x13 + ; CHECK-LABEL: name: consecutive_xsfmm + ; CHECK: liveins: $v8m8, $x10, $x11, $x12, $x13 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x10 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gprnox0 = COPY $x11 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gprnox0 = COPY $x12 + ; CHECK-NEXT: dead [[COPY4:%[0-9]+]]:gprnox0 = COPY $x13 + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY2]], 1032, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY1]], 4, 2, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY3]], 4, 2, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY]], [[COPY]], 7, $noreg, $noreg, $noreg, 4, 2, implicit $frm, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY3]], 520, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: PseudoSF_VSTE16 [[COPY1]], [[COPY2]], $noreg, 4, 1, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoRET + %0:vrm8 = COPY $v8m8 + %1:gprnox0 = COPY $x10 + %2:gprnox0 = COPY $x11 + %3:gprnox0 = COPY $x12 + %4:gprnox0 = COPY $x13 + PseudoSF_MM_F_F $t2, %0:vrm8, %0:vrm8, 7, %1:gprnox0, %2:gprnox0, %3:gprnox0, 4, 2, implicit $frm + PseudoSF_VSTE16 %1:gprnox0, %2:gprnox0, %3:gprnox0, 4, 1 + PseudoRET +... +--- +name: vsettnt_max +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: gprnox0 } +liveins: + - { reg: '$x10', virtual-reg: '%0' } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: {} +body: | + bb.0.entry: + liveins: $x10 + ; CHECK-LABEL: name: vsettnt_max + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10 + ; CHECK-NEXT: dead [[PseudoSF_VSETTNTX0_:%[0-9]+]]:gpr = PseudoSF_VSETTNTX0 killed $x0, 520, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: dead [[PseudoSF_VSETTK:%[0-9]+]]:gprnox0 = PseudoSF_VSETTK [[COPY]], 4, 1, implicit-def $vtype, implicit $vtype, implicit $vtype + ; CHECK-NEXT: dead [[PseudoSF_VSETTNTX0_1:%[0-9]+]]:gprnox0 = PseudoSF_VSETTNTX0 $x0, 520, implicit-def $vl, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: [[PseudoSF_VSETTM:%[0-9]+]]:gprnox0 = PseudoSF_VSETTM [[COPY]], 4, 1, implicit-def $vtype, implicit $vtype, implicit $vtype + ; CHECK-NEXT: $x10 = COPY [[PseudoSF_VSETTM]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprnox0 = COPY $x10 + %1:gprnox0 = PseudoSF_VSETTK %0:gprnox0, 4, 1, implicit-def $vtype, implicit $vtype + %2:gprnox0 = PseudoSF_VSETTNTX0 $x0, 520, implicit-def $vl, implicit-def $vtype, implicit $vtype + %3:gprnox0 = PseudoSF_VSETTM %0:gprnox0, 4, 1, implicit-def $vtype, implicit $vtype + $x10 = COPY %3:gprnox0 + PseudoRET implicit $x10 +... +--- +name: single_vsettm +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: gprnox0 } +liveins: + - { reg: '$x10', virtual-reg: '%0' } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: {} +body: | + bb.0.entry: + liveins: $x10 + ; CHECK-LABEL: name: single_vsettm + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10 + ; CHECK-NEXT: dead [[PseudoSF_VSETTNTX0_:%[0-9]+]]:gpr = PseudoSF_VSETTNTX0 killed $x0, 520, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: [[PseudoSF_VSETTM:%[0-9]+]]:gprnox0 = PseudoSF_VSETTM [[COPY]], 4, 1, implicit-def $vtype, implicit $vtype, implicit $vtype + ; CHECK-NEXT: $x10 = COPY [[PseudoSF_VSETTM]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprnox0 = COPY $x10 + %1:gprnox0 = PseudoSF_VSETTM %0:gprnox0, 4, 1, implicit-def $vtype, implicit $vtype + $x10 = COPY %1:gprnox0 + PseudoRET implicit $x10 +... +--- +name: single_vsettn +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: gprnox0 } +liveins: + - { reg: '$x10', virtual-reg: '%0' } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: {} +body: | + bb.0.entry: + liveins: $x10 + ; CHECK-LABEL: name: single_vsettn + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10 + ; CHECK-NEXT: [[PseudoSF_VSETTNT:%[0-9]+]]:gprnox0 = PseudoSF_VSETTNT [[COPY]], 520, implicit-def $vl, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: $x10 = COPY [[PseudoSF_VSETTNT]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprnox0 = COPY $x10 + %1:gprnox0 = PseudoSF_VSETTNT %0:gprnox0, 520, implicit-def $vl, implicit-def $vtype, implicit $vtype + $x10 = COPY %1:gprnox0 + PseudoRET implicit $x10 +... +--- +name: single_vsettk +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: gprnox0 } +liveins: + - { reg: '$x10', virtual-reg: '%0' } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: {} +body: | + bb.0.entry: + liveins: $x10 + ; CHECK-LABEL: name: single_vsettk + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10 + ; CHECK-NEXT: dead [[PseudoSF_VSETTNTX0_:%[0-9]+]]:gpr = PseudoSF_VSETTNTX0 killed $x0, 520, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: [[PseudoSF_VSETTK:%[0-9]+]]:gprnox0 = PseudoSF_VSETTK [[COPY]], 4, 1, implicit-def $vtype, implicit $vtype, implicit $vtype + ; CHECK-NEXT: $x10 = COPY [[PseudoSF_VSETTK]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprnox0 = COPY $x10 + %1:gprnox0 = PseudoSF_VSETTK %0:gprnox0, 4, 1, implicit-def $vtype, implicit $vtype + $x10 = COPY %1:gprnox0 + PseudoRET implicit $x10 +... +--- +name: sf_vtzero +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: gprnox0 } + - { id: 1, class: gprnox0 } +liveins: + - { reg: '$x10', virtual-reg: '%0' } + - { reg: '$x11', virtual-reg: '%1' } +frameInfo: + maxAlignment: 1 +machineFunctionInfo: {} +body: | + bb.0.entry: + liveins: $x10, $x11 + ; CHECK-LABEL: name: sf_vtzero + ; CHECK: liveins: $x10, $x11 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x11 + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1536, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY]], 3, 3, implicit-def $vtype, implicit $vtype + ; CHECK-NEXT: PseudoSF_VTZERO_T $t1, $noreg, $noreg, 3, 4, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoRET + %0:gprnox0 = COPY $x10 + %1:gprnox0 = COPY $x11 + PseudoSF_VTZERO_T $t1, %0:gprnox0, %1:gprnox0, 3, 4 + PseudoRET +... From a07ace7bedfd881f53e3453e98e2ee0961b50ac6 Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Thu, 5 Jun 2025 02:12:05 -0700 Subject: [PATCH 2/3] [RISCV] Support XSfmm LLVM IR and CodeGen Co-authored-by: Piyou Chen --- llvm/include/llvm/IR/IntrinsicsRISCVXsf.td | 95 +++++++++ llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp | 6 + llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 182 ++++++++++++++++++ llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h | 1 + llvm/lib/Target/RISCV/RISCVInstrInfoXSfmm.td | 51 +++++ .../CodeGen/RISCV/rvv/sifive-O0-ATM-ATK.ll | 18 ++ .../RISCV/rvv/sifive_sf_mm_e4m3_e4m3.ll | 20 ++ .../RISCV/rvv/sifive_sf_mm_e4m3_e5m2.ll | 20 ++ .../RISCV/rvv/sifive_sf_mm_e5m2_e4m3.ll | 20 ++ .../RISCV/rvv/sifive_sf_mm_e5m2_e5m2.ll | 20 ++ .../CodeGen/RISCV/rvv/sifive_sf_mm_f_f.ll | 52 +++++ .../CodeGen/RISCV/rvv/sifive_sf_mm_s_s.ll | 20 ++ .../CodeGen/RISCV/rvv/sifive_sf_mm_s_u.ll | 20 ++ .../CodeGen/RISCV/rvv/sifive_sf_mm_u_s.ll | 20 ++ .../CodeGen/RISCV/rvv/sifive_sf_mm_u_u.ll | 20 ++ .../CodeGen/RISCV/rvv/sifive_sf_vlte16.ll | 23 +++ .../CodeGen/RISCV/rvv/sifive_sf_vlte32.ll | 23 +++ .../CodeGen/RISCV/rvv/sifive_sf_vlte64.ll | 23 +++ .../test/CodeGen/RISCV/rvv/sifive_sf_vlte8.ll | 23 +++ .../CodeGen/RISCV/rvv/sifive_sf_vsettk.ll | 23 +++ .../CodeGen/RISCV/rvv/sifive_sf_vsettm.ll | 23 +++ .../CodeGen/RISCV/rvv/sifive_sf_vsettnt.ll | 72 +++++++ .../CodeGen/RISCV/rvv/sifive_sf_vste16.ll | 23 +++ .../CodeGen/RISCV/rvv/sifive_sf_vste32.ll | 23 +++ .../CodeGen/RISCV/rvv/sifive_sf_vste64.ll | 23 +++ .../test/CodeGen/RISCV/rvv/sifive_sf_vste8.ll | 23 +++ .../CodeGen/RISCV/rvv/sifive_sf_vtdiscard.ll | 22 +++ .../CodeGen/RISCV/rvv/sifive_sf_vtmv_t_v.ll | 114 +++++++++++ .../CodeGen/RISCV/rvv/sifive_sf_vtmv_v_t.ll | 114 +++++++++++ .../CodeGen/RISCV/rvv/sifive_sf_vtzero_t.ll | 24 +++ 30 files changed, 1141 insertions(+) create mode 100644 llvm/test/CodeGen/RISCV/rvv/sifive-O0-ATM-ATK.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_e4m3_e4m3.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_e4m3_e5m2.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_e5m2_e4m3.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_e5m2_e5m2.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_f_f.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_s_s.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_s_u.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_u_s.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_u_u.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/sifive_sf_vlte16.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/sifive_sf_vlte32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/sifive_sf_vlte64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/sifive_sf_vlte8.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/sifive_sf_vsettk.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/sifive_sf_vsettm.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/sifive_sf_vsettnt.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/sifive_sf_vste16.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/sifive_sf_vste32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/sifive_sf_vste64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/sifive_sf_vste8.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/sifive_sf_vtdiscard.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/sifive_sf_vtmv_t_v.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/sifive_sf_vtmv_v_t.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/sifive_sf_vtzero_t.ll diff --git a/llvm/include/llvm/IR/IntrinsicsRISCVXsf.td b/llvm/include/llvm/IR/IntrinsicsRISCVXsf.td index bf20080229aa4..1942423ae5bea 100644 --- a/llvm/include/llvm/IR/IntrinsicsRISCVXsf.td +++ b/llvm/include/llvm/IR/IntrinsicsRISCVXsf.td @@ -180,4 +180,99 @@ let TargetPrefix = "riscv" in { // XSfvfnrclipxfqf defm int_riscv_sf_vfnrclip_x_f_qf : RISCVSFCustomVFNRCLIP; defm int_riscv_sf_vfnrclip_xu_f_qf : RISCVSFCustomVFNRCLIP; + + // XSfmm + // Output: (output_len) + // Input: (input_len, vsew, twiden) + class RISCVSFVSet + : DefaultAttrsIntrinsic<[llvm_anyint_ty], + [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], + [ImmArg>, ImmArg>, IntrNoMem]>; + + // Input: (tss, base, tn) + // IntrReadMem, IntrHasSideEffects does not work for pattern matching. + class RISCVSFTileLoad + : DefaultAttrsIntrinsic<[], + [llvm_anyint_ty, llvm_ptr_ty, LLVMMatchType<0>], + [NoCapture>]>, + RISCVVIntrinsic; + + // Input: (tss, base, tn) + class RISCVSFTileStore + : DefaultAttrsIntrinsic<[], + [llvm_anyint_ty, llvm_ptr_ty, LLVMMatchType<0>], + [NoCapture>, IntrWriteMem, + IntrHasSideEffects]>, + RISCVVIntrinsic; + + // Output: () + // Input: (mtd, mat1, mat2, tm, tn, tk, twiden) + class RISCVSFCustomMatMul + : DefaultAttrsIntrinsic<[], [llvm_anyint_ty, llvm_anyvector_ty, + !if(is_float, LLVMMatchType<1>, + llvm_anyvector_ty), + LLVMMatchType<0>, LLVMMatchType<0>, + LLVMMatchType<0>, LLVMMatchType<0>], + [IntrNoMem, IntrHasSideEffects, + ImmArg>, ImmArg>]>, + RISCVVIntrinsic; + + def int_riscv_sf_vsettnt : RISCVSFVSet; + def int_riscv_sf_vsettm : RISCVSFVSet; + def int_riscv_sf_vsettk : RISCVSFVSet; + + def int_riscv_sf_vlte8 : RISCVSFTileLoad; + def int_riscv_sf_vlte16 : RISCVSFTileLoad; + def int_riscv_sf_vlte32 : RISCVSFTileLoad; + def int_riscv_sf_vlte64 : RISCVSFTileLoad; + def int_riscv_sf_vste8 : RISCVSFTileStore; + def int_riscv_sf_vste16 : RISCVSFTileStore; + def int_riscv_sf_vste32 : RISCVSFTileStore; + def int_riscv_sf_vste64 : RISCVSFTileStore; + + // Output: (vd) + // Input: (tss, tn) + def int_riscv_sf_vtmv_v_t + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], + [llvm_anyint_ty, LLVMMatchType<1>], + [IntrNoMem, IntrHasSideEffects]>, + RISCVVIntrinsic { + let VLOperand = 2; + } + // Output: () + // Input: (tss, vs2, tn) + def int_riscv_sf_vtmv_t_v + : DefaultAttrsIntrinsic<[], [LLVMMatchType<1>, llvm_anyvector_ty, + llvm_anyint_ty], [IntrNoMem, IntrHasSideEffects]>, + RISCVVIntrinsic { + let VLOperand = 2; + } + + foreach a = ["u", "s"] in { + foreach b = ["u", "s"] in { + def int_riscv_sf_mm_ # a # _ # b : RISCVSFCustomMatMul; + } + } + + def int_riscv_sf_mm_f_f : RISCVSFCustomMatMul; + foreach e1 = [5, 4] in + foreach e2 = [5, 4] in + def int_riscv_sf_mm_e # e1 # m # !sub(7, e1) # _e # e2 # m # !sub(7, e2) + : RISCVSFCustomMatMul; + + // Output: () + // Input: (mtd) + def int_riscv_sf_vtzero_t + : DefaultAttrsIntrinsic<[], + [llvm_anyint_ty, LLVMMatchType<0>,LLVMMatchType<0>, + LLVMMatchType<0>, LLVMMatchType<0>], + [ImmArg>, ImmArg>, + ImmArg>, IntrNoMem, IntrHasSideEffects]>, + RISCVVIntrinsic; + + // Output: () + // Input: () + def int_riscv_sf_vtdiscard + : DefaultAttrsIntrinsic<[], [], [IntrNoMem, IntrHasSideEffects]>, + RISCVVIntrinsic; } // TargetPrefix = "riscv" diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp index 72f1596d79a02..534c330463085 100644 --- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp +++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp @@ -1100,6 +1100,12 @@ static bool lowerRISCVVMachineInstrToMCInst(const MachineInstr *MI, --NumOps; if (RISCVII::hasRoundModeOp(TSFlags)) --NumOps; + if (RISCVII::hasTWidenOp(TSFlags)) + --NumOps; + if (RISCVII::hasTMOp(TSFlags)) + --NumOps; + if (RISCVII::hasTKOp(TSFlags)) + --NumOps; bool hasVLOutput = RISCV::isFaultFirstLoad(*MI); for (unsigned OpNo = 0; OpNo != NumOps; ++OpNo) { diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp index 494d6ed03292a..d44eee21e0f9e 100644 --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp @@ -522,6 +522,43 @@ void RISCVDAGToDAGISel::selectVSETVLI(SDNode *Node) { CurDAG->getMachineNode(Opcode, DL, XLenVT, VLOperand, VTypeIOp)); } +void RISCVDAGToDAGISel::selectXSfmmVSET(SDNode *Node) { + if (!Subtarget->hasVendorXSfmmbase()) + return; + + assert(Node->getOpcode() == ISD::INTRINSIC_WO_CHAIN && "Unexpected opcode"); + + SDLoc DL(Node); + MVT XLenVT = Subtarget->getXLenVT(); + + unsigned IntNo = Node->getConstantOperandVal(0); + + assert((IntNo == Intrinsic::riscv_sf_vsettnt || + IntNo == Intrinsic::riscv_sf_vsettm || + IntNo == Intrinsic::riscv_sf_vsettk) && + "Unexpected XSfmm vset intrinsic"); + + unsigned SEW = RISCVVType::decodeVSEW(Node->getConstantOperandVal(2)); + unsigned Widen = RISCVVType::decodeTWiden(Node->getConstantOperandVal(3)); + unsigned PseudoOpCode = + IntNo == Intrinsic::riscv_sf_vsettnt ? RISCV::PseudoSF_VSETTNT + : IntNo == Intrinsic::riscv_sf_vsettm ? RISCV::PseudoSF_VSETTM + : RISCV::PseudoSF_VSETTK; + + unsigned VTypeI = RISCVVType::encodeXSfmmVType(SEW, Widen, 0); + SDValue VTypeIOp = CurDAG->getTargetConstant(VTypeI, DL, XLenVT); + SDValue Log2SEW = CurDAG->getTargetConstant(Log2_32(SEW), DL, XLenVT); + SDValue TWiden = CurDAG->getTargetConstant(Widen, DL, XLenVT); + + if (IntNo == Intrinsic::riscv_sf_vsettnt) + ReplaceNode(Node, CurDAG->getMachineNode(PseudoOpCode, DL, XLenVT, + Node->getOperand(1), VTypeIOp)); + else + ReplaceNode(Node, + CurDAG->getMachineNode(PseudoOpCode, DL, XLenVT, + Node->getOperand(1), Log2SEW, TWiden)); +} + bool RISCVDAGToDAGISel::tryShrinkShlLogicImm(SDNode *Node) { MVT VT = Node->getSimpleValueType(0); unsigned Opcode = Node->getOpcode(); @@ -777,6 +814,11 @@ bool RISCVDAGToDAGISel::tryIndexedLoad(SDNode *Node) { return true; } +static Register getTileReg(uint64_t TileNum) { + assert(TileNum <= 15 && "Invalid tile number"); + return RISCV::T0 + TileNum; +} + void RISCVDAGToDAGISel::selectSF_VC_X_SE(SDNode *Node) { if (!Subtarget->hasVInstructions()) return; @@ -1955,6 +1997,10 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) { case Intrinsic::riscv_vsetvli: case Intrinsic::riscv_vsetvlimax: return selectVSETVLI(Node); + case Intrinsic::riscv_sf_vsettnt: + case Intrinsic::riscv_sf_vsettm: + case Intrinsic::riscv_sf_vsettk: + return selectXSfmmVSET(Node); } break; } @@ -2352,6 +2398,142 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) { case Intrinsic::riscv_sf_vc_i_se: selectSF_VC_X_SE(Node); return; + case Intrinsic::riscv_sf_vlte8: + case Intrinsic::riscv_sf_vlte16: + case Intrinsic::riscv_sf_vlte32: + case Intrinsic::riscv_sf_vlte64: { + unsigned Log2SEW; + unsigned PseudoInst; + switch (IntNo) { + case Intrinsic::riscv_sf_vlte8: + PseudoInst = RISCV::PseudoSF_VLTE8; + Log2SEW = 3; + break; + case Intrinsic::riscv_sf_vlte16: + PseudoInst = RISCV::PseudoSF_VLTE16; + Log2SEW = 4; + break; + case Intrinsic::riscv_sf_vlte32: + PseudoInst = RISCV::PseudoSF_VLTE32; + Log2SEW = 5; + break; + case Intrinsic::riscv_sf_vlte64: + PseudoInst = RISCV::PseudoSF_VLTE64; + Log2SEW = 6; + break; + } + + SDValue SEWOp = CurDAG->getTargetConstant(Log2SEW, DL, XLenVT); + SDValue TWidenOp = CurDAG->getTargetConstant(1, DL, XLenVT); + SmallVector Operands = {Node->getOperand(2), + Node->getOperand(3), + Node->getOperand(4), + SEWOp, + TWidenOp, + Node->getOperand(0)}; + + MachineSDNode *TileLoad = + CurDAG->getMachineNode(PseudoInst, DL, Node->getVTList(), Operands); + if (auto *MemOp = dyn_cast(Node)) + CurDAG->setNodeMemRefs(TileLoad, {MemOp->getMemOperand()}); + + ReplaceNode(Node, TileLoad); + return; + } + case Intrinsic::riscv_sf_mm_s_s: + case Intrinsic::riscv_sf_mm_s_u: + case Intrinsic::riscv_sf_mm_u_s: + case Intrinsic::riscv_sf_mm_u_u: + case Intrinsic::riscv_sf_mm_e5m2_e5m2: + case Intrinsic::riscv_sf_mm_e5m2_e4m3: + case Intrinsic::riscv_sf_mm_e4m3_e5m2: + case Intrinsic::riscv_sf_mm_e4m3_e4m3: + case Intrinsic::riscv_sf_mm_f_f: { + bool HasFRM = false; + unsigned PseudoInst; + switch (IntNo) { + case Intrinsic::riscv_sf_mm_s_s: + PseudoInst = RISCV::PseudoSF_MM_S_S; + break; + case Intrinsic::riscv_sf_mm_s_u: + PseudoInst = RISCV::PseudoSF_MM_S_U; + break; + case Intrinsic::riscv_sf_mm_u_s: + PseudoInst = RISCV::PseudoSF_MM_U_S; + break; + case Intrinsic::riscv_sf_mm_u_u: + PseudoInst = RISCV::PseudoSF_MM_U_U; + break; + case Intrinsic::riscv_sf_mm_e5m2_e5m2: + PseudoInst = RISCV::PseudoSF_MM_E5M2_E5M2; + HasFRM = true; + break; + case Intrinsic::riscv_sf_mm_e5m2_e4m3: + PseudoInst = RISCV::PseudoSF_MM_E5M2_E4M3; + HasFRM = true; + break; + case Intrinsic::riscv_sf_mm_e4m3_e5m2: + PseudoInst = RISCV::PseudoSF_MM_E4M3_E5M2; + HasFRM = true; + break; + case Intrinsic::riscv_sf_mm_e4m3_e4m3: + PseudoInst = RISCV::PseudoSF_MM_E4M3_E4M3; + HasFRM = true; + break; + case Intrinsic::riscv_sf_mm_f_f: + if (Node->getOperand(3).getValueType().getScalarType() == MVT::bf16) + PseudoInst = RISCV::PseudoSF_MM_F_F_ALT; + else + PseudoInst = RISCV::PseudoSF_MM_F_F; + HasFRM = true; + break; + } + uint64_t TileNum = Node->getConstantOperandVal(2); + SDValue Op1 = Node->getOperand(3); + SDValue Op2 = Node->getOperand(4); + MVT VT = Op1->getSimpleValueType(0); + unsigned Log2SEW = Log2_32(VT.getScalarSizeInBits()); + SDValue TmOp = Node->getOperand(5); + SDValue TnOp = Node->getOperand(6); + SDValue TkOp = Node->getOperand(7); + SDValue TWidenOp = Node->getOperand(8); + SDValue Chain = Node->getOperand(0); + + // sf.mm.f.f with sew=32, twiden=2 is invalid + if (IntNo == Intrinsic::riscv_sf_mm_f_f && Log2SEW == 5 && + TWidenOp->getAsZExtVal() == 2) + report_fatal_error("sf.mm.f.f doesn't support (sew=32, twiden=2)"); + + SmallVector Operands( + {CurDAG->getRegister(getTileReg(TileNum), XLenVT), Op1, Op2}); + if (HasFRM) + Operands.push_back( + CurDAG->getTargetConstant(RISCVFPRndMode::DYN, DL, XLenVT)); + Operands.append({TmOp, TnOp, TkOp, + CurDAG->getTargetConstant(Log2SEW, DL, XLenVT), TWidenOp, + Chain}); + + auto *NewNode = + CurDAG->getMachineNode(PseudoInst, DL, Node->getVTList(), Operands); + + ReplaceNode(Node, NewNode); + return; + } + case Intrinsic::riscv_sf_vtzero_t: { + uint64_t TileNum = Node->getConstantOperandVal(2); + SDValue Tm = Node->getOperand(3); + SDValue Tn = Node->getOperand(4); + SDValue Log2SEW = Node->getOperand(5); + SDValue TWiden = Node->getOperand(6); + SDValue Chain = Node->getOperand(0); + auto *NewNode = CurDAG->getMachineNode( + RISCV::PseudoSF_VTZERO_T, DL, Node->getVTList(), + {CurDAG->getRegister(getTileReg(TileNum), XLenVT), Tm, Tn, Log2SEW, + TWiden, Chain}); + + ReplaceNode(Node, NewNode); + return; + } } break; } diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h index f199c2031b9a9..ce40075ff6d7b 100644 --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h @@ -164,6 +164,7 @@ class RISCVDAGToDAGISel : public SelectionDAGISel { void selectVSXSEG(SDNode *Node, unsigned NF, bool IsMasked, bool IsOrdered); void selectVSETVLI(SDNode *Node); + void selectXSfmmVSET(SDNode *Node); void selectSF_VC_X_SE(SDNode *Node); diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXSfmm.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXSfmm.td index 750cd89fb5eb8..fd54d17770961 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXSfmm.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXSfmm.td @@ -410,3 +410,54 @@ let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in { : Pseudo<(outs), (ins TR:$rd, AVL:$atm, AVL:$atn, ixlenimm:$sew, ixlenimm:$twiden), []>, RISCVVPseudo; def PseudoSF_VTDISCARD : Pseudo<(outs), (ins), []>, RISCVVPseudo; } + +class VPatXSfmmTileStore : + Pat<(!cast(intrinsic_name) + (XLenVT GPR:$rs2), + (XLenVT GPR:$rs1), + (XLenVT AVL:$tn)), + (!cast(inst_name) + (XLenVT GPR:$rs2), + (XLenVT GPR:$rs1), + GPR:$tn, log2sew, 1)>; + +class VPatXSfmmTileMove_T_V : + Pat<(!cast(intrinsic_name) + (XLenVT GPR:$rs1), + (reg_type VRM8:$vs2), + (XLenVT AVL:$atn)), + (!cast(inst_name) + (XLenVT GPR:$rs1), + (reg_type VRM8:$vs2), + GPR:$atn, log2sew, 1)>; + +class VPatXSfmmTileMove_V_T : + Pat<(result_type (!cast(intrinsic_name) + (XLenVT GPR:$rs1), + (XLenVT AVL:$atn))), + (!cast(inst_name) + (XLenVT GPR:$rs1), + GPR:$atn, log2sew, 1)>; + +class VPatXSfmmVTDiscard : + Pat<(!cast(intrinsic_name)), + (!cast(inst_name))>; + +foreach eew = [8, 16, 32, 64] in + def : VPatXSfmmTileStore<"int_riscv_sf_vste" # eew, "PseudoSF_VSTE" # eew, !logtwo(eew)>; + +foreach vti = [VI8M8, VI16M8, VI32M8, VI64M8, VF16M8, VF32M8, VF64M8, VBF16M8] in { + def : VPatXSfmmTileMove_T_V<"int_riscv_sf_vtmv_t_v", "PseudoSF_VTMV_T_V", vti.Vector, vti.Log2SEW>; + def : VPatXSfmmTileMove_V_T<"int_riscv_sf_vtmv_v_t", "PseudoSF_VTMV_V_T", vti.Vector, vti.Log2SEW>; +} + +def : VPatXSfmmVTDiscard<"int_riscv_sf_vtdiscard", "PseudoSF_VTDISCARD">; diff --git a/llvm/test/CodeGen/RISCV/rvv/sifive-O0-ATM-ATK.ll b/llvm/test/CodeGen/RISCV/rvv/sifive-O0-ATM-ATK.ll new file mode 100644 index 0000000000000..d9a49a1b6b6ea --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/sifive-O0-ATM-ATK.ll @@ -0,0 +1,18 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv64 -mattr=+v -O0 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-RV64 + +define void @matmul() { +; CHECK-RV64-LABEL: matmul: +; CHECK-RV64: # %bb.0: # %entry +; CHECK-RV64-NEXT: li a0, 0 +; CHECK-RV64-NEXT: vsetvli zero, a0, 512 +; CHECK-RV64-NEXT: sf.vsettm zero, a0 +; CHECK-RV64-NEXT: sf.vtzero.t mt0 +; CHECK-RV64-NEXT: ret +entry: + call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 0, i64 0, i64 3, i64 1) + ret void +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn +declare void @llvm.riscv.sf.vtzero.t.i64(i64 immarg, i64, i64, i64 immarg, i64 immarg) #0 diff --git a/llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_e4m3_e4m3.ll b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_e4m3_e4m3.ll new file mode 100644 index 0000000000000..9b9a849cd7262 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_e4m3_e4m3.ll @@ -0,0 +1,20 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xsfmm32a8f \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xsfmm32a8f \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK + +declare void @llvm.riscv.sf.mm.e4m3.e4m3.iXLen.nxv64i8(iXLen, , , iXLen, iXLen, iXLen, iXLen) + +define void @test_sf_mm_e4m3_e4m3_w4_u8m8_u8m8(iXLen %mtd, %v1, %v2, iXLen %tm, iXLen %tn, iXLen %tk) { +; CHECK-LABEL: test_sf_mm_e4m3_e4m3_w4_u8m8_u8m8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt zero, a2, e8, w4 +; CHECK-NEXT: sf.vsettm zero, a1 +; CHECK-NEXT: sf.vsettk zero, a3 +; CHECK-NEXT: sf.mm.e4m3.e4m3 mt0, v8, v16 +; CHECK-NEXT: ret + entry: + call void @llvm.riscv.sf.mm.e4m3.e4m3.iXLen.nxv64i8(iXLen 0, %v1, %v2, iXLen %tm, iXLen %tn, iXLen %tk, iXLen 4) + ret void +} diff --git a/llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_e4m3_e5m2.ll b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_e4m3_e5m2.ll new file mode 100644 index 0000000000000..b63974f04a66e --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_e4m3_e5m2.ll @@ -0,0 +1,20 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xsfmm32a8f \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xsfmm32a8f \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK + +declare void @llvm.riscv.sf.mm.e4m3.e5m2.iXLen.nxv64i8(iXLen, , , iXLen, iXLen, iXLen, iXLen) + +define void @test_sf_mm_e4m3_e5m2_w4_u8m8_u8m8(iXLen %mtd, %v1, %v2, iXLen %tm, iXLen %tn, iXLen %tk) { +; CHECK-LABEL: test_sf_mm_e4m3_e5m2_w4_u8m8_u8m8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt zero, a2, e8, w4 +; CHECK-NEXT: sf.vsettm zero, a1 +; CHECK-NEXT: sf.vsettk zero, a3 +; CHECK-NEXT: sf.mm.e4m3.e5m2 mt0, v8, v16 +; CHECK-NEXT: ret + entry: + call void @llvm.riscv.sf.mm.e4m3.e5m2.iXLen.nxv64i8(iXLen 0, %v1, %v2, iXLen %tm, iXLen %tn, iXLen %tk, iXLen 4) + ret void +} diff --git a/llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_e5m2_e4m3.ll b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_e5m2_e4m3.ll new file mode 100644 index 0000000000000..62d629b1b1f1d --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_e5m2_e4m3.ll @@ -0,0 +1,20 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xsfmm32a8f \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xsfmm32a8f \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK + +declare void @llvm.riscv.sf.mm.e5m2.e4m3.iXLen.nxv64i8(iXLen, , , iXLen, iXLen, iXLen, iXLen) + +define void @test_sf_mm_e5m2_e5m2_w4_u8m8_u8m8(iXLen %mtd, %v1, %v2, iXLen %tm, iXLen %tn, iXLen %tk) { +; CHECK-LABEL: test_sf_mm_e5m2_e5m2_w4_u8m8_u8m8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt zero, a2, e8, w4 +; CHECK-NEXT: sf.vsettm zero, a1 +; CHECK-NEXT: sf.vsettk zero, a3 +; CHECK-NEXT: sf.mm.e5m2.e4m3 mt0, v8, v16 +; CHECK-NEXT: ret + entry: + call void @llvm.riscv.sf.mm.e5m2.e4m3.iXLen.nxv64i8(iXLen 0, %v1, %v2, iXLen %tm, iXLen %tn, iXLen %tk, iXLen 4) + ret void +} diff --git a/llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_e5m2_e5m2.ll b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_e5m2_e5m2.ll new file mode 100644 index 0000000000000..7a90c97bcf0be --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_e5m2_e5m2.ll @@ -0,0 +1,20 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xsfmm32a8f \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xsfmm32a8f \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK + +declare void @llvm.riscv.sf.mm.e5m2.e5m2.iXLen.nxv64i8(iXLen, , , iXLen, iXLen, iXLen, iXLen) + +define void @test_sf_mm_e4m3_e5m2_w4_u8m8_u8m8(iXLen %mtd, %v1, %v2, iXLen %tm, iXLen %tn, iXLen %tk) { +; CHECK-LABEL: test_sf_mm_e4m3_e5m2_w4_u8m8_u8m8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt zero, a2, e8, w4 +; CHECK-NEXT: sf.vsettm zero, a1 +; CHECK-NEXT: sf.vsettk zero, a3 +; CHECK-NEXT: sf.mm.e5m2.e5m2 mt0, v8, v16 +; CHECK-NEXT: ret + entry: + call void @llvm.riscv.sf.mm.e5m2.e5m2.iXLen.nxv64i8(iXLen 0, %v1, %v2, iXLen %tm, iXLen %tn, iXLen %tk, iXLen 4) + ret void +} diff --git a/llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_f_f.ll b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_f_f.ll new file mode 100644 index 0000000000000..29451c60b9248 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_f_f.ll @@ -0,0 +1,52 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \ +; RUN: -mattr=+zvfh -mattr=+xsfmm32a32f -mattr=+xsfmm64a64f \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \ +; RUN: -mattr=+zvfh -mattr=+xsfmm32a32f -mattr=+xsfmm64a64f \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK + +declare void @llvm.riscv.sf.mm.f.f.iXLen.nxv32f16(iXLen, , , iXLen, iXLen, iXLen, iXLen) + +define void @test_sf_mm_f_f_w2_f16m8(iXLen %mtd, %v1, %v2, iXLen %tm, iXLen %tn, iXLen %tk) { +; CHECK-LABEL: test_sf_mm_f_f_w2_f16m8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt zero, a2, e16, w2 +; CHECK-NEXT: sf.vsettm zero, a1 +; CHECK-NEXT: sf.vsettk zero, a3 +; CHECK-NEXT: sf.mm.f.f mt0, v8, v16 +; CHECK-NEXT: ret + entry: + call void @llvm.riscv.sf.mm.f.f.iXLen.nxv32f16(iXLen 0, %v1, %v2, iXLen %tm, iXLen %tn, iXLen %tk, iXLen 2) + ret void +} + +declare void @llvm.riscv.sf.mm.f.f.iXLen.nxv16f32(iXLen, , , iXLen, iXLen, iXLen, iXLen) + +define void @test_sf_mm_f_f_w1_f32m8(iXLen %mtd, %v1, %v2, iXLen %tm, iXLen %tn, iXLen %tk) { +; CHECK-LABEL: test_sf_mm_f_f_w1_f32m8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt zero, a2, e32, w1 +; CHECK-NEXT: sf.vsettm zero, a1 +; CHECK-NEXT: sf.vsettk zero, a3 +; CHECK-NEXT: sf.mm.f.f mt0, v8, v16 +; CHECK-NEXT: ret + entry: + call void @llvm.riscv.sf.mm.f.f.iXLen.nxv16f32(iXLen 0, %v1, %v2, iXLen %tm, iXLen %tn, iXLen %tk, iXLen 1) + ret void +} + +declare void @llvm.riscv.sf.mm.f.f.iXLen.nxv8f64(iXLen, , , iXLen, iXLen, iXLen, iXLen) + +define void @test_sf_mm_f_f_w1_f64m8(iXLen %mtd, %v1, %v2, iXLen %tm, iXLen %tn, iXLen %tk) { +; CHECK-LABEL: test_sf_mm_f_f_w1_f64m8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt zero, a2, e64, w1 +; CHECK-NEXT: sf.vsettm zero, a1 +; CHECK-NEXT: sf.vsettk zero, a3 +; CHECK-NEXT: sf.mm.f.f mt0, v8, v16 +; CHECK-NEXT: ret + entry: + call void @llvm.riscv.sf.mm.f.f.iXLen.nxv8f64(iXLen 0, %v1, %v2, iXLen %tm, iXLen %tn, iXLen %tk, iXLen 1) + ret void +} diff --git a/llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_s_s.ll b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_s_s.ll new file mode 100644 index 0000000000000..6a4b29ff0e786 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_s_s.ll @@ -0,0 +1,20 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xsfmm32a8i \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xsfmm32a8i \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK + +declare void @llvm.riscv.sf.mm.s.s.iXLen.nxv64i8.nxv64i8(iXLen, , , iXLen, iXLen, iXLen, iXLen) + +define void @test_sf_mm_s_s_w4_i8m8_i8m8(iXLen %mtd, %v1, %v2, iXLen %tm, iXLen %tn, iXLen %tk) { +; CHECK-LABEL: test_sf_mm_s_s_w4_i8m8_i8m8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt zero, a2, e8, w4 +; CHECK-NEXT: sf.vsettm zero, a1 +; CHECK-NEXT: sf.vsettk zero, a3 +; CHECK-NEXT: sf.mm.s.s mt0, v8, v16 +; CHECK-NEXT: ret + entry: + call void @llvm.riscv.sf.mm.s.s.iXLen.nxv64i8.nxv64i8(iXLen 0, %v1, %v2, iXLen %tm, iXLen %tn, iXLen %tk, iXLen 4) + ret void +} diff --git a/llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_s_u.ll b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_s_u.ll new file mode 100644 index 0000000000000..79239b01cd1d4 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_s_u.ll @@ -0,0 +1,20 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xsfmm32a8i \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xsfmm32a8i \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK + +declare void @llvm.riscv.sf.mm.s.u.iXLen.nxv64i8.nxv64i8(iXLen, , , iXLen, iXLen, iXLen, iXLen) + +define void @test_sf_mm_s_u_w4_i8m8_i8m8(iXLen %mtd, %v1, %v2, iXLen %tm, iXLen %tn, iXLen %tk) { +; CHECK-LABEL: test_sf_mm_s_u_w4_i8m8_i8m8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt zero, a2, e8, w4 +; CHECK-NEXT: sf.vsettm zero, a1 +; CHECK-NEXT: sf.vsettk zero, a3 +; CHECK-NEXT: sf.mm.s.u mt0, v8, v16 +; CHECK-NEXT: ret + entry: + call void @llvm.riscv.sf.mm.s.u.iXLen.nxv64i8.nxv64i8(iXLen 0, %v1, %v2, iXLen %tm, iXLen %tn, iXLen %tk, iXLen 4) + ret void +} diff --git a/llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_u_s.ll b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_u_s.ll new file mode 100644 index 0000000000000..b0d039bb194a4 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_u_s.ll @@ -0,0 +1,20 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xsfmm32a8i \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xsfmm32a8i \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK + +declare void @llvm.riscv.sf.mm.u.s.iXLen.nxv64i8.nxv64i8(iXLen, , , iXLen, iXLen, iXLen, iXLen) + +define void @test_sf_mm_u_s_w4_i8m8_i8m8(iXLen %mtd, %v1, %v2, iXLen %tm, iXLen %tn, iXLen %tk) { +; CHECK-LABEL: test_sf_mm_u_s_w4_i8m8_i8m8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt zero, a2, e8, w4 +; CHECK-NEXT: sf.vsettm zero, a1 +; CHECK-NEXT: sf.vsettk zero, a3 +; CHECK-NEXT: sf.mm.u.s mt0, v8, v16 +; CHECK-NEXT: ret + entry: + call void @llvm.riscv.sf.mm.u.s.iXLen.nxv64i8.nxv64i8(iXLen 0, %v1, %v2, iXLen %tm, iXLen %tn, iXLen %tk, iXLen 4) + ret void +} diff --git a/llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_u_u.ll b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_u_u.ll new file mode 100644 index 0000000000000..913c277655e43 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_u_u.ll @@ -0,0 +1,20 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xsfmm32a8i \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xsfmm32a8i \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK + +declare void @llvm.riscv.sf.mm.u.u.iXLen.nxv64i8.nxv64i8(iXLen, , , iXLen, iXLen, iXLen, iXLen) + +define void @test_sf_mm_u_u_w4_i8m8_i8m8(iXLen %mtd, %v1, %v2, iXLen %tm, iXLen %tn, iXLen %tk) { +; CHECK-LABEL: test_sf_mm_u_u_w4_i8m8_i8m8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt zero, a2, e8, w4 +; CHECK-NEXT: sf.vsettm zero, a1 +; CHECK-NEXT: sf.vsettk zero, a3 +; CHECK-NEXT: sf.mm.u.u mt0, v8, v16 +; CHECK-NEXT: ret + entry: + call void @llvm.riscv.sf.mm.u.u.iXLen.nxv64i8.nxv64i8(iXLen 0, %v1, %v2, iXLen %tm, iXLen %tn, iXLen %tk, iXLen 4) + ret void +} diff --git a/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vlte16.ll b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vlte16.ll new file mode 100644 index 0000000000000..8048dec110a5f --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vlte16.ll @@ -0,0 +1,23 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \ +; RUN: -mattr=+zvfh -mattr=+experimental-zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+xsfmm32a -mattr=+xsfmm32a8f -mattr=+xsfmm32a4i -mattr=+xsfmm64a64f \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \ +; RUN: -mattr=+zvfh -mattr=+experimental-zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+experimental-zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+xsfmm32a -mattr=+xsfmm32a8f -mattr=+xsfmm32a4i -mattr=+xsfmm64a64f \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK + +declare void @llvm.riscv.sf.vlte16.iXLen(iXLen, ptr, iXLen) + +define dso_local void @test_sf_vlte16(iXLen %tss, ptr %base, iXLen %vl) { +; CHECK-LABEL: test_sf_vlte16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt zero, a2, e16, w1 +; CHECK-NEXT: sf.vlte16 a0, (a1) +; CHECK-NEXT: ret + entry: + call void @llvm.riscv.sf.vlte16.iXLen(iXLen %tss, ptr %base, iXLen %vl) + ret void +} diff --git a/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vlte32.ll b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vlte32.ll new file mode 100644 index 0000000000000..a526dc8471b1a --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vlte32.ll @@ -0,0 +1,23 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \ +; RUN: -mattr=+zvfh -mattr=+experimental-zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+xsfmm32a -mattr=+xsfmm32a8f -mattr=+xsfmm32a4i -mattr=+xsfmm64a64f \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \ +; RUN: -mattr=+zvfh -mattr=+experimental-zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+experimental-zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+xsfmm32a -mattr=+xsfmm32a8f -mattr=+xsfmm32a4i -mattr=+xsfmm64a64f \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK + +declare void @llvm.riscv.sf.vlte32.iXLen(iXLen, ptr, iXLen) + +define dso_local void @test_sf_vlte32(iXLen %tss, ptr %base, iXLen %vl) { +; CHECK-LABEL: test_sf_vlte32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt zero, a2, e32, w1 +; CHECK-NEXT: sf.vlte32 a0, (a1) +; CHECK-NEXT: ret + entry: + call void @llvm.riscv.sf.vlte32.iXLen(iXLen %tss, ptr %base, iXLen %vl) + ret void +} diff --git a/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vlte64.ll b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vlte64.ll new file mode 100644 index 0000000000000..ed0c48ac467e6 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vlte64.ll @@ -0,0 +1,23 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \ +; RUN: -mattr=+zvfh -mattr=+experimental-zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+xsfmm32a -mattr=+xsfmm32a8f -mattr=+xsfmm32a4i -mattr=+xsfmm64a64f \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \ +; RUN: -mattr=+zvfh -mattr=+experimental-zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+experimental-zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+xsfmm32a -mattr=+xsfmm32a8f -mattr=+xsfmm32a4i -mattr=+xsfmm64a64f \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK + +declare void @llvm.riscv.sf.vlte64.iXLen(iXLen, ptr, iXLen) + +define dso_local void @test_sf_vlte64(iXLen %tss, ptr %base, iXLen %vl) { +; CHECK-LABEL: test_sf_vlte64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt zero, a2, e64, w1 +; CHECK-NEXT: sf.vlte64 a0, (a1) +; CHECK-NEXT: ret + entry: + call void @llvm.riscv.sf.vlte64.iXLen(iXLen %tss, ptr %base, iXLen %vl) + ret void +} diff --git a/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vlte8.ll b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vlte8.ll new file mode 100644 index 0000000000000..67b3ed2ec55ab --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vlte8.ll @@ -0,0 +1,23 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \ +; RUN: -mattr=+zvfh -mattr=+experimental-zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+xsfmm32a -mattr=+xsfmm32a8f -mattr=+xsfmm32a4i -mattr=+xsfmm64a64f \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \ +; RUN: -mattr=+zvfh -mattr=+experimental-zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+experimental-zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+xsfmm32a -mattr=+xsfmm32a8f -mattr=+xsfmm32a4i -mattr=+xsfmm64a64f \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK + +declare void @llvm.riscv.sf.vlte8.iXLen(iXLen, ptr, iXLen) + +define dso_local void @test_sf_vlte8(iXLen %tss, ptr %base, iXLen %vl) { +; CHECK-LABEL: test_sf_vlte8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt zero, a2, e8, w1 +; CHECK-NEXT: sf.vlte8 a0, (a1) +; CHECK-NEXT: ret + entry: + call void @llvm.riscv.sf.vlte8.iXLen(iXLen %tss, ptr %base, iXLen %vl) + ret void +} diff --git a/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vsettk.ll b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vsettk.ll new file mode 100644 index 0000000000000..4da37fad1b536 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vsettk.ll @@ -0,0 +1,23 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \ +; RUN: -mattr=+zvfh -mattr=+experimental-zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+xsfmm32a -mattr=+xsfmm32a8f -mattr=+xsfmm32a4i -mattr=+xsfmm64a64f \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \ +; RUN: -mattr=+zvfh -mattr=+experimental-zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+experimental-zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+xsfmm32a -mattr=+xsfmm32a8f -mattr=+xsfmm32a4i -mattr=+xsfmm64a64f \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK + +declare iXLen @llvm.riscv.sf.vsettk.iXLen(iXLen, iXLen, iXLen) + +define iXLen @test_sf_vsettk(iXLen %tk) { +; CHECK-LABEL: test_sf_vsettk: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt a1, zero, e16, w2 +; CHECK-NEXT: sf.vsettk a0, a0 +; CHECK-NEXT: ret + entry: + %0 = call iXLen @llvm.riscv.sf.vsettk.iXLen(iXLen %tk, iXLen 1, iXLen 2) + ret iXLen %0 +} diff --git a/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vsettm.ll b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vsettm.ll new file mode 100644 index 0000000000000..143c26cc8cff1 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vsettm.ll @@ -0,0 +1,23 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \ +; RUN: -mattr=+zvfh -mattr=+experimental-zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+xsfmm32a -mattr=+xsfmm32a8f -mattr=+xsfmm32a4i -mattr=+xsfmm64a64f \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \ +; RUN: -mattr=+zvfh -mattr=+experimental-zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+experimental-zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+xsfmm32a -mattr=+xsfmm32a8f -mattr=+xsfmm32a4i -mattr=+xsfmm64a64f \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK + +declare iXLen @llvm.riscv.sf.vsettm.iXLen(iXLen, iXLen, iXLen) + +define iXLen @test_sf_vsettm(iXLen %tm) { +; CHECK-LABEL: test_sf_vsettm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt a1, zero, e8, w4 +; CHECK-NEXT: sf.vsettm a0, a0 +; CHECK-NEXT: ret + entry: + %0 = call iXLen @llvm.riscv.sf.vsettm.iXLen(iXLen %tm, iXLen 0, iXLen 3) + ret iXLen %0 +} diff --git a/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vsettnt.ll b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vsettnt.ll new file mode 100644 index 0000000000000..48fa1bc8f6cbe --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vsettnt.ll @@ -0,0 +1,72 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \ +; RUN: -mattr=+zvfh -mattr=+experimental-zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+xsfmm32a -mattr=+xsfmm32a8f -mattr=+xsfmm32a4i -mattr=+xsfmm64a64f \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \ +; RUN: -mattr=+zvfh -mattr=+experimental-zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+experimental-zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+xsfmm32a -mattr=+xsfmm32a8f -mattr=+xsfmm32a4i -mattr=+xsfmm64a64f \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK + +declare iXLen @llvm.riscv.sf.vsettnt.iXLen(iXLen, iXLen, iXLen) + +define iXLen @test_sf_vsettnt_e8w1(iXLen %tn) { +; CHECK-LABEL: test_sf_vsettnt_e8w1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt a0, a0, e8, w1 +; CHECK-NEXT: ret + entry: + %0 = call iXLen @llvm.riscv.sf.vsettnt.iXLen(iXLen %tn, iXLen 0, iXLen 1) + ret iXLen %0 +} + +define iXLen @test_sf_vsettnt_e8w2(iXLen %tn) { +; CHECK-LABEL: test_sf_vsettnt_e8w2: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt a0, a0, e8, w2 +; CHECK-NEXT: ret + entry: + %0 = call iXLen @llvm.riscv.sf.vsettnt.iXLen(iXLen %tn, iXLen 0, iXLen 2) + ret iXLen %0 +} + +define iXLen @test_sf_vsettnt_e8w4(iXLen %tn) { +; CHECK-LABEL: test_sf_vsettnt_e8w4: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt a0, a0, e8, w4 +; CHECK-NEXT: ret + entry: + %0 = call iXLen @llvm.riscv.sf.vsettnt.iXLen(iXLen %tn, iXLen 0, iXLen 3) + ret iXLen %0 +} + +define iXLen @test_sf_vsettnt_e16w1(iXLen %tn) { +; CHECK-LABEL: test_sf_vsettnt_e16w1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt a0, a0, e16, w1 +; CHECK-NEXT: ret + entry: + %0 = call iXLen @llvm.riscv.sf.vsettnt.iXLen(iXLen %tn, iXLen 1, iXLen 1) + ret iXLen %0 +} + +define iXLen @test_sf_vsettnt_e16w2(iXLen %tn) { +; CHECK-LABEL: test_sf_vsettnt_e16w2: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt a0, a0, e16, w2 +; CHECK-NEXT: ret + entry: + %0 = call iXLen @llvm.riscv.sf.vsettnt.iXLen(iXLen %tn, iXLen 1, iXLen 2) + ret iXLen %0 +} + +define iXLen @test_sf_vsettnt_e16w4(iXLen %tn) { +; CHECK-LABEL: test_sf_vsettnt_e16w4: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt a0, a0, e16, w4 +; CHECK-NEXT: ret + entry: + %0 = call iXLen @llvm.riscv.sf.vsettnt.iXLen(iXLen %tn, iXLen 1, iXLen 3) + ret iXLen %0 +} diff --git a/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vste16.ll b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vste16.ll new file mode 100644 index 0000000000000..7a76151e01cc5 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vste16.ll @@ -0,0 +1,23 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \ +; RUN: -mattr=+zvfh -mattr=+experimental-zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+xsfmm32a -mattr=+xsfmm32a8f -mattr=+xsfmm32a4i -mattr=+xsfmm64a64f \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \ +; RUN: -mattr=+zvfh -mattr=+experimental-zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+experimental-zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+xsfmm32a -mattr=+xsfmm32a8f -mattr=+xsfmm32a4i -mattr=+xsfmm64a64f \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK + +declare void @llvm.riscv.sf.vste16.iXLen(iXLen, ptr, iXLen) + +define dso_local void @test_sf_vste16(iXLen %tss, ptr %base, iXLen %vl) { +; CHECK-LABEL: test_sf_vste16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt zero, a2, e16, w1 +; CHECK-NEXT: sf.vste16 a0, (a1) +; CHECK-NEXT: ret + entry: + call void @llvm.riscv.sf.vste16.iXLen(iXLen %tss, ptr %base, iXLen %vl) + ret void +} diff --git a/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vste32.ll b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vste32.ll new file mode 100644 index 0000000000000..8ff6e6af3b02d --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vste32.ll @@ -0,0 +1,23 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \ +; RUN: -mattr=+zvfh -mattr=+experimental-zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+xsfmm32a -mattr=+xsfmm32a8f -mattr=+xsfmm32a4i -mattr=+xsfmm64a64f \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \ +; RUN: -mattr=+zvfh -mattr=+experimental-zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+experimental-zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+xsfmm32a -mattr=+xsfmm32a8f -mattr=+xsfmm32a4i -mattr=+xsfmm64a64f \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK + +declare void @llvm.riscv.sf.vste32.iXLen(iXLen, ptr, iXLen) + +define dso_local void @test_sf_vste32(iXLen %tss, ptr %base, iXLen %vl) { +; CHECK-LABEL: test_sf_vste32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt zero, a2, e32, w1 +; CHECK-NEXT: sf.vste32 a0, (a1) +; CHECK-NEXT: ret + entry: + call void @llvm.riscv.sf.vste32.iXLen(iXLen %tss, ptr %base, iXLen %vl) + ret void +} diff --git a/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vste64.ll b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vste64.ll new file mode 100644 index 0000000000000..53990e4dd2483 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vste64.ll @@ -0,0 +1,23 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \ +; RUN: -mattr=+zvfh -mattr=+experimental-zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+xsfmm32a -mattr=+xsfmm32a8f -mattr=+xsfmm32a4i -mattr=+xsfmm64a64f \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \ +; RUN: -mattr=+zvfh -mattr=+experimental-zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+experimental-zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+xsfmm32a -mattr=+xsfmm32a8f -mattr=+xsfmm32a4i -mattr=+xsfmm64a64f \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK + +declare void @llvm.riscv.sf.vste64.iXLen(iXLen, ptr, iXLen) + +define dso_local void @test_sf_vste64(iXLen %tss, ptr %base, iXLen %vl) { +; CHECK-LABEL: test_sf_vste64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt zero, a2, e64, w1 +; CHECK-NEXT: sf.vste64 a0, (a1) +; CHECK-NEXT: ret + entry: + call void @llvm.riscv.sf.vste64.iXLen(iXLen %tss, ptr %base, iXLen %vl) + ret void +} diff --git a/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vste8.ll b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vste8.ll new file mode 100644 index 0000000000000..09b72594ac7c6 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vste8.ll @@ -0,0 +1,23 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \ +; RUN: -mattr=+zvfh -mattr=+experimental-zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+xsfmm32a -mattr=+xsfmm32a8f -mattr=+xsfmm32a4i -mattr=+xsfmm64a64f \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \ +; RUN: -mattr=+zvfh -mattr=+experimental-zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+experimental-zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+xsfmm32a -mattr=+xsfmm32a8f -mattr=+xsfmm32a4i -mattr=+xsfmm64a64f \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK + +declare void @llvm.riscv.sf.vste8.iXLen(iXLen, ptr, iXLen) + +define dso_local void @test_sf_vste8(iXLen %tss, ptr %base, iXLen %vl) { +; CHECK-LABEL: test_sf_vste8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt zero, a2, e8, w1 +; CHECK-NEXT: sf.vste8 a0, (a1) +; CHECK-NEXT: ret + entry: + call void @llvm.riscv.sf.vste8.iXLen(iXLen %tss, ptr %base, iXLen %vl) + ret void +} diff --git a/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vtdiscard.ll b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vtdiscard.ll new file mode 100644 index 0000000000000..394eb60f73743 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vtdiscard.ll @@ -0,0 +1,22 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \ +; RUN: -mattr=+zvfh -mattr=+experimental-zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+xsfmm32a -mattr=+xsfmm32a8f -mattr=+xsfmm32a4i -mattr=+xsfmm64a64f \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \ +; RUN: -mattr=+zvfh -mattr=+experimental-zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+experimental-zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+xsfmm32a -mattr=+xsfmm32a8f -mattr=+xsfmm32a4i -mattr=+xsfmm64a64f \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK + +declare void @llvm.riscv.sf.vtdiscard() + +define dso_local void @test_sf_vtdiscard() { +; CHECK-LABEL: test_sf_vtdiscard: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vtdiscard +; CHECK-NEXT: ret + entry: + call void @llvm.riscv.sf.vtdiscard() + ret void +} diff --git a/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vtmv_t_v.ll b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vtmv_t_v.ll new file mode 100644 index 0000000000000..66c9d26c209f0 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vtmv_t_v.ll @@ -0,0 +1,114 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \ +; RUN: -mattr=+zvfh -mattr=+zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+xsfmm32a -mattr=+xsfmm32a8f -mattr=+xsfmm32a4i -mattr=+xsfmm64a64f \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \ +; RUN: -mattr=+zvfh -mattr=+zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+xsfmm32a -mattr=+xsfmm32a8f -mattr=+xsfmm32a4i -mattr=+xsfmm64a64f \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK + +declare void @llvm.riscv.sf.vtmv.t.v.nxv32bf16.iXLen(iXLen, , iXLen) + +define void @test_sf_vtmv_t_v_bf16m8(iXLen %tss, %src, iXLen %vl) { +; CHECK-LABEL: test_sf_vtmv_t_v_bf16m8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt zero, a1, e16, w1 +; CHECK-NEXT: sf.vtmv.t.v a0, v8 +; CHECK-NEXT: ret + entry: + call void @llvm.riscv.sf.vtmv.t.v.nxv32bf16.iXLen(iXLen %tss, %src, iXLen %vl) + ret void +} + +declare void @llvm.riscv.sf.vtmv.t.v.nxv32f16.iXLen(iXLen, , iXLen) + +define void @test_sf_vtmv_t_v_f16(iXLen %tss, %src, iXLen %vl) { +; CHECK-LABEL: test_sf_vtmv_t_v_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt zero, a1, e16, w1 +; CHECK-NEXT: sf.vtmv.t.v a0, v8 +; CHECK-NEXT: ret + entry: + call void @llvm.riscv.sf.vtmv.t.v.nxv32f16.iXLen(iXLen %tss, %src, iXLen %vl) + ret void +} + +declare void @llvm.riscv.sf.vtmv.t.v.nxv16f32.iXLen(iXLen, , iXLen) + +define void @test_sf_vtmv_t_v_f32(iXLen %tss, %src, iXLen %vl) { +; CHECK-LABEL: test_sf_vtmv_t_v_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt zero, a1, e32, w1 +; CHECK-NEXT: sf.vtmv.t.v a0, v8 +; CHECK-NEXT: ret + entry: + call void @llvm.riscv.sf.vtmv.t.v.nxv16f32.iXLen(iXLen %tss, %src, iXLen %vl) + ret void +} + +declare void @llvm.riscv.sf.vtmv.t.v.nxv8f64.iXLen(iXLen, , iXLen) + +define void @test_sf_vtmv_t_v_f64(iXLen %tss, %src, iXLen %vl) { +; CHECK-LABEL: test_sf_vtmv_t_v_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt zero, a1, e64, w1 +; CHECK-NEXT: sf.vtmv.t.v a0, v8 +; CHECK-NEXT: ret + entry: + call void @llvm.riscv.sf.vtmv.t.v.nxv8f64.iXLen(iXLen %tss, %src, iXLen %vl) + ret void +} + +declare void @llvm.riscv.sf.vtmv.t.v.nxv64i8.iXLen(iXLen, , iXLen) + +define void @test_sf_vtmv_t_v_i8(iXLen %tss, %src, iXLen %vl) { +; CHECK-LABEL: test_sf_vtmv_t_v_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt zero, a1, e8, w1 +; CHECK-NEXT: sf.vtmv.t.v a0, v8 +; CHECK-NEXT: ret + entry: + call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.iXLen(iXLen %tss, %src, iXLen %vl) + ret void +} + +declare void @llvm.riscv.sf.vtmv.t.v.nxv32i16.iXLen(iXLen, , iXLen) + +define void @test_sf_vtmv_t_v_i16(iXLen %tss, %src, iXLen %vl) { +; CHECK-LABEL: test_sf_vtmv_t_v_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt zero, a1, e16, w1 +; CHECK-NEXT: sf.vtmv.t.v a0, v8 +; CHECK-NEXT: ret + entry: + call void @llvm.riscv.sf.vtmv.t.v.nxv32i16.iXLen(iXLen %tss, %src, iXLen %vl) + ret void +} + +declare void @llvm.riscv.sf.vtmv.t.v.nxv16i32.iXLen(iXLen, , iXLen) + +define void @test_sf_vtmv_t_v_i32(iXLen %tss, %src, iXLen %vl) { +; CHECK-LABEL: test_sf_vtmv_t_v_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt zero, a1, e32, w1 +; CHECK-NEXT: sf.vtmv.t.v a0, v8 +; CHECK-NEXT: ret + entry: + call void @llvm.riscv.sf.vtmv.t.v.nxv16i32.iXLen(iXLen %tss, %src, iXLen %vl) + ret void +} + +declare void @llvm.riscv.sf.vtmv.t.v.nxv8i64.iXLen(iXLen, , iXLen) + +define void @test_sf_vtmv_t_v_i64(iXLen %tss, %src, iXLen %vl) { +; CHECK-LABEL: test_sf_vtmv_t_v_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt zero, a1, e64, w1 +; CHECK-NEXT: sf.vtmv.t.v a0, v8 +; CHECK-NEXT: ret + entry: + call void @llvm.riscv.sf.vtmv.t.v.nxv8i64.iXLen(iXLen %tss, %src, iXLen %vl) + ret void +} diff --git a/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vtmv_v_t.ll b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vtmv_v_t.ll new file mode 100644 index 0000000000000..0dcc2ab5b9a0d --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vtmv_v_t.ll @@ -0,0 +1,114 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \ +; RUN: -mattr=+zvfh -mattr=+zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+xsfmm32a -mattr=+xsfmm32a8f -mattr=+xsfmm32a4i -mattr=+xsfmm64a64f \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \ +; RUN: -mattr=+zvfh -mattr=+zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+xsfmm32a -mattr=+xsfmm32a8f -mattr=+xsfmm32a4i -mattr=+xsfmm64a64f \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK + +declare @llvm.riscv.sf.vtmv.v.t.nxv32bf16.iXLen(iXLen, iXLen) + +define @test_sf_vtmv_v_t_bf16m8(iXLen %tss, iXLen %vl) { +; CHECK-LABEL: test_sf_vtmv_v_t_bf16m8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt zero, a1, e16, w1 +; CHECK-NEXT: sf.vtmv.v.t v8, a0 +; CHECK-NEXT: ret + entry: + %0 = call @llvm.riscv.sf.vtmv.v.t.nxv32bf16.iXLen(iXLen %tss, iXLen %vl) + ret %0 +} + +declare @llvm.riscv.sf.vtmv.v.t.nxv32f16.iXLen(iXLen, iXLen) + +define @test_sf_vtmv_v_t_f16(iXLen %tss, iXLen %vl) { +; CHECK-LABEL: test_sf_vtmv_v_t_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt zero, a1, e16, w1 +; CHECK-NEXT: sf.vtmv.v.t v8, a0 +; CHECK-NEXT: ret + entry: + %0 = call @llvm.riscv.sf.vtmv.v.t.nxv32f16.iXLen(iXLen %tss, iXLen %vl) + ret %0 +} + +declare @llvm.riscv.sf.vtmv.v.t.nxv16f32.iXLen(iXLen, iXLen) + +define @test_sf_vtmv_v_t_f32(iXLen %tss, iXLen %vl) { +; CHECK-LABEL: test_sf_vtmv_v_t_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt zero, a1, e32, w1 +; CHECK-NEXT: sf.vtmv.v.t v8, a0 +; CHECK-NEXT: ret + entry: + %0 = call @llvm.riscv.sf.vtmv.v.t.nxv16f32.iXLen(iXLen %tss, iXLen %vl) + ret %0 +} + +declare @llvm.riscv.sf.vtmv.v.t.nxv8f64.iXLen(iXLen, iXLen) + +define @test_sf_vtmv_v_t_f64(iXLen %tss, iXLen %vl) { +; CHECK-LABEL: test_sf_vtmv_v_t_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt zero, a1, e64, w1 +; CHECK-NEXT: sf.vtmv.v.t v8, a0 +; CHECK-NEXT: ret + entry: + %0 = call @llvm.riscv.sf.vtmv.v.t.nxv8f64.iXLen(iXLen %tss, iXLen %vl) + ret %0 +} + +declare @llvm.riscv.sf.vtmv.v.t.nxv64i8.iXLen(iXLen, iXLen) + +define @test_sf_vtmv_v_t_i8(iXLen %tss, iXLen %vl) { +; CHECK-LABEL: test_sf_vtmv_v_t_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt zero, a1, e8, w1 +; CHECK-NEXT: sf.vtmv.v.t v8, a0 +; CHECK-NEXT: ret + entry: + %0 = call @llvm.riscv.sf.vtmv.v.t.nxv64i8.iXLen(iXLen %tss, iXLen %vl) + ret %0 +} + +declare @llvm.riscv.sf.vtmv.v.t.nxv32i16.iXLen(iXLen, iXLen) + +define @test_sf_vtmv_v_t_i16(iXLen %tss, iXLen %vl) { +; CHECK-LABEL: test_sf_vtmv_v_t_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt zero, a1, e16, w1 +; CHECK-NEXT: sf.vtmv.v.t v8, a0 +; CHECK-NEXT: ret + entry: + %0 = call @llvm.riscv.sf.vtmv.v.t.nxv32i16.iXLen(iXLen %tss, iXLen %vl) + ret %0 +} + +declare @llvm.riscv.sf.vtmv.v.t.nxv16i32.iXLen(iXLen, iXLen) + +define @test_sf_vtmv_v_t_i32(iXLen %tss, iXLen %vl) { +; CHECK-LABEL: test_sf_vtmv_v_t_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt zero, a1, e32, w1 +; CHECK-NEXT: sf.vtmv.v.t v8, a0 +; CHECK-NEXT: ret + entry: + %0 = call @llvm.riscv.sf.vtmv.v.t.nxv16i32.iXLen(iXLen %tss, iXLen %vl) + ret %0 +} + +declare @llvm.riscv.sf.vtmv.v.t.nxv8i64.iXLen(iXLen, iXLen) + +define @test_sf_vtmv_v_t_i64(iXLen %tss, iXLen %vl) { +; CHECK-LABEL: test_sf_vtmv_v_t_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt zero, a1, e64, w1 +; CHECK-NEXT: sf.vtmv.v.t v8, a0 +; CHECK-NEXT: ret + entry: + %0 = call @llvm.riscv.sf.vtmv.v.t.nxv8i64.iXLen(iXLen %tss, iXLen %vl) + ret %0 +} diff --git a/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vtzero_t.ll b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vtzero_t.ll new file mode 100644 index 0000000000000..bbccb026f161b --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/sifive_sf_vtzero_t.ll @@ -0,0 +1,24 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \ +; RUN: -mattr=+zvfh -mattr=+experimental-zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+xsfmm32a -mattr=+xsfmm32a8f -mattr=+xsfmm32a4i -mattr=+xsfmm64a64f \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \ +; RUN: -mattr=+zvfh -mattr=+experimental-zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+experimental-zvfbfmin -mattr=+xsfmmbase \ +; RUN: -mattr=+xsfmm32a -mattr=+xsfmm32a8f -mattr=+xsfmm32a4i -mattr=+xsfmm64a64f \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK + +declare void @llvm.riscv.sf.vtzero.t.iXLen(iXLen, iXLen, iXLen, iXLen, iXLen) +define void @test_sf_vtzero_t(iXLen %tm, iXLen %tn) { +; CHECK-LABEL: test_sf_vtzero_t: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: sf.vsettnt zero, a1, e8, w4 +; CHECK-NEXT: sf.vsettm zero, a0 +; CHECK-NEXT: sf.vtzero.t mt0 +; CHECK-NEXT: ret + entry: + call void @llvm.riscv.sf.vtzero.t.iXLen(iXLen 0, iXLen %tm, iXLen %tn, iXLen 3, iXLen 4) + ret void +} + From ae966e1bd820ab425406d6d18e4c63d5a4e698ff Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Thu, 5 Jun 2025 02:45:05 -0700 Subject: [PATCH 3/3] [RISCV] Support XSfmm C intrinsics In this version of intrinsics, users need to manage the life time of tiles on their own, compiler doesn't have tile type for variables not only for design simplicity but also preventing users to write bad performance code that could potentially having tile spills which are quite expensive in terms of cycles. --- .../clang/Basic/riscv_sifive_vector.td | 170 ++++++++++++++++++ .../clang/Basic/riscv_vector_common.td | 3 + .../clang/Support/RISCVVIntrinsicUtils.h | 12 +- clang/lib/CodeGen/TargetBuiltins/RISCV.cpp | 2 + clang/lib/Headers/sifive_vector.h | 56 ++++++ clang/lib/Sema/SemaRISCV.cpp | 50 ++++++ clang/lib/Support/RISCVVIntrinsicUtils.cpp | 11 +- .../non-overloaded/sf_mm_e4m3_e4m3.c | 18 ++ .../non-overloaded/sf_mm_e4m3_e5m2.c | 18 ++ .../non-overloaded/sf_mm_e5m2_e4m3.c | 18 ++ .../non-overloaded/sf_mm_e5m2_e5m2.c | 18 ++ .../non-policy/non-overloaded/sf_mm_f_f.c | 40 +++++ .../non-policy/non-overloaded/sf_mm_s_s.c | 18 ++ .../non-policy/non-overloaded/sf_mm_s_u.c | 18 ++ .../non-policy/non-overloaded/sf_mm_u_s.c | 18 ++ .../non-policy/non-overloaded/sf_mm_u_u.c | 18 ++ .../non-policy/non-overloaded/sf_vlte16.c | 49 +++++ .../non-policy/non-overloaded/sf_vlte32.c | 38 ++++ .../non-policy/non-overloaded/sf_vlte64.c | 38 ++++ .../non-policy/non-overloaded/sf_vlte8.c | 28 +++ .../non-policy/non-overloaded/sf_vsettk.c | 99 ++++++++++ .../non-policy/non-overloaded/sf_vsettm.c | 99 ++++++++++ .../non-policy/non-overloaded/sf_vsettn.c | 99 ++++++++++ .../non-policy/non-overloaded/sf_vsettnt.c | 99 ++++++++++ .../non-policy/non-overloaded/sf_vste16.c | 49 +++++ .../non-policy/non-overloaded/sf_vste32.c | 38 ++++ .../non-policy/non-overloaded/sf_vste64.c | 38 ++++ .../non-policy/non-overloaded/sf_vste8.c | 28 +++ .../non-policy/non-overloaded/sf_vtdiscard.c | 18 ++ .../non-policy/non-overloaded/sf_vtmv_t_v.c | 130 ++++++++++++++ .../non-policy/non-overloaded/sf_vtmv_v_t.c | 130 ++++++++++++++ .../non-policy/non-overloaded/sf_vtzero_t.c | 99 ++++++++++ .../non-policy/overloaded/sf_mm_e4m3_e4m3.c | 18 ++ .../non-policy/overloaded/sf_mm_e4m3_e5m2.c | 18 ++ .../non-policy/overloaded/sf_mm_e5m2_e4m3.c | 18 ++ .../non-policy/overloaded/sf_mm_e5m2_e5m2.c | 18 ++ .../non-policy/overloaded/sf_mm_f_f.c | 40 +++++ .../non-policy/overloaded/sf_mm_s_s.c | 18 ++ .../non-policy/overloaded/sf_mm_s_u.c | 18 ++ .../non-policy/overloaded/sf_mm_u_s.c | 18 ++ .../non-policy/overloaded/sf_mm_u_u.c | 18 ++ .../non-policy/overloaded/sf_vlte16.c | 49 +++++ .../non-policy/overloaded/sf_vlte32.c | 38 ++++ .../non-policy/overloaded/sf_vlte64.c | 38 ++++ .../non-policy/overloaded/sf_vlte8.c | 28 +++ .../non-policy/overloaded/sf_vste16.c | 49 +++++ .../non-policy/overloaded/sf_vste32.c | 38 ++++ .../non-policy/overloaded/sf_vste64.c | 38 ++++ .../non-policy/overloaded/sf_vste8.c | 28 +++ .../non-policy/overloaded/sf_vtmv_t_v.c | 130 ++++++++++++++ clang/test/Sema/sifive-xsfmm.c | 17 ++ clang/test/Sema/sifive_sf_vset_invalid.c | 17 ++ clang/utils/TableGen/RISCVVEmitter.cpp | 23 ++- 53 files changed, 2235 insertions(+), 9 deletions(-) create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c create mode 100644 clang/test/Sema/sifive-xsfmm.c create mode 100644 clang/test/Sema/sifive_sf_vset_invalid.c diff --git a/clang/include/clang/Basic/riscv_sifive_vector.td b/clang/include/clang/Basic/riscv_sifive_vector.td index f7996f362378a..9740f98f1285a 100644 --- a/clang/include/clang/Basic/riscv_sifive_vector.td +++ b/clang/include/clang/Basic/riscv_sifive_vector.td @@ -14,6 +14,10 @@ include "riscv_vector_common.td" +class IsFloat { + bit val = !or(!eq(type, "x"), !eq(type, "f"), !eq(type, "d"), !eq(type, "y")); +} + //===----------------------------------------------------------------------===// // Instruction definitions //===----------------------------------------------------------------------===// @@ -198,3 +202,169 @@ let ManualCodegen = [{ defm sf_vfnrclip_xu_f_qf : RVVVFNRCLIPBuiltinSet<"Uv", "UvFqf", "c">; } } + +multiclass RVVSFTileLoadStoreBuiltinSet types, + list RequiredFeatures = []> { + let OverloadedName = NAME, + Name = NAME, + IRName = NAME, + Log2LMUL = [0], + HasMasked = false, + ManualCodegen = [{IntrinsicTypes = {Ops.back()->getType()};}] in + foreach type = types in { + let RequiredFeatures = !listconcat(RequiredFeatures, + !cond(!eq(type, "x"): ["Zvfhmin"], + !eq(type, "y"): ["Zvfbfmin"], + true: [])) in { + def : RVVBuiltin<"e", "0zPCe", type>; + if !not(IsFloat.val) then + def : RVVBuiltin<"Ue", "0zPCUe", type>; + } + } +} + +multiclass RVVSFTileMoveBuiltinSet> suffixes_prototypes, + list intrinsic_types, + string type, + list RequiredFeatures = []> { + foreach sp = suffixes_prototypes in + let RequiredFeatures = !listconcat(RequiredFeatures, + !cond(!eq(type, "x"): ["Zvfhmin"], + !eq(type, "y"): ["Zvfbfmin"], + true: [])), + SupportOverloading = false, + HasMasked = false, + Name = NAME, + IRName = NAME, + HasVL = true, + Log2LMUL = [3], + IntrinsicTypes = intrinsic_types in + def : RVVBuiltin; +} + +multiclass RVVSFTileMoveVTBuiltinSet RequiredFeatures = []> { + foreach type = ["c", "s", "i", "l"] in + defm NAME : + RVVSFTileMoveBuiltinSet<[["v", "vz"], ["Uv", "Uvz"]], [-1], type, + RequiredFeatures>; + foreach type = ["x", "y", "f", "d"] in + defm NAME : + RVVSFTileMoveBuiltinSet<[["v", "vz"]], [-1], type, RequiredFeatures>; +} + +multiclass RVVSFTileMoveTVBuiltinSet RequiredFeatures = []> { + let SupportOverloading = true, OverloadedName = NAME in { + foreach type = ["c", "s", "i", "l"] in + defm NAME : + RVVSFTileMoveBuiltinSet<[["v", "0zv"], ["Uv", "0zUv"]], [1], type, + RequiredFeatures>; + foreach type = ["x", "y", "f", "d"] in + defm NAME : + RVVSFTileMoveBuiltinSet<[["v", "0zv"]], [1], type, RequiredFeatures>; + } +} + +multiclass RVVOp0Op1Op2BuiltinSet> suffixes_prototypes> + : RVVBuiltinSet; + +multiclass RVVSFMatMulBuiltinSet widens> { + foreach widen = widens in + let OverloadedName = NAME, + TWiden = widen, + HasVL = false, + Log2LMUL = [3], + HasMasked = false in + defm NAME : RVVOp0Op1Op2BuiltinSet(widen)), suffix, prototype]]>; +} + +multiclass RVVSFMatMulFloatBuiltinSet type_range, int widen> { + // Currently the XSfmm spec doesn't support w8. + foreach type = type_range in + let OverloadedName = name # !strconcat("_w", !cast(widen)), + TWiden = widen, + HasVL = false, + Log2LMUL = [3], + Name = name # "_" # !strconcat("w", !cast(widen)), + HasMasked = false in + defm : RVVOp0Op1BuiltinSet; +} + +multiclass RVVSFVTZeroBuiltinSet { + let SupportOverloading = false, + HasVL = false, + HasMasked = false, + Name = NAME, + IRName = NAME, + Log2LMUL = [0] in + defm : RVVOp0BuiltinSet; +} + +multiclass RVVSFVTDiscardBuiltinSet { + let SupportOverloading = false, + HasVL = false, + HasMasked = false, + Name = NAME, + IRName = NAME, + Log2LMUL = [0] in + defm : RVVBuiltinSet; +} + +let RequiredFeatures = ["Xsfmmbase"] in { + let SupportOverloading = false, + HasVL = false, + HasMasked = false, + Log2LMUL = [0], + ManualCodegen = [{IntrinsicTypes = {ResultType};}] in // Set XLEN type + { + // let HasBuiltinAlias = false in + def sf_vsettnt : RVVBuiltin<"", "zzKzKz", "i">; + def sf_vsettm : RVVBuiltin<"", "zzKzKz", "i">; + let IRName = "sf_vsettnt" in + def sf_vsettn : RVVBuiltin<"", "zzKzKz", "i">; + def sf_vsettk : RVVBuiltin<"", "zzKzKz", "i">; + } + defm sf_vtzero_t : RVVSFVTZeroBuiltinSet; + defm sf_vtdiscard : RVVSFVTDiscardBuiltinSet; +} + +defm sf_vtmv_v_t : RVVSFTileMoveVTBuiltinSet<["Xsfmmbase"]>; +defm sf_vtmv_t_v : RVVSFTileMoveTVBuiltinSet<["Xsfmmbase"]>; + +defm sf_vlte8 : RVVSFTileLoadStoreBuiltinSet<["c"], ["Xsfmmbase"]>; +defm sf_vlte16 : RVVSFTileLoadStoreBuiltinSet<["s", "x", "y"], ["Xsfmmbase"]>; +defm sf_vlte32 : RVVSFTileLoadStoreBuiltinSet<["i", "f"], ["Xsfmmbase"]>; +defm sf_vlte64 : RVVSFTileLoadStoreBuiltinSet<["l", "d"], ["Xsfmmbase"]>; + +defm sf_vste8 : RVVSFTileLoadStoreBuiltinSet<["c"], ["Xsfmmbase"]>; +defm sf_vste16 : RVVSFTileLoadStoreBuiltinSet<["s", "x", "y"], ["Xsfmmbase"]>; +defm sf_vste32 : RVVSFTileLoadStoreBuiltinSet<["i", "f"], ["Xsfmmbase"]>; +defm sf_vste64 : RVVSFTileLoadStoreBuiltinSet<["l", "d"], ["Xsfmmbase"]>; + +let RequiredFeatures = ["Xsfmm32a8i"] in { + defm sf_mm_u_u : RVVSFMatMulBuiltinSet<"0KzUvUvzzz", "UvUv", "c", [4]>; + defm sf_mm_s_u : RVVSFMatMulBuiltinSet<"0KzvUvzzz", "vUv", "c", [4]>; + defm sf_mm_u_s : RVVSFMatMulBuiltinSet<"0KzUvvzzz", "Uvv", "c", [4]>; + defm sf_mm_s_s : RVVSFMatMulBuiltinSet<"0Kzvvzzz", "vv", "c", [4]>; + +} + +let RequiredFeatures = ["Xsfmm32a16f"] in + defm : RVVSFMatMulFloatBuiltinSet<"sf_mm_f_f", "0Kzvvzzz", "v", ["x", "y"], 2>; + +let RequiredFeatures = ["Xsfmm32a32f"] in + defm : RVVSFMatMulFloatBuiltinSet<"sf_mm_f_f", "0Kzvvzzz", "v", ["f"], 1>; + +let RequiredFeatures = ["Xsfmm32a8f"] in + foreach e1 = [5, 4] in + foreach e2 = [5, 4] in + let OverloadedName = "sf_mm_e" # e1 # "m" # !sub(7, e1) # "_e" # e2 # "m" # !sub(7, e2) in + defm : RVVSFMatMulFloatBuiltinSet< + "sf_mm_e" # e1 # "m" # !sub(7, e1) # "_e" # e2 # "m" # !sub(7, e2), + "0KzUvUvzzz", "UvUv", ["c"], 4>; + +let RequiredFeatures = ["Xsfmm64a64f"] in + defm : RVVSFMatMulFloatBuiltinSet<"sf_mm_f_f", "0Kzvvzzz", "v", ["d"], 1>; diff --git a/clang/include/clang/Basic/riscv_vector_common.td b/clang/include/clang/Basic/riscv_vector_common.td index 5a81376208f70..cd593b2b01969 100644 --- a/clang/include/clang/Basic/riscv_vector_common.td +++ b/clang/include/clang/Basic/riscv_vector_common.td @@ -245,6 +245,9 @@ class RVVBuiltin IntrinsicTypes; unsigned NF = 1; Policy PolicyAttrs; + unsigned TWiden = 0; public: RVVIntrinsic(llvm::StringRef Name, llvm::StringRef Suffix, @@ -411,8 +412,8 @@ class RVVIntrinsic { bool HasVL, PolicyScheme Scheme, bool SupportOverloading, bool HasBuiltinAlias, llvm::StringRef ManualCodegen, const RVVTypes &Types, - const std::vector &IntrinsicTypes, - unsigned NF, Policy PolicyAttrs, bool HasFRMRoundModeOp); + const std::vector &IntrinsicTypes, unsigned NF, + Policy PolicyAttrs, bool HasFRMRoundModeOp, unsigned TWiden); ~RVVIntrinsic() = default; RVVTypePtr getOutputType() const { return OutputType; } @@ -436,6 +437,7 @@ class RVVIntrinsic { llvm::StringRef getManualCodegen() const { return ManualCodegen; } PolicyScheme getPolicyScheme() const { return Scheme; } unsigned getNF() const { return NF; } + unsigned getTWiden() const { return TWiden; } const std::vector &getIntrinsicTypes() const { return IntrinsicTypes; } @@ -508,6 +510,12 @@ enum RVVRequire { RVV_REQ_Zvfbfwma, RVV_REQ_Zvfbfmin, RVV_REQ_Zvfh, + RVV_REQ_Xsfmmbase, + RVV_REQ_Xsfmm32a8f, + RVV_REQ_Xsfmm32a16f, + RVV_REQ_Xsfmm32a32f, + RVV_REQ_Xsfmm64a64f, + RVV_REQ_Xsfmm32a8i, RVV_REQ_Experimental, RVV_REQ_NUM, }; diff --git a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp index 89e3f6f203df3..68ce56c2a78bf 100644 --- a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp +++ b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp @@ -188,6 +188,8 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID, bool IsMasked = false; // This is used by segment load/store to determine it's llvm type. unsigned SegInstSEW = 8; + // This is used by XSfmm. + unsigned TWiden = 0; // Required for overloaded intrinsics. llvm::SmallVector IntrinsicTypes; diff --git a/clang/lib/Headers/sifive_vector.h b/clang/lib/Headers/sifive_vector.h index 4e67ad6fca262..ae01627de2d7d 100644 --- a/clang/lib/Headers/sifive_vector.h +++ b/clang/lib/Headers/sifive_vector.h @@ -115,4 +115,60 @@ #endif #endif +#define __riscv_sf_vsettnt_e8w1(atn) __riscv_sf_vsettnt(atn, 0, 1); +#define __riscv_sf_vsettnt_e8w2(atn) __riscv_sf_vsettnt(atn, 0, 2); +#define __riscv_sf_vsettnt_e8w4(atn) __riscv_sf_vsettnt(atn, 0, 3); +#define __riscv_sf_vsettnt_e16w1(atn) __riscv_sf_vsettnt(atn, 1, 1); +#define __riscv_sf_vsettnt_e16w2(atn) __riscv_sf_vsettnt(atn, 1, 2); +#define __riscv_sf_vsettnt_e16w4(atn) __riscv_sf_vsettnt(atn, 1, 3); +#define __riscv_sf_vsettnt_e32w1(atn) __riscv_sf_vsettnt(atn, 2, 1); +#define __riscv_sf_vsettnt_e32w2(atn) __riscv_sf_vsettnt(atn, 2, 2); +#define __riscv_sf_vsettm_e8w1(atm) __riscv_sf_vsettm(atm, 0, 1); +#define __riscv_sf_vsettm_e8w2(atm) __riscv_sf_vsettm(atm, 0, 2); +#define __riscv_sf_vsettm_e8w4(atm) __riscv_sf_vsettm(atm, 0, 3); +#define __riscv_sf_vsettm_e16w1(atm) __riscv_sf_vsettm(atm, 1, 1); +#define __riscv_sf_vsettm_e16w2(atm) __riscv_sf_vsettm(atm, 1, 2); +#define __riscv_sf_vsettm_e16w4(atm) __riscv_sf_vsettm(atm, 1, 3); +#define __riscv_sf_vsettm_e32w1(atm) __riscv_sf_vsettm(atm, 2, 1); +#define __riscv_sf_vsettm_e32w2(atm) __riscv_sf_vsettm(atm, 2, 2); +#define __riscv_sf_vsettn_e8w1(atn) __riscv_sf_vsettn(atn, 0, 1); +#define __riscv_sf_vsettn_e8w2(atn) __riscv_sf_vsettn(atn, 0, 2); +#define __riscv_sf_vsettn_e8w4(atn) __riscv_sf_vsettn(atn, 0, 3); +#define __riscv_sf_vsettn_e16w1(atn) __riscv_sf_vsettn(atn, 1, 1); +#define __riscv_sf_vsettn_e16w2(atn) __riscv_sf_vsettn(atn, 1, 2); +#define __riscv_sf_vsettn_e16w4(atn) __riscv_sf_vsettn(atn, 1, 3); +#define __riscv_sf_vsettn_e32w1(atn) __riscv_sf_vsettn(atn, 2, 1); +#define __riscv_sf_vsettn_e32w2(atn) __riscv_sf_vsettn(atn, 2, 2); +#define __riscv_sf_vsettk_e8w1(atk) __riscv_sf_vsettk(atk, 0, 1); +#define __riscv_sf_vsettk_e8w2(atk) __riscv_sf_vsettk(atk, 0, 2); +#define __riscv_sf_vsettk_e8w4(atk) __riscv_sf_vsettk(atk, 0, 3); +#define __riscv_sf_vsettk_e16w1(atk) __riscv_sf_vsettk(atk, 1, 1); +#define __riscv_sf_vsettk_e16w2(atk) __riscv_sf_vsettk(atk, 1, 2); +#define __riscv_sf_vsettk_e16w4(atk) __riscv_sf_vsettk(atk, 1, 3); +#define __riscv_sf_vsettk_e32w1(atk) __riscv_sf_vsettk(atk, 2, 1); +#define __riscv_sf_vsettk_e32w2(atk) __riscv_sf_vsettk(atk, 2, 2); +#define __riscv_sf_vtzero_t_e8w1(tile, atm, atn) \ + __riscv_sf_vtzero_t(tile, atm, atn, 3, 1); +#define __riscv_sf_vtzero_t_e8w2(tile, atm, atn) \ + __riscv_sf_vtzero_t(tile, atm, atn, 3, 2); +#define __riscv_sf_vtzero_t_e8w4(tile, atm, atn) \ + __riscv_sf_vtzero_t(tile, atm, atn, 3, 4); +#define __riscv_sf_vtzero_t_e16w1(tile, atm, atn) \ + __riscv_sf_vtzero_t(tile, atm, atn, 4, 1); +#define __riscv_sf_vtzero_t_e16w2(tile, atm, atn) \ + __riscv_sf_vtzero_t(tile, atm, atn, 4, 2); +#define __riscv_sf_vtzero_t_e16w4(tile, atm, atn) \ + __riscv_sf_vtzero_t(tile, atm, atn, 4, 4); +#define __riscv_sf_vtzero_t_e32w1(tile, atm, atn) \ + __riscv_sf_vtzero_t(tile, atm, atn, 5, 1); +#define __riscv_sf_vtzero_t_e32w2(tile, atm, atn) \ + __riscv_sf_vtzero_t(tile, atm, atn, 5, 2); +#if __riscv_v_elen >= 64 +#define __riscv_sf_vsettnt_e64w1(atn) __riscv_sf_vsettnt(atn, 3, 1); +#define __riscv_sf_vsettm_e64w1(atm) __riscv_sf_vsettm(atm, 3, 1); +#define __riscv_sf_vsettn_e64w1(atn) __riscv_sf_vsettn(atn, 3, 1); +#define __riscv_sf_vsettk_e64w1(atk) __riscv_sf_vsettk(atk, 3, 1); +#define __riscv_sf_vtzero_t_e64w1(tile, atm, atn) \ + __riscv_sf_vtzero_t(tile, atm, atn, 6, 1); +#endif #endif //_SIFIVE_VECTOR_H_ diff --git a/clang/lib/Sema/SemaRISCV.cpp b/clang/lib/Sema/SemaRISCV.cpp index ac88f5e059b7b..311bc25ca6851 100644 --- a/clang/lib/Sema/SemaRISCV.cpp +++ b/clang/lib/Sema/SemaRISCV.cpp @@ -244,6 +244,12 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics( {"zvfbfwma", RVV_REQ_Zvfbfwma}, {"zvfbfmin", RVV_REQ_Zvfbfmin}, {"zvfh", RVV_REQ_Zvfh}, + {"xsfmmbase", RVV_REQ_Xsfmmbase}, + {"xsfmm32a8f", RVV_REQ_Xsfmm32a8f}, + {"xsfmm32a16f", RVV_REQ_Xsfmm32a16f}, + {"xsfmm32a32f", RVV_REQ_Xsfmm32a32f}, + {"xsfmm64a64f", RVV_REQ_Xsfmm64a64f}, + {"xsfmm32a8i", RVV_REQ_Xsfmm32a8i}, {"experimental", RVV_REQ_Experimental}}; // Construction of RVVIntrinsicRecords need to sync with createRVVIntrinsics @@ -679,6 +685,50 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI, return CheckVSetVL(1, 2); case RISCVVector::BI__builtin_rvv_vsetvlimax: return CheckVSetVL(0, 1); + case RISCVVector::BI__builtin_rvv_sf_vsettnt: + case RISCVVector::BI__builtin_rvv_sf_vsettm: + case RISCVVector::BI__builtin_rvv_sf_vsettn: + case RISCVVector::BI__builtin_rvv_sf_vsettk: + return SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 3) || + SemaRef.BuiltinConstantArgRange(TheCall, 2, 1, 3); + case RISCVVector::BI__builtin_rvv_sf_mm_f_f_w1: + case RISCVVector::BI__builtin_rvv_sf_mm_f_f_w2: + case RISCVVector::BI__builtin_rvv_sf_mm_e5m2_e4m3_w4: + case RISCVVector::BI__builtin_rvv_sf_mm_e5m2_e5m2_w4: + case RISCVVector::BI__builtin_rvv_sf_mm_e4m3_e4m3_w4: + case RISCVVector::BI__builtin_rvv_sf_mm_e4m3_e5m2_w4: + case RISCVVector::BI__builtin_rvv_sf_mm_u_u_w4: + case RISCVVector::BI__builtin_rvv_sf_mm_u_s_w4: + case RISCVVector::BI__builtin_rvv_sf_mm_s_u_w4: + case RISCVVector::BI__builtin_rvv_sf_mm_s_s_w4: { + QualType Arg1Type = TheCall->getArg(1)->getType(); + ASTContext::BuiltinVectorTypeInfo Info = + SemaRef.Context.getBuiltinVectorTypeInfo( + Arg1Type->castAs()); + unsigned EltSize = SemaRef.Context.getTypeSize(Info.ElementType); + llvm::APSInt Result; + + // We can't check the value of a dependent argument. + Expr *Arg = TheCall->getArg(0); + if (Arg->isTypeDependent() || Arg->isValueDependent()) + return false; + + // Check constant-ness first. + if (SemaRef.BuiltinConstantArg(TheCall, 0, Result)) + return true; + + // For TEW = 32, mtd can only be 0, 4, 8, 12. + // For TEW = 64, mtd can only be 0, 2, 4, 6, 8, 10, 12, 14. + // Only `sf_mm_f_f_w1` and `sf_mm_f_f_w2` might have TEW = 64. + if ((BuiltinID == RISCVVector::BI__builtin_rvv_sf_mm_f_f_w1 && + EltSize == 64) || + (BuiltinID == RISCVVector::BI__builtin_rvv_sf_mm_f_f_w2 && + EltSize == 32)) + return SemaRef.BuiltinConstantArgRange(TheCall, 0, 0, 15) || + SemaRef.BuiltinConstantArgMultiple(TheCall, 0, 2); + return SemaRef.BuiltinConstantArgRange(TheCall, 0, 0, 15) || + SemaRef.BuiltinConstantArgMultiple(TheCall, 0, 4); + } case RISCVVector::BI__builtin_rvv_vget_v: { ASTContext::BuiltinVectorTypeInfo ResVecInfo = Context.getBuiltinVectorTypeInfo(cast( diff --git a/clang/lib/Support/RISCVVIntrinsicUtils.cpp b/clang/lib/Support/RISCVVIntrinsicUtils.cpp index 37f95411af195..2adc6e2470d0a 100644 --- a/clang/lib/Support/RISCVVIntrinsicUtils.cpp +++ b/clang/lib/Support/RISCVVIntrinsicUtils.cpp @@ -978,11 +978,12 @@ RVVIntrinsic::RVVIntrinsic( bool HasMaskedOffOperand, bool HasVL, PolicyScheme Scheme, bool SupportOverloading, bool HasBuiltinAlias, StringRef ManualCodegen, const RVVTypes &OutInTypes, const std::vector &NewIntrinsicTypes, - unsigned NF, Policy NewPolicyAttrs, bool HasFRMRoundModeOp) + unsigned NF, Policy NewPolicyAttrs, bool HasFRMRoundModeOp, unsigned TWiden) : IRName(IRName), IsMasked(IsMasked), HasMaskedOffOperand(HasMaskedOffOperand), HasVL(HasVL), Scheme(Scheme), SupportOverloading(SupportOverloading), HasBuiltinAlias(HasBuiltinAlias), - ManualCodegen(ManualCodegen.str()), NF(NF), PolicyAttrs(NewPolicyAttrs) { + ManualCodegen(ManualCodegen.str()), NF(NF), PolicyAttrs(NewPolicyAttrs), + TWiden(TWiden) { // Init BuiltinName, Name and OverloadedName BuiltinName = NewName.str(); @@ -1233,6 +1234,12 @@ llvm::raw_ostream &operator<<(llvm::raw_ostream &OS, enum RVVRequire Require) { STRINGIFY(RVV_REQ_Zvfbfwma) STRINGIFY(RVV_REQ_Zvfbfmin) STRINGIFY(RVV_REQ_Zvfh) + STRINGIFY(RVV_REQ_Xsfmmbase) + STRINGIFY(RVV_REQ_Xsfmm32a8f) + STRINGIFY(RVV_REQ_Xsfmm32a16f) + STRINGIFY(RVV_REQ_Xsfmm32a32f) + STRINGIFY(RVV_REQ_Xsfmm64a64f) + STRINGIFY(RVV_REQ_Xsfmm32a8i) STRINGIFY(RVV_REQ_Experimental) default: llvm_unreachable("Unsupported RVVRequire!"); diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c new file mode 100644 index 0000000000000..3da3ba04d942d --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c @@ -0,0 +1,18 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmm32a8f \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_e4m3_e4m3_w4_u8m8_u8m8( +// CHECK-RV64-SAME: [[V1:%.*]], [[V2:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 0, [[V1]], [[V2]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 4) +// CHECK-RV64-NEXT: ret void +// +void test_sf_mm_e4m3_e4m3_w4_u8m8_u8m8(vuint8m8_t v1, vuint8m8_t v2, size_t tm, size_t tn, size_t tk) { + return __riscv_sf_mm_e4m3_e4m3_w4_u8m8_u8m8(0, v1, v2, tm, tn, tk); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c new file mode 100644 index 0000000000000..272f1dbf3efa7 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c @@ -0,0 +1,18 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmm32a8f \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_e4m3_e5m2_w4_u8m8_u8m8( +// CHECK-RV64-SAME: [[V1:%.*]], [[V2:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.e4m3.e5m2.i64.nxv64i8(i64 0, [[V1]], [[V2]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 4) +// CHECK-RV64-NEXT: ret void +// +void test_sf_mm_e4m3_e5m2_w4_u8m8_u8m8(vuint8m8_t v1, vuint8m8_t v2, size_t tm, size_t tn, size_t tk) { + return __riscv_sf_mm_e4m3_e5m2_w4_u8m8_u8m8(0, v1, v2, tm, tn, tk); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c new file mode 100644 index 0000000000000..56f56c01391f9 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c @@ -0,0 +1,18 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmm32a8f \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_e5m2_e4m3_w4_u8m8_u8m8( +// CHECK-RV64-SAME: [[V1:%.*]], [[V2:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.e5m2.e4m3.i64.nxv64i8(i64 0, [[V1]], [[V2]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 4) +// CHECK-RV64-NEXT: ret void +// +void test_sf_mm_e5m2_e4m3_w4_u8m8_u8m8(vuint8m8_t v1, vuint8m8_t v2, size_t tm, size_t tn, size_t tk) { + return __riscv_sf_mm_e5m2_e4m3_w4_u8m8_u8m8(0, v1, v2, tm, tn, tk); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c new file mode 100644 index 0000000000000..8044c42b54d13 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c @@ -0,0 +1,18 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmm32a8f \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_e5m2_e5m2_w4_u8m8_u8m8( +// CHECK-RV64-SAME: [[V1:%.*]], [[V2:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.e5m2.e5m2.i64.nxv64i8(i64 0, [[V1]], [[V2]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 4) +// CHECK-RV64-NEXT: ret void +// +void test_sf_mm_e5m2_e5m2_w4_u8m8_u8m8(vuint8m8_t v1, vuint8m8_t v2, size_t tm, size_t tn, size_t tk) { + return __riscv_sf_mm_e5m2_e5m2_w4_u8m8_u8m8(0, v1, v2, tm, tn, tk); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c new file mode 100644 index 0000000000000..daebe63106314 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c @@ -0,0 +1,40 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmm32a16f \ +// RUN: -target-feature +xsfmm32a32f -target-feature +xsfmm64a64f \ +// RUN: -target-feature +zvfhmin -target-feature +zve64d -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_f_f_w2_f16m8( +// CHECK-RV64-SAME: [[V1:%.*]], [[V2:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 0, [[V1]], [[V2]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 2) +// CHECK-RV64-NEXT: ret void +// +void test_sf_mm_f_f_w2_f16m8(vfloat16m8_t v1, vfloat16m8_t v2, size_t tm, size_t tn, size_t tk) { + return __riscv_sf_mm_f_f_w2_f16m8(0, v1, v2, tm, tn, tk); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_f_f_w1_f32m8( +// CHECK-RV64-SAME: [[V1:%.*]], [[V2:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.f.f.i64.nxv16f32(i64 0, [[V1]], [[V2]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 1) +// CHECK-RV64-NEXT: ret void +// +void test_sf_mm_f_f_w1_f32m8(vfloat32m8_t v1, vfloat32m8_t v2, size_t tm, size_t tn, size_t tk) { + return __riscv_sf_mm_f_f_w1_f32m8(0, v1, v2, tm, tn, tk); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_f_f_w1_f64m8( +// CHECK-RV64-SAME: [[V1:%.*]], [[V2:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.f.f.i64.nxv8f64(i64 0, [[V1]], [[V2]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 1) +// CHECK-RV64-NEXT: ret void +// +void test_sf_mm_f_f_w1_f64m8(vfloat64m8_t v1, vfloat64m8_t v2, size_t tm, size_t tn, size_t tk) { + return __riscv_sf_mm_f_f_w1_f64m8(0, v1, v2, tm, tn, tk); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c new file mode 100644 index 0000000000000..0cbc38521c4ad --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c @@ -0,0 +1,18 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmm32a8i \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_s_s_w4_i8m8_i8m8( +// CHECK-RV64-SAME: [[V1:%.*]], [[V2:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.s.s.i64.nxv64i8.nxv64i8(i64 0, [[V1]], [[V2]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 4) +// CHECK-RV64-NEXT: ret void +// +void test_sf_mm_s_s_w4_i8m8_i8m8(vint8m8_t v1, vint8m8_t v2, size_t tm, size_t tn, size_t tk) { + return __riscv_sf_mm_s_s_w4_i8m8_i8m8(0, v1, v2, tm, tn, tk); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c new file mode 100644 index 0000000000000..1f8635b0ea1b7 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c @@ -0,0 +1,18 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmm32a8i \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_s_u_w4_i8m8_u8m8( +// CHECK-RV64-SAME: [[V1:%.*]], [[V2:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.s.u.i64.nxv64i8.nxv64i8(i64 0, [[V1]], [[V2]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 4) +// CHECK-RV64-NEXT: ret void +// +void test_sf_mm_s_u_w4_i8m8_u8m8(vint8m8_t v1, vuint8m8_t v2, size_t tm, size_t tn, size_t tk) { + return __riscv_sf_mm_s_u_w4_i8m8_u8m8(0, v1, v2, tm, tn, tk); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c new file mode 100644 index 0000000000000..a11ca8f8010ea --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c @@ -0,0 +1,18 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmm32a8i \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_u_s_w4_u8m8_i8m8( +// CHECK-RV64-SAME: [[V1:%.*]], [[V2:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.u.s.i64.nxv64i8.nxv64i8(i64 0, [[V1]], [[V2]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 4) +// CHECK-RV64-NEXT: ret void +// +void test_sf_mm_u_s_w4_u8m8_i8m8(vuint8m8_t v1, vint8m8_t v2, size_t tm, size_t tn, size_t tk) { + return __riscv_sf_mm_u_s_w4_u8m8_i8m8(0, v1, v2, tm, tn, tk); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c new file mode 100644 index 0000000000000..6d9d4b702f0af --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c @@ -0,0 +1,18 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmm32a8i \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_u_u_w4_u8m8_u8m8( +// CHECK-RV64-SAME: [[V1:%.*]], [[V2:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.u.u.i64.nxv64i8.nxv64i8(i64 0, [[V1]], [[V2]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 4) +// CHECK-RV64-NEXT: ret void +// +void test_sf_mm_u_u_w4_u8m8_u8m8(vuint8m8_t v1, vuint8m8_t v2, size_t tm, size_t tn, size_t tk) { + return __riscv_sf_mm_u_u_w4_u8m8_u8m8(0, v1, v2, tm, tn, tk); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c new file mode 100644 index 0000000000000..2c23176aca97c --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c @@ -0,0 +1,49 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmmbase \ +// RUN: -target-feature +zvfhmin -target-feature +zvfbfmin \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vlte16_bf16( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vlte16.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vlte16_bf16(size_t tss, __bf16 *base, size_t vl) { + return __riscv_sf_vlte16_bf16(tss, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vlte16_f16( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vlte16.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vlte16_f16(size_t tss, _Float16 *base, size_t vl) { + return __riscv_sf_vlte16_f16(tss, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vlte16_i16( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vlte16.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vlte16_i16(size_t tss, int16_t *base, size_t vl) { + return __riscv_sf_vlte16_i16(tss, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vlte16_u16( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vlte16.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vlte16_u16(size_t tss, uint16_t *base, size_t vl) { + return __riscv_sf_vlte16_u16(tss, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c new file mode 100644 index 0000000000000..a0422cfe2c8ce --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c @@ -0,0 +1,38 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmmbase \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vlte32_f32( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vlte32.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vlte32_f32(size_t tss, float *base, size_t vl) { + return __riscv_sf_vlte32_f32(tss, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vlte32_i32( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vlte32.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vlte32_i32(size_t tss, int32_t *base, size_t vl) { + return __riscv_sf_vlte32_i32(tss, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vlte32_u32( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vlte32.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vlte32_u32(size_t tss, uint32_t *base, size_t vl) { + return __riscv_sf_vlte32_u32(tss, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c new file mode 100644 index 0000000000000..e8b9552451e65 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c @@ -0,0 +1,38 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmmbase \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vlte64_f64( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vlte64.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vlte64_f64(size_t tss, double *base, size_t vl) { + return __riscv_sf_vlte64_f64(tss, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vlte64_i64( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vlte64.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vlte64_i64(size_t tss, int64_t *base, size_t vl) { + return __riscv_sf_vlte64_i64(tss, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vlte64_u64( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vlte64.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vlte64_u64(size_t tss, uint64_t *base, size_t vl) { + return __riscv_sf_vlte64_u64(tss, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c new file mode 100644 index 0000000000000..a86ccec3bd3ca --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c @@ -0,0 +1,28 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmmbase \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vlte8_i8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vlte8.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vlte8_i8(size_t tss, int8_t *base, size_t vl) { + return __riscv_sf_vlte8_i8(tss, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vlte8_u8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vlte8.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vlte8_u8(size_t tss, uint8_t *base, size_t vl) { + return __riscv_sf_vlte8_u8(tss, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c new file mode 100644 index 0000000000000..32b7bce839b6e --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c @@ -0,0 +1,99 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmmbase \ +// RUN: -target-feature +zve64x \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettk_e8w1( +// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettk.i64(i64 [[TN]], i64 0, i64 1) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +size_t test_sf_vsettk_e8w1(size_t tn) { + return __riscv_sf_vsettk_e8w1(tn); +} + +// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettk_e8w2( +// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettk.i64(i64 [[TN]], i64 0, i64 2) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +size_t test_sf_vsettk_e8w2(size_t tn) { + return __riscv_sf_vsettk_e8w2(tn); +} + +// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettk_e8w4( +// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettk.i64(i64 [[TN]], i64 0, i64 3) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +size_t test_sf_vsettk_e8w4(size_t tn) { + return __riscv_sf_vsettk_e8w4(tn); +} + +// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettk_e16w1( +// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettk.i64(i64 [[TN]], i64 1, i64 1) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +size_t test_sf_vsettk_e16w1(size_t tn) { + return __riscv_sf_vsettk_e16w1(tn); +} + +// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettk_e16w2( +// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettk.i64(i64 [[TN]], i64 1, i64 2) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +size_t test_sf_vsettk_e16w2(size_t tn) { + return __riscv_sf_vsettk_e16w2(tn); +} + +// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettk_e16w4( +// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettk.i64(i64 [[TN]], i64 1, i64 3) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +size_t test_sf_vsettk_e16w4(size_t tn) { + return __riscv_sf_vsettk_e16w4(tn); +} + +// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettk_e32w1( +// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettk.i64(i64 [[TN]], i64 2, i64 1) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +size_t test_sf_vsettk_e32w1(size_t tn) { + return __riscv_sf_vsettk_e32w1(tn); +} + +// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettk_e32w2( +// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettk.i64(i64 [[TN]], i64 2, i64 2) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +size_t test_sf_vsettk_e32w2(size_t tn) { + return __riscv_sf_vsettk_e32w2(tn); +} + +// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettk_e64w1( +// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettk.i64(i64 [[TN]], i64 3, i64 1) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +size_t test_sf_vsettk_e64w1(size_t tn) { + return __riscv_sf_vsettk_e64w1(tn); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c new file mode 100644 index 0000000000000..0ce7c5785a22f --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c @@ -0,0 +1,99 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmmbase \ +// RUN: -target-feature +zve64x \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettm_e8w1( +// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettm.i64(i64 [[TN]], i64 0, i64 1) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +size_t test_sf_vsettm_e8w1(size_t tn) { + return __riscv_sf_vsettm_e8w1(tn); +} + +// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettm_e8w2( +// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettm.i64(i64 [[TN]], i64 0, i64 2) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +size_t test_sf_vsettm_e8w2(size_t tn) { + return __riscv_sf_vsettm_e8w2(tn); +} + +// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettm_e8w4( +// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettm.i64(i64 [[TN]], i64 0, i64 3) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +size_t test_sf_vsettm_e8w4(size_t tn) { + return __riscv_sf_vsettm_e8w4(tn); +} + +// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettm_e16w1( +// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettm.i64(i64 [[TN]], i64 1, i64 1) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +size_t test_sf_vsettm_e16w1(size_t tn) { + return __riscv_sf_vsettm_e16w1(tn); +} + +// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettm_e16w2( +// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettm.i64(i64 [[TN]], i64 1, i64 2) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +size_t test_sf_vsettm_e16w2(size_t tn) { + return __riscv_sf_vsettm_e16w2(tn); +} + +// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettm_e16w4( +// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettm.i64(i64 [[TN]], i64 1, i64 3) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +size_t test_sf_vsettm_e16w4(size_t tn) { + return __riscv_sf_vsettm_e16w4(tn); +} + +// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettm_e32w1( +// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettm.i64(i64 [[TN]], i64 2, i64 1) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +size_t test_sf_vsettm_e32w1(size_t tn) { + return __riscv_sf_vsettm_e32w1(tn); +} + +// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettm_e32w2( +// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettm.i64(i64 [[TN]], i64 2, i64 2) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +size_t test_sf_vsettm_e32w2(size_t tn) { + return __riscv_sf_vsettm_e32w2(tn); +} + +// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettm_e64w1( +// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettm.i64(i64 [[TN]], i64 3, i64 1) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +size_t test_sf_vsettm_e64w1(size_t tn) { + return __riscv_sf_vsettm_e64w1(tn); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c new file mode 100644 index 0000000000000..7b058f4667738 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c @@ -0,0 +1,99 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmmbase \ +// RUN: -target-feature +zve64x \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettn_e8w1( +// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettnt.i64(i64 [[TN]], i64 0, i64 1) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +size_t test_sf_vsettn_e8w1(size_t tn) { + return __riscv_sf_vsettn_e8w1(tn); +} + +// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettn_e8w2( +// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettnt.i64(i64 [[TN]], i64 0, i64 2) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +size_t test_sf_vsettn_e8w2(size_t tn) { + return __riscv_sf_vsettn_e8w2(tn); +} + +// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettn_e8w4( +// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettnt.i64(i64 [[TN]], i64 0, i64 3) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +size_t test_sf_vsettn_e8w4(size_t tn) { + return __riscv_sf_vsettn_e8w4(tn); +} + +// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettn_e16w1( +// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettnt.i64(i64 [[TN]], i64 1, i64 1) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +size_t test_sf_vsettn_e16w1(size_t tn) { + return __riscv_sf_vsettn_e16w1(tn); +} + +// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettn_e16w2( +// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettnt.i64(i64 [[TN]], i64 1, i64 2) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +size_t test_sf_vsettn_e16w2(size_t tn) { + return __riscv_sf_vsettn_e16w2(tn); +} + +// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettn_e16w4( +// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettnt.i64(i64 [[TN]], i64 1, i64 3) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +size_t test_sf_vsettn_e16w4(size_t tn) { + return __riscv_sf_vsettn_e16w4(tn); +} + +// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettn_e32w1( +// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettnt.i64(i64 [[TN]], i64 2, i64 1) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +size_t test_sf_vsettn_e32w1(size_t tn) { + return __riscv_sf_vsettn_e32w1(tn); +} + +// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettn_e32w2( +// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettnt.i64(i64 [[TN]], i64 2, i64 2) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +size_t test_sf_vsettn_e32w2(size_t tn) { + return __riscv_sf_vsettn_e32w2(tn); +} + +// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettn_e64w1( +// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettnt.i64(i64 [[TN]], i64 3, i64 1) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +size_t test_sf_vsettn_e64w1(size_t tn) { + return __riscv_sf_vsettn_e64w1(tn); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c new file mode 100644 index 0000000000000..29eaec3668c4f --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c @@ -0,0 +1,99 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmmbase \ +// RUN: -target-feature +zve64x \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettnt_e8w1( +// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettnt.i64(i64 [[TN]], i64 0, i64 1) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +size_t test_sf_vsettnt_e8w1(size_t tn) { + return __riscv_sf_vsettnt_e8w1(tn); +} + +// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettnt_e8w2( +// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettnt.i64(i64 [[TN]], i64 0, i64 2) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +size_t test_sf_vsettnt_e8w2(size_t tn) { + return __riscv_sf_vsettnt_e8w2(tn); +} + +// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettnt_e8w4( +// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettnt.i64(i64 [[TN]], i64 0, i64 3) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +size_t test_sf_vsettnt_e8w4(size_t tn) { + return __riscv_sf_vsettnt_e8w4(tn); +} + +// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettnt_e16w1( +// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettnt.i64(i64 [[TN]], i64 1, i64 1) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +size_t test_sf_vsettnt_e16w1(size_t tn) { + return __riscv_sf_vsettnt_e16w1(tn); +} + +// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettnt_e16w2( +// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettnt.i64(i64 [[TN]], i64 1, i64 2) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +size_t test_sf_vsettnt_e16w2(size_t tn) { + return __riscv_sf_vsettnt_e16w2(tn); +} + +// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettnt_e16w4( +// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettnt.i64(i64 [[TN]], i64 1, i64 3) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +size_t test_sf_vsettnt_e16w4(size_t tn) { + return __riscv_sf_vsettnt_e16w4(tn); +} + +// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettnt_e32w1( +// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettnt.i64(i64 [[TN]], i64 2, i64 1) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +size_t test_sf_vsettnt_e32w1(size_t tn) { + return __riscv_sf_vsettnt_e32w1(tn); +} + +// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettnt_e32w2( +// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettnt.i64(i64 [[TN]], i64 2, i64 2) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +size_t test_sf_vsettnt_e32w2(size_t tn) { + return __riscv_sf_vsettnt_e32w2(tn); +} + +// CHECK-RV64-LABEL: define dso_local i64 @test_sf_vsettnt_e64w1( +// CHECK-RV64-SAME: i64 noundef [[TN:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.sf.vsettnt.i64(i64 [[TN]], i64 3, i64 1) +// CHECK-RV64-NEXT: ret i64 [[TMP0]] +// +size_t test_sf_vsettnt_e64w1(size_t tn) { + return __riscv_sf_vsettnt_e64w1(tn); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c new file mode 100644 index 0000000000000..bf50e7fe527dd --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c @@ -0,0 +1,49 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmmbase \ +// RUN: -target-feature +zvfhmin -target-feature +zvfbfmin \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vste16_bf16( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vste16.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vste16_bf16(size_t tss, __bf16 *base, size_t vl) { + return __riscv_sf_vste16_bf16(tss, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vste16_f16( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vste16.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vste16_f16(size_t tss, _Float16 *base, size_t vl) { + return __riscv_sf_vste16_f16(tss, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vste16_i16( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vste16.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vste16_i16(size_t tss, int16_t *base, size_t vl) { + return __riscv_sf_vste16_i16(tss, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vste16_u16( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vste16.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vste16_u16(size_t tss, uint16_t *base, size_t vl) { + return __riscv_sf_vste16_u16(tss, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c new file mode 100644 index 0000000000000..d1d7191f2b11d --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c @@ -0,0 +1,38 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmmbase \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vste32_f32( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vste32.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vste32_f32(size_t tss, float *base, size_t vl) { + return __riscv_sf_vste32_f32(tss, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vste32_i32( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vste32.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vste32_i32(size_t tss, int32_t *base, size_t vl) { + return __riscv_sf_vste32_i32(tss, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vste32_u32( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vste32.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vste32_u32(size_t tss, uint32_t *base, size_t vl) { + return __riscv_sf_vste32_u32(tss, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c new file mode 100644 index 0000000000000..4c7d4b18b30f9 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c @@ -0,0 +1,38 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmmbase \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vste64_f64( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vste64.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vste64_f64(size_t tss, double *base, size_t vl) { + return __riscv_sf_vste64_f64(tss, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vste64_i64( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vste64.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vste64_i64(size_t tss, int64_t *base, size_t vl) { + return __riscv_sf_vste64_i64(tss, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vste64_u64( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vste64.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vste64_u64(size_t tss, uint64_t *base, size_t vl) { + return __riscv_sf_vste64_u64(tss, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c new file mode 100644 index 0000000000000..d03bc61c49f90 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c @@ -0,0 +1,28 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmmbase \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vste8_i8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vste8.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vste8_i8(size_t tss, int8_t *base, size_t vl) { + return __riscv_sf_vste8_i8(tss, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vste8_u8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vste8.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vste8_u8(size_t tss, uint8_t *base, size_t vl) { + return __riscv_sf_vste8_u8(tss, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c new file mode 100644 index 0000000000000..7eef2c927934d --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c @@ -0,0 +1,18 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmmbase \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vtdiscard( +// CHECK-RV64-SAME: ) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vtdiscard() +// CHECK-RV64-NEXT: ret void +// +void test_sf_vtdiscard() { + return __riscv_sf_vtdiscard(); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c new file mode 100644 index 0000000000000..37ee503391132 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c @@ -0,0 +1,130 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmmbase \ +// RUN: -target-feature +zvfhmin -target-feature +zvfbfmin \ +// RUN: -target-feature +zve64d \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vtmv_t_v_bf16m8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vtmv.t.v.nxv32bf16.i64(i64 [[TSS]], [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vtmv_t_v_bf16m8(size_t tss, vbfloat16m8_t src, size_t vl) { + return __riscv_sf_vtmv_t_v_bf16m8(tss, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vtmv_t_v_f16m8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vtmv.t.v.nxv32f16.i64(i64 [[TSS]], [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vtmv_t_v_f16m8(size_t tss, vfloat16m8_t src, size_t vl) { + return __riscv_sf_vtmv_t_v_f16m8(tss, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vtmv_t_v_f32m8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vtmv.t.v.nxv16f32.i64(i64 [[TSS]], [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vtmv_t_v_f32m8(size_t tss, vfloat32m8_t src, size_t vl) { + return __riscv_sf_vtmv_t_v_f32m8(tss, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vtmv_t_v_f64m8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vtmv.t.v.nxv8f64.i64(i64 [[TSS]], [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vtmv_t_v_f64m8(size_t tss, vfloat64m8_t src, size_t vl) { + return __riscv_sf_vtmv_t_v_f64m8(tss, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vtmv_t_v_i8m8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 [[TSS]], [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vtmv_t_v_i8m8(size_t tss, vint8m8_t src, size_t vl) { + return __riscv_sf_vtmv_t_v_i8m8(tss, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vtmv_t_v_i16m8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64 [[TSS]], [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vtmv_t_v_i16m8(size_t tss, vint16m8_t src, size_t vl) { + return __riscv_sf_vtmv_t_v_i16m8(tss, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vtmv_t_v_i32m8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64 [[TSS]], [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vtmv_t_v_i32m8(size_t tss, vint32m8_t src, size_t vl) { + return __riscv_sf_vtmv_t_v_i32m8(tss, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vtmv_t_v_i64m8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64 [[TSS]], [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vtmv_t_v_i64m8(size_t tss, vint64m8_t src, size_t vl) { + return __riscv_sf_vtmv_t_v_i64m8(tss, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vtmv_t_v_u8m8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 [[TSS]], [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vtmv_t_v_u8m8(size_t tss, vuint8m8_t src, size_t vl) { + return __riscv_sf_vtmv_t_v_u8m8(tss, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vtmv_t_v_u16m8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64 [[TSS]], [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vtmv_t_v_u16m8(size_t tss, vuint16m8_t src, size_t vl) { + return __riscv_sf_vtmv_t_v_u16m8(tss, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vtmv_t_v_u32m8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64 [[TSS]], [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vtmv_t_v_u32m8(size_t tss, vuint32m8_t src, size_t vl) { + return __riscv_sf_vtmv_t_v_u32m8(tss, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vtmv_t_v_u64m8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64 [[TSS]], [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vtmv_t_v_u64m8(size_t tss, vuint64m8_t src, size_t vl) { + return __riscv_sf_vtmv_t_v_u64m8(tss, src, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c new file mode 100644 index 0000000000000..d127cf42173ec --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c @@ -0,0 +1,130 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmmbase \ +// RUN: -target-feature +zvfhmin -target-feature +zvfbfmin \ +// RUN: -target-feature +zve64d \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_sf_vtmv_v_t_bf16m8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vtmv.v.t.nxv32bf16.i64(i64 [[TSS]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_sf_vtmv_v_t_bf16m8(size_t tss, size_t vl) { + return __riscv_sf_vtmv_v_t_bf16m8(tss, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vtmv_v_t_f16m8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vtmv.v.t.nxv32f16.i64(i64 [[TSS]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m8_t test_sf_vtmv_v_t_f16m8(size_t tss, size_t vl) { + return __riscv_sf_vtmv_v_t_f16m8(tss, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vtmv_v_t_f32m8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vtmv.v.t.nxv16f32.i64(i64 [[TSS]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m8_t test_sf_vtmv_v_t_f32m8(size_t tss, size_t vl) { + return __riscv_sf_vtmv_v_t_f32m8(tss, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vtmv_v_t_f64m8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vtmv.v.t.nxv8f64.i64(i64 [[TSS]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m8_t test_sf_vtmv_v_t_f64m8(size_t tss, size_t vl) { + return __riscv_sf_vtmv_v_t_f64m8(tss, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vtmv_v_t_i8m8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 [[TSS]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m8_t test_sf_vtmv_v_t_i8m8(size_t tss, size_t vl) { + return __riscv_sf_vtmv_v_t_i8m8(tss, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vtmv_v_t_i16m8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vtmv.v.t.nxv32i16.i64(i64 [[TSS]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m8_t test_sf_vtmv_v_t_i16m8(size_t tss, size_t vl) { + return __riscv_sf_vtmv_v_t_i16m8(tss, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vtmv_v_t_i32m8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vtmv.v.t.nxv16i32.i64(i64 [[TSS]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_sf_vtmv_v_t_i32m8(size_t tss, size_t vl) { + return __riscv_sf_vtmv_v_t_i32m8(tss, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vtmv_v_t_i64m8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vtmv.v.t.nxv8i64.i64(i64 [[TSS]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m8_t test_sf_vtmv_v_t_i64m8(size_t tss, size_t vl) { + return __riscv_sf_vtmv_v_t_i64m8(tss, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vtmv_v_t_u8m8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 [[TSS]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m8_t test_sf_vtmv_v_t_u8m8(size_t tss, size_t vl) { + return __riscv_sf_vtmv_v_t_u8m8(tss, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vtmv_v_t_u16m8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vtmv.v.t.nxv32i16.i64(i64 [[TSS]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_sf_vtmv_v_t_u16m8(size_t tss, size_t vl) { + return __riscv_sf_vtmv_v_t_u16m8(tss, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vtmv_v_t_u32m8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vtmv.v.t.nxv16i32.i64(i64 [[TSS]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_sf_vtmv_v_t_u32m8(size_t tss, size_t vl) { + return __riscv_sf_vtmv_v_t_u32m8(tss, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_sf_vtmv_v_t_u64m8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vtmv.v.t.nxv8i64.i64(i64 [[TSS]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_sf_vtmv_v_t_u64m8(size_t tss, size_t vl) { + return __riscv_sf_vtmv_v_t_u64m8(tss, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c new file mode 100644 index 0000000000000..1e4de48d321a3 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c @@ -0,0 +1,99 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmmbase \ +// RUN: -target-feature +zve64x \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vtzero_t_e8w1( +// CHECK-RV64-SAME: i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 [[TM]], i64 [[TN]], i64 3, i64 1) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vtzero_t_e8w1(size_t tm, size_t tn) { + return __riscv_sf_vtzero_t_e8w1(0, tm, tn); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vtzero_t_e8w2( +// CHECK-RV64-SAME: i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 [[TM]], i64 [[TN]], i64 3, i64 2) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vtzero_t_e8w2(size_t tm, size_t tn) { + return __riscv_sf_vtzero_t_e8w2(0, tm, tn); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vtzero_t_e8w4( +// CHECK-RV64-SAME: i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 [[TM]], i64 [[TN]], i64 3, i64 4) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vtzero_t_e8w4(size_t tm, size_t tn) { + return __riscv_sf_vtzero_t_e8w4(0, tm, tn); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vtzero_t_e16w1( +// CHECK-RV64-SAME: i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 [[TM]], i64 [[TN]], i64 4, i64 1) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vtzero_t_e16w1(size_t tm, size_t tn) { + return __riscv_sf_vtzero_t_e16w1(0, tm, tn); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vtzero_t_e16w2( +// CHECK-RV64-SAME: i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 [[TM]], i64 [[TN]], i64 4, i64 2) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vtzero_t_e16w2(size_t tm, size_t tn) { + return __riscv_sf_vtzero_t_e16w2(0, tm, tn); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vtzero_t_e16w4( +// CHECK-RV64-SAME: i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 [[TM]], i64 [[TN]], i64 4, i64 4) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vtzero_t_e16w4(size_t tm, size_t tn) { + return __riscv_sf_vtzero_t_e16w4(0, tm, tn); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vtzero_t_e32w1( +// CHECK-RV64-SAME: i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 [[TM]], i64 [[TN]], i64 5, i64 1) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vtzero_t_e32w1(size_t tm, size_t tn) { + return __riscv_sf_vtzero_t_e32w1(0, tm, tn); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vtzero_t_e32w2( +// CHECK-RV64-SAME: i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 [[TM]], i64 [[TN]], i64 5, i64 2) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vtzero_t_e32w2(size_t tm, size_t tn) { + return __riscv_sf_vtzero_t_e32w2(0, tm, tn); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vtzero_t_e64w1( +// CHECK-RV64-SAME: i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 [[TM]], i64 [[TN]], i64 6, i64 1) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vtzero_t_e64w1(size_t tm, size_t tn) { + return __riscv_sf_vtzero_t_e64w1(0, tm, tn); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c new file mode 100644 index 0000000000000..eee0397de2d6d --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c @@ -0,0 +1,18 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmm32a8f \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_e4m3_e4m3_w4_u8m8_u8m8( +// CHECK-RV64-SAME: [[V1:%.*]], [[V2:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 0, [[V1]], [[V2]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 4) +// CHECK-RV64-NEXT: ret void +// +void test_sf_mm_e4m3_e4m3_w4_u8m8_u8m8(vuint8m8_t v1, vuint8m8_t v2, size_t tm, size_t tn, size_t tk) { + return __riscv_sf_mm_e4m3_e4m3(0, v1, v2, tm, tn, tk); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c new file mode 100644 index 0000000000000..ae723fca1248c --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c @@ -0,0 +1,18 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmm32a8f \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_e4m3_e5m2_w4_u8m8_u8m8( +// CHECK-RV64-SAME: [[V1:%.*]], [[V2:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.e4m3.e5m2.i64.nxv64i8(i64 0, [[V1]], [[V2]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 4) +// CHECK-RV64-NEXT: ret void +// +void test_sf_mm_e4m3_e5m2_w4_u8m8_u8m8(vuint8m8_t v1, vuint8m8_t v2, size_t tm, size_t tn, size_t tk) { + return __riscv_sf_mm_e4m3_e5m2(0, v1, v2, tm, tn, tk); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c new file mode 100644 index 0000000000000..8d985df0aa075 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c @@ -0,0 +1,18 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmm32a8f \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_e5m2_e4m3_w4_u8m8_u8m8( +// CHECK-RV64-SAME: [[V1:%.*]], [[V2:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.e5m2.e4m3.i64.nxv64i8(i64 0, [[V1]], [[V2]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 4) +// CHECK-RV64-NEXT: ret void +// +void test_sf_mm_e5m2_e4m3_w4_u8m8_u8m8(vuint8m8_t v1, vuint8m8_t v2, size_t tm, size_t tn, size_t tk) { + return __riscv_sf_mm_e5m2_e4m3(0, v1, v2, tm, tn, tk); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c new file mode 100644 index 0000000000000..571df0531cefe --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c @@ -0,0 +1,18 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmm32a8f \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_e5m2_e5m2_w4_u8m8_u8m8( +// CHECK-RV64-SAME: [[V1:%.*]], [[V2:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.e5m2.e5m2.i64.nxv64i8(i64 0, [[V1]], [[V2]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 4) +// CHECK-RV64-NEXT: ret void +// +void test_sf_mm_e5m2_e5m2_w4_u8m8_u8m8(vuint8m8_t v1, vuint8m8_t v2, size_t tm, size_t tn, size_t tk) { + return __riscv_sf_mm_e5m2_e5m2(0, v1, v2, tm, tn, tk); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c new file mode 100644 index 0000000000000..b8f324dd89493 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c @@ -0,0 +1,40 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmm32a16f \ +// RUN: -target-feature +xsfmm32a32f -target-feature +xsfmm64a64f \ +// RUN: -target-feature +zvfhmin -target-feature +zve64d -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_f_f_w2_f16m8( +// CHECK-RV64-SAME: [[V1:%.*]], [[V2:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 0, [[V1]], [[V2]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 2) +// CHECK-RV64-NEXT: ret void +// +void test_sf_mm_f_f_w2_f16m8(vfloat16m8_t v1, vfloat16m8_t v2, size_t tm, size_t tn, size_t tk) { + return __riscv_sf_mm_f_f_w2(0, v1, v2, tm, tn, tk); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_f_f_w1_f32m8( +// CHECK-RV64-SAME: [[V1:%.*]], [[V2:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.f.f.i64.nxv16f32(i64 0, [[V1]], [[V2]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 1) +// CHECK-RV64-NEXT: ret void +// +void test_sf_mm_f_f_w1_f32m8(vfloat32m8_t v1, vfloat32m8_t v2, size_t tm, size_t tn, size_t tk) { + return __riscv_sf_mm_f_f_w1(0, v1, v2, tm, tn, tk); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_f_f_w1_f64m8( +// CHECK-RV64-SAME: [[V1:%.*]], [[V2:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.f.f.i64.nxv8f64(i64 0, [[V1]], [[V2]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 1) +// CHECK-RV64-NEXT: ret void +// +void test_sf_mm_f_f_w1_f64m8(vfloat64m8_t v1, vfloat64m8_t v2, size_t tm, size_t tn, size_t tk) { + return __riscv_sf_mm_f_f_w1(0, v1, v2, tm, tn, tk); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c new file mode 100644 index 0000000000000..5da2c06310a7f --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c @@ -0,0 +1,18 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmm32a8i \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_s_s_w4_i8m8_i8m8( +// CHECK-RV64-SAME: [[V1:%.*]], [[V2:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.s.s.i64.nxv64i8.nxv64i8(i64 0, [[V1]], [[V2]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 4) +// CHECK-RV64-NEXT: ret void +// +void test_sf_mm_s_s_w4_i8m8_i8m8(vint8m8_t v1, vint8m8_t v2, size_t tm, size_t tn, size_t tk) { + return __riscv_sf_mm_s_s(0, v1, v2, tm, tn, tk); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c new file mode 100644 index 0000000000000..2a46af86e0d11 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c @@ -0,0 +1,18 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmm32a8i \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_s_u_w4_i8m8_u8m8( +// CHECK-RV64-SAME: [[V1:%.*]], [[V2:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.s.u.i64.nxv64i8.nxv64i8(i64 0, [[V1]], [[V2]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 4) +// CHECK-RV64-NEXT: ret void +// +void test_sf_mm_s_u_w4_i8m8_u8m8(vint8m8_t v1, vuint8m8_t v2, size_t tm, size_t tn, size_t tk) { + return __riscv_sf_mm_s_u(0, v1, v2, tm, tn, tk); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c new file mode 100644 index 0000000000000..c3583e90677d3 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c @@ -0,0 +1,18 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmm32a8i \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_u_s_w4_u8m8_i8m8( +// CHECK-RV64-SAME: [[V1:%.*]], [[V2:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.u.s.i64.nxv64i8.nxv64i8(i64 0, [[V1]], [[V2]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 4) +// CHECK-RV64-NEXT: ret void +// +void test_sf_mm_u_s_w4_u8m8_i8m8(vuint8m8_t v1, vint8m8_t v2, size_t tm, size_t tn, size_t tk) { + return __riscv_sf_mm_u_s(0, v1, v2, tm, tn, tk); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c new file mode 100644 index 0000000000000..b595eb53c03c6 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c @@ -0,0 +1,18 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmm32a8i \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_u_u_w4_u8m8_u8m8( +// CHECK-RV64-SAME: [[V1:%.*]], [[V2:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.u.u.i64.nxv64i8.nxv64i8(i64 0, [[V1]], [[V2]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 4) +// CHECK-RV64-NEXT: ret void +// +void test_sf_mm_u_u_w4_u8m8_u8m8(vuint8m8_t v1, vuint8m8_t v2, size_t tm, size_t tn, size_t tk) { + return __riscv_sf_mm_u_u(0, v1, v2, tm, tn, tk); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c new file mode 100644 index 0000000000000..e199c1fb35041 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c @@ -0,0 +1,49 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmmbase \ +// RUN: -target-feature +zvfhmin -target-feature +zvfbfmin \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vlte16_bf16( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vlte16.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vlte16_bf16(size_t tss, __bf16 *base, size_t vl) { + return __riscv_sf_vlte16(tss, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vlte16_f16( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vlte16.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vlte16_f16(size_t tss, _Float16 *base, size_t vl) { + return __riscv_sf_vlte16(tss, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vlte16_i16( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vlte16.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vlte16_i16(size_t tss, int16_t *base, size_t vl) { + return __riscv_sf_vlte16(tss, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vlte16_u16( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vlte16.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vlte16_u16(size_t tss, uint16_t *base, size_t vl) { + return __riscv_sf_vlte16(tss, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c new file mode 100644 index 0000000000000..388884d91f0d0 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c @@ -0,0 +1,38 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmmbase \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vlte32_f32( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vlte32.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vlte32_f32(size_t tss, float *base, size_t vl) { + return __riscv_sf_vlte32(tss, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vlte32_i32( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vlte32.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vlte32_i32(size_t tss, int32_t *base, size_t vl) { + return __riscv_sf_vlte32(tss, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vlte32_u32( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vlte32.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vlte32_u32(size_t tss, uint32_t *base, size_t vl) { + return __riscv_sf_vlte32(tss, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c new file mode 100644 index 0000000000000..80d7542f10585 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c @@ -0,0 +1,38 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmmbase \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vlte64_f64( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vlte64.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vlte64_f64(size_t tss, double *base, size_t vl) { + return __riscv_sf_vlte64(tss, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vlte64_i64( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vlte64.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vlte64_i64(size_t tss, int64_t *base, size_t vl) { + return __riscv_sf_vlte64(tss, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vlte64_u64( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vlte64.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vlte64_u64(size_t tss, uint64_t *base, size_t vl) { + return __riscv_sf_vlte64(tss, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c new file mode 100644 index 0000000000000..c29bf933cf85c --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c @@ -0,0 +1,28 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmmbase \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vlte8_i8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vlte8.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vlte8_i8(size_t tss, int8_t *base, size_t vl) { + return __riscv_sf_vlte8(tss, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vlte8_u8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vlte8.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vlte8_u8(size_t tss, uint8_t *base, size_t vl) { + return __riscv_sf_vlte8(tss, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c new file mode 100644 index 0000000000000..e1fff6c95ce03 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c @@ -0,0 +1,49 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmmbase \ +// RUN: -target-feature +zvfhmin -target-feature +zvfbfmin \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vste16_bf16( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vste16.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vste16_bf16(size_t tss, __bf16 *base, size_t vl) { + return __riscv_sf_vste16(tss, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vste16_f16( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vste16.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vste16_f16(size_t tss, _Float16 *base, size_t vl) { + return __riscv_sf_vste16(tss, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vste16_i16( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vste16.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vste16_i16(size_t tss, int16_t *base, size_t vl) { + return __riscv_sf_vste16(tss, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vste16_u16( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vste16.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vste16_u16(size_t tss, uint16_t *base, size_t vl) { + return __riscv_sf_vste16(tss, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c new file mode 100644 index 0000000000000..0c3bc4ce95912 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c @@ -0,0 +1,38 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmmbase \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vste32_f32( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vste32.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vste32_f32(size_t tss, float *base, size_t vl) { + return __riscv_sf_vste32(tss, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vste32_i32( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vste32.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vste32_i32(size_t tss, int32_t *base, size_t vl) { + return __riscv_sf_vste32(tss, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vste32_u32( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vste32.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vste32_u32(size_t tss, uint32_t *base, size_t vl) { + return __riscv_sf_vste32(tss, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c new file mode 100644 index 0000000000000..0a568073e1ab9 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c @@ -0,0 +1,38 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmmbase \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vste64_f64( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vste64.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vste64_f64(size_t tss, double *base, size_t vl) { + return __riscv_sf_vste64(tss, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vste64_i64( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vste64.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vste64_i64(size_t tss, int64_t *base, size_t vl) { + return __riscv_sf_vste64(tss, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vste64_u64( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vste64.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vste64_u64(size_t tss, uint64_t *base, size_t vl) { + return __riscv_sf_vste64(tss, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c new file mode 100644 index 0000000000000..3115945796ba0 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c @@ -0,0 +1,28 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmmbase \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vste8_i8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vste8.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vste8_i8(size_t tss, int8_t *base, size_t vl) { + return __riscv_sf_vste8(tss, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vste8_u8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vste8.i64(i64 [[TSS]], ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vste8_u8(size_t tss, uint8_t *base, size_t vl) { + return __riscv_sf_vste8(tss, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c new file mode 100644 index 0000000000000..2461c39c64c56 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c @@ -0,0 +1,130 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmmbase \ +// RUN: -target-feature +zvfhmin -target-feature +zvfbfmin \ +// RUN: -target-feature +zve64d \ +// RUN: -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vtmv_t_v_bf16m8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vtmv.t.v.nxv32bf16.i64(i64 [[TSS]], [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vtmv_t_v_bf16m8(size_t tss, vbfloat16m8_t src, size_t vl) { + return __riscv_sf_vtmv_t_v(tss, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vtmv_t_v_f16m8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vtmv.t.v.nxv32f16.i64(i64 [[TSS]], [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vtmv_t_v_f16m8(size_t tss, vfloat16m8_t src, size_t vl) { + return __riscv_sf_vtmv_t_v(tss, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vtmv_t_v_f32m8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vtmv.t.v.nxv16f32.i64(i64 [[TSS]], [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vtmv_t_v_f32m8(size_t tss, vfloat32m8_t src, size_t vl) { + return __riscv_sf_vtmv_t_v(tss, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vtmv_t_v_f64m8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vtmv.t.v.nxv8f64.i64(i64 [[TSS]], [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vtmv_t_v_f64m8(size_t tss, vfloat64m8_t src, size_t vl) { + return __riscv_sf_vtmv_t_v(tss, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vtmv_t_v_i8m8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 [[TSS]], [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vtmv_t_v_i8m8(size_t tss, vint8m8_t src, size_t vl) { + return __riscv_sf_vtmv_t_v(tss, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vtmv_t_v_i16m8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64 [[TSS]], [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vtmv_t_v_i16m8(size_t tss, vint16m8_t src, size_t vl) { + return __riscv_sf_vtmv_t_v(tss, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vtmv_t_v_i32m8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64 [[TSS]], [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vtmv_t_v_i32m8(size_t tss, vint32m8_t src, size_t vl) { + return __riscv_sf_vtmv_t_v(tss, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vtmv_t_v_i64m8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64 [[TSS]], [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vtmv_t_v_i64m8(size_t tss, vint64m8_t src, size_t vl) { + return __riscv_sf_vtmv_t_v(tss, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vtmv_t_v_u8m8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 [[TSS]], [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vtmv_t_v_u8m8(size_t tss, vuint8m8_t src, size_t vl) { + return __riscv_sf_vtmv_t_v(tss, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vtmv_t_v_u16m8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64 [[TSS]], [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vtmv_t_v_u16m8(size_t tss, vuint16m8_t src, size_t vl) { + return __riscv_sf_vtmv_t_v(tss, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vtmv_t_v_u32m8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64 [[TSS]], [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vtmv_t_v_u32m8(size_t tss, vuint32m8_t src, size_t vl) { + return __riscv_sf_vtmv_t_v(tss, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_sf_vtmv_t_v_u64m8( +// CHECK-RV64-SAME: i64 noundef [[TSS:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64 [[TSS]], [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vtmv_t_v_u64m8(size_t tss, vuint64m8_t src, size_t vl) { + return __riscv_sf_vtmv_t_v(tss, src, vl); +} + diff --git a/clang/test/Sema/sifive-xsfmm.c b/clang/test/Sema/sifive-xsfmm.c new file mode 100644 index 0000000000000..2257f6176ca75 --- /dev/null +++ b/clang/test/Sema/sifive-xsfmm.c @@ -0,0 +1,17 @@ +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +xsfmmbase -target-feature +xsfmm32a -target-feature +xsfmm32a8f \ +// RUN: -target-feature +xsfmm32a16f -target-feature +xsfmm32a32f -target-feature +xsfmm64a64f \ +// RUN: -target-feature +xsfmm32a4f -target-feature +xsfmm32a8i -disable-O0-optnone \ +// RUN: -fsyntax-only %s -verify +// REQUIRES: riscv-registered-target +#include + +void test(vfloat32m8_t arg0, vuint8m8_t arg1) { + __riscv_sf_mm_f_f_w1(4, arg0, arg0, 1, 2, 3); + __riscv_sf_mm_e5m2_e4m3(8, arg1, arg1, 1, 2, 3); + __riscv_sf_mm_u_u(12, arg1, arg1, 1, 2, 3); + + __riscv_sf_mm_f_f_w1(5, arg0, arg0, 1, 2, 3); /* expected-error {{argument should be a multiple of 4}} */ + __riscv_sf_mm_e5m2_e4m3(7, arg1, arg1, 1, 2, 3); /* expected-error {{argument should be a multiple of 4}} */ + __riscv_sf_mm_u_u(15, arg1, arg1, 1, 2, 3); /* expected-error {{argument should be a multiple of 4}} */ +} diff --git a/clang/test/Sema/sifive_sf_vset_invalid.c b/clang/test/Sema/sifive_sf_vset_invalid.c new file mode 100644 index 0000000000000..96d8e0d2a6b1d --- /dev/null +++ b/clang/test/Sema/sifive_sf_vset_invalid.c @@ -0,0 +1,17 @@ +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +xsfmmbase -disable-O0-optnone \ +// RUN: -o - -fsyntax-only %s -verify + +#include + +void test(size_t vl) { + __riscv_sf_vsettnt(vl, 1, 8); + // expected-error@-1 {{argument value 8 is outside the valid range [1, 3]}} + __riscv_sf_vsettm(vl, 8, 9); + // expected-error@-1 {{argument value 8 is outside the valid range [0, 3]}} + __riscv_sf_vsettn(vl, 8, 2); + // expected-error@-1 {{argument value 8 is outside the valid range [0, 3]}} + __riscv_sf_vsettk(vl, 0, 0); + // expected-error@-1 {{argument value 0 is outside the valid range [1, 3]}} +} diff --git a/clang/utils/TableGen/RISCVVEmitter.cpp b/clang/utils/TableGen/RISCVVEmitter.cpp index c58f66568a315..da45137acf3e4 100644 --- a/clang/utils/TableGen/RISCVVEmitter.cpp +++ b/clang/utils/TableGen/RISCVVEmitter.cpp @@ -247,6 +247,8 @@ static unsigned getSegInstLog2SEW(StringRef InstName) { void emitCodeGenSwitchBody(const RVVIntrinsic *RVVI, raw_ostream &OS) { if (!RVVI->getIRName().empty()) OS << " ID = Intrinsic::riscv_" + RVVI->getIRName() + ";\n"; + if (RVVI->getTWiden() > 0) + OS << " TWiden = " << RVVI->getTWiden() << ";\n"; OS << " PolicyAttrs = " << RVVI->getPolicyAttrsBits() << ";\n"; OS << " SegInstSEW = " << getSegInstLog2SEW(RVVI->getOverloadedName()) @@ -299,6 +301,9 @@ void emitCodeGenSwitchBody(const RVVIntrinsic *RVVI, raw_ostream &OS) { OS << " Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));\n"; } + if (RVVI->getTWiden() > 0) + OS << " Ops.push_back(ConstantInt::get(Ops.back()->getType(), TWiden));\n"; + OS << " IntrinsicTypes = {"; ListSeparator LS; for (const auto &Idx : RVVI->getIntrinsicTypes()) { @@ -587,7 +592,8 @@ void RVVEmitter::createCodeGen(raw_ostream &OS) { (Def->getManualCodegen() != PrevDef->getManualCodegen()) || (Def->getPolicyAttrs() != PrevDef->getPolicyAttrs()) || (getSegInstLog2SEW(Def->getOverloadedName()) != - getSegInstLog2SEW(PrevDef->getOverloadedName()))) { + getSegInstLog2SEW(PrevDef->getOverloadedName())) || + (Def->getTWiden() != PrevDef->getTWiden())) { emitCodeGenSwitchBody(PrevDef, OS); } PrevDef = Def.get(); @@ -649,6 +655,7 @@ void RVVEmitter::createRVVIntrinsics( StringRef IRName = R->getValueAsString("IRName"); StringRef MaskedIRName = R->getValueAsString("MaskedIRName"); unsigned NF = R->getValueAsInt("NF"); + unsigned TWiden = R->getValueAsInt("TWiden"); bool IsTuple = R->getValueAsBit("IsTuple"); bool HasFRMRoundModeOp = R->getValueAsBit("HasFRMRoundModeOp"); @@ -698,7 +705,7 @@ void RVVEmitter::createRVVIntrinsics( /*IsMasked=*/false, /*HasMaskedOffOperand=*/false, HasVL, UnMaskedPolicyScheme, SupportOverloading, HasBuiltinAlias, ManualCodegen, *Types, IntrinsicTypes, NF, DefaultPolicy, - HasFRMRoundModeOp)); + HasFRMRoundModeOp, TWiden)); if (UnMaskedPolicyScheme != PolicyScheme::SchemeNone) for (auto P : SupportedUnMaskedPolicies) { SmallVector PolicyPrototype = @@ -713,7 +720,7 @@ void RVVEmitter::createRVVIntrinsics( /*IsMask=*/false, /*HasMaskedOffOperand=*/false, HasVL, UnMaskedPolicyScheme, SupportOverloading, HasBuiltinAlias, ManualCodegen, *PolicyTypes, IntrinsicTypes, NF, P, - HasFRMRoundModeOp)); + HasFRMRoundModeOp, TWiden)); } if (!HasMasked) continue; @@ -724,7 +731,7 @@ void RVVEmitter::createRVVIntrinsics( Name, SuffixStr, OverloadedName, OverloadedSuffixStr, MaskedIRName, /*IsMasked=*/true, HasMaskedOffOperand, HasVL, MaskedPolicyScheme, SupportOverloading, HasBuiltinAlias, ManualCodegen, *MaskTypes, - IntrinsicTypes, NF, DefaultPolicy, HasFRMRoundModeOp)); + IntrinsicTypes, NF, DefaultPolicy, HasFRMRoundModeOp, TWiden)); if (MaskedPolicyScheme == PolicyScheme::SchemeNone) continue; for (auto P : SupportedMaskedPolicies) { @@ -739,7 +746,7 @@ void RVVEmitter::createRVVIntrinsics( MaskedIRName, /*IsMasked=*/true, HasMaskedOffOperand, HasVL, MaskedPolicyScheme, SupportOverloading, HasBuiltinAlias, ManualCodegen, *PolicyTypes, IntrinsicTypes, NF, P, - HasFRMRoundModeOp)); + HasFRMRoundModeOp, TWiden)); } } // End for Log2LMULList } // End for TypeRange @@ -793,6 +800,12 @@ void RVVEmitter::createRVVIntrinsics( .Case("Zvfbfwma", RVV_REQ_Zvfbfwma) .Case("Zvfbfmin", RVV_REQ_Zvfbfmin) .Case("Zvfh", RVV_REQ_Zvfh) + .Case("Xsfmmbase", RVV_REQ_Xsfmmbase) + .Case("Xsfmm32a8f", RVV_REQ_Xsfmm32a8f) + .Case("Xsfmm32a16f", RVV_REQ_Xsfmm32a16f) + .Case("Xsfmm32a32f", RVV_REQ_Xsfmm32a32f) + .Case("Xsfmm64a64f", RVV_REQ_Xsfmm64a64f) + .Case("Xsfmm32a8i", RVV_REQ_Xsfmm32a8i) .Case("Experimental", RVV_REQ_Experimental); SR.RequiredExtensions.set(RequireExt); }