diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp index 66d26bf5b11e2..fc3300247b190 100644 --- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp +++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp @@ -1313,6 +1313,12 @@ bool RISCVVLOptimizer::tryReduceVL(MachineInstr &MI) { return false; } + if (CommonVL->isIdenticalTo(VLOp)) { + LLVM_DEBUG( + dbgs() << " Abort due to CommonVL == VLOp, no point in reducing.\n"); + return false; + } + if (CommonVL->isImm()) { LLVM_DEBUG(dbgs() << " Reduce VL from " << VLOp << " to " << CommonVL->getImm() << " for " << MI << "\n"); diff --git a/llvm/test/CodeGen/RISCV/rvv/vlopt-same-vl.ll b/llvm/test/CodeGen/RISCV/rvv/vlopt-same-vl.ll new file mode 100644 index 0000000000000..65e6eddfb3cd6 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/vlopt-same-vl.ll @@ -0,0 +1,27 @@ +; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-enable-vl-optimizer \ +; RUN: -verify-machineinstrs -debug-only=riscv-vl-optimizer -o - 2>&1 %s | FileCheck %s + +; REQUIRES: asserts + +; GitHub Issue #123862 provided a case where the riscv-vl-optimizer pass was +; very slow. It was found that that case benefited greatly from aborting due +; to CommonVL == VLOp. Adding the case provided in the issue would show up +; as a long running test instead of a test failure. We would likley have a hard +; time figuring if that case had a regression. So instead, we check this output +; which was responsible for speeding it up. + +define @same_vl_imm( %passthru, %a, %b) { + ; CHECK: User VL is: 4 + ; CHECK-NEXT: Abort due to CommonVL == VLOp, no point in reducing. + %v = call @llvm.riscv.vadd.nxv4i32.nxv4i32( poison, %a, %b, i64 4) + %w = call @llvm.riscv.vadd.nxv4i32.nxv4i32( poison, %v, %a, i64 4) + ret %w +} + +define @same_vl_reg( %passthru, %a, %b, i64 %vl) { + ; CHECK: User VL is: %3:gprnox0 + ; CHECK-NEXT: Abort due to CommonVL == VLOp, no point in reducing. + %v = call @llvm.riscv.vadd.nxv4i32.nxv4i32( poison, %a, %b, i64 %vl) + %w = call @llvm.riscv.vadd.nxv4i32.nxv4i32( poison, %v, %a, i64 %vl) + ret %w +}