diff --git a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
index 440413b8c2684..9e174e2415e71 100644
--- a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
+++ b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
@@ -276,7 +276,7 @@ static cl::opt<bool>
 static cl::opt<bool>
     ClHandleICmpExact("msan-handle-icmp-exact",
                       cl::desc("exact handling of relational integer ICmp"),
-                      cl::Hidden, cl::init(true));
+                      cl::Hidden, cl::init(false));
 
 static cl::opt<bool> ClHandleLifetimeIntrinsics(
     "msan-handle-lifetime-intrinsics",
diff --git a/llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll b/llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll
index 7aeb763b30904..809e20dcb4a91 100644
--- a/llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll
@@ -1622,21 +1622,7 @@ define zeroext i1 @ICmpSLTZero(i32 %x) nounwind uwtable readnone sanitize_memory
 ; CHECK-SAME: i32 [[X:%.*]]) #[[ATTR0]] {
 ; CHECK-NEXT:    [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8
 ; CHECK-NEXT:    call void @llvm.donothing()
-; CHECK-NEXT:    [[TMP2:%.*]] = shl i32 [[TMP1]], 1
-; CHECK-NEXT:    [[TMP3:%.*]] = lshr i32 [[TMP2]], 1
-; CHECK-NEXT:    [[TMP4:%.*]] = xor i32 [[TMP1]], [[TMP3]]
-; CHECK-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP3]], -1
-; CHECK-NEXT:    [[TMP6:%.*]] = and i32 [[X]], [[TMP5]]
-; CHECK-NEXT:    [[TMP7:%.*]] = or i32 [[TMP6]], [[TMP4]]
-; CHECK-NEXT:    [[TMP8:%.*]] = icmp slt i32 [[TMP7]], 0
-; CHECK-NEXT:    [[TMP9:%.*]] = shl i32 [[TMP1]], 1
-; CHECK-NEXT:    [[TMP10:%.*]] = lshr i32 [[TMP9]], 1
-; CHECK-NEXT:    [[TMP11:%.*]] = xor i32 [[TMP1]], [[TMP10]]
-; CHECK-NEXT:    [[TMP12:%.*]] = xor i32 [[TMP11]], -1
-; CHECK-NEXT:    [[TMP13:%.*]] = and i32 [[X]], [[TMP12]]
-; CHECK-NEXT:    [[TMP14:%.*]] = or i32 [[TMP13]], [[TMP10]]
-; CHECK-NEXT:    [[TMP15:%.*]] = icmp slt i32 [[TMP14]], 0
-; CHECK-NEXT:    [[TMP16:%.*]] = xor i1 [[TMP8]], [[TMP15]]
+; CHECK-NEXT:    [[TMP16:%.*]] = icmp slt i32 [[TMP1]], 0
 ; CHECK-NEXT:    [[TMP17:%.*]] = icmp slt i32 [[X]], 0
 ; CHECK-NEXT:    store i1 [[TMP16]], ptr @__msan_retval_tls, align 8
 ; CHECK-NEXT:    ret i1 [[TMP17]]
@@ -1646,21 +1632,7 @@ define zeroext i1 @ICmpSLTZero(i32 %x) nounwind uwtable readnone sanitize_memory
 ; ORIGIN-NEXT:    [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8
 ; ORIGIN-NEXT:    [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4
 ; ORIGIN-NEXT:    call void @llvm.donothing()
-; ORIGIN-NEXT:    [[TMP3:%.*]] = shl i32 [[TMP1]], 1
-; ORIGIN-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 1
-; ORIGIN-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]]
-; ORIGIN-NEXT:    [[TMP6:%.*]] = xor i32 [[TMP4]], -1
-; ORIGIN-NEXT:    [[TMP7:%.*]] = and i32 [[X]], [[TMP6]]
-; ORIGIN-NEXT:    [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP5]]
-; ORIGIN-NEXT:    [[TMP9:%.*]] = icmp slt i32 [[TMP8]], 0
-; ORIGIN-NEXT:    [[TMP10:%.*]] = shl i32 [[TMP1]], 1
-; ORIGIN-NEXT:    [[TMP11:%.*]] = lshr i32 [[TMP10]], 1
-; ORIGIN-NEXT:    [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]]
-; ORIGIN-NEXT:    [[TMP13:%.*]] = xor i32 [[TMP12]], -1
-; ORIGIN-NEXT:    [[TMP14:%.*]] = and i32 [[X]], [[TMP13]]
-; ORIGIN-NEXT:    [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP11]]
-; ORIGIN-NEXT:    [[TMP16:%.*]] = icmp slt i32 [[TMP15]], 0
-; ORIGIN-NEXT:    [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]]
+; ORIGIN-NEXT:    [[TMP17:%.*]] = icmp slt i32 [[TMP1]], 0
 ; ORIGIN-NEXT:    [[TMP18:%.*]] = icmp slt i32 [[X]], 0
 ; ORIGIN-NEXT:    store i1 [[TMP17]], ptr @__msan_retval_tls, align 8
 ; ORIGIN-NEXT:    store i32 [[TMP2]], ptr @__msan_retval_origin_tls, align 4
@@ -1671,21 +1643,7 @@ define zeroext i1 @ICmpSLTZero(i32 %x) nounwind uwtable readnone sanitize_memory
 ; CALLS-NEXT:    [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8
 ; CALLS-NEXT:    [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4
 ; CALLS-NEXT:    call void @llvm.donothing()
-; CALLS-NEXT:    [[TMP3:%.*]] = shl i32 [[TMP1]], 1
-; CALLS-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 1
-; CALLS-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]]
-; CALLS-NEXT:    [[TMP6:%.*]] = xor i32 [[TMP4]], -1
-; CALLS-NEXT:    [[TMP7:%.*]] = and i32 [[X]], [[TMP6]]
-; CALLS-NEXT:    [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP5]]
-; CALLS-NEXT:    [[TMP9:%.*]] = icmp slt i32 [[TMP8]], 0
-; CALLS-NEXT:    [[TMP10:%.*]] = shl i32 [[TMP1]], 1
-; CALLS-NEXT:    [[TMP11:%.*]] = lshr i32 [[TMP10]], 1
-; CALLS-NEXT:    [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]]
-; CALLS-NEXT:    [[TMP13:%.*]] = xor i32 [[TMP12]], -1
-; CALLS-NEXT:    [[TMP14:%.*]] = and i32 [[X]], [[TMP13]]
-; CALLS-NEXT:    [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP11]]
-; CALLS-NEXT:    [[TMP16:%.*]] = icmp slt i32 [[TMP15]], 0
-; CALLS-NEXT:    [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]]
+; CALLS-NEXT:    [[TMP17:%.*]] = icmp slt i32 [[TMP1]], 0
 ; CALLS-NEXT:    [[TMP18:%.*]] = icmp slt i32 [[X]], 0
 ; CALLS-NEXT:    store i1 [[TMP17]], ptr @__msan_retval_tls, align 8
 ; CALLS-NEXT:    store i32 [[TMP2]], ptr @__msan_retval_origin_tls, align 4
@@ -1701,21 +1659,7 @@ define zeroext i1 @ICmpSGEZero(i32 %x) nounwind uwtable readnone sanitize_memory
 ; CHECK-SAME: i32 [[X:%.*]]) #[[ATTR0]] {
 ; CHECK-NEXT:    [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8
 ; CHECK-NEXT:    call void @llvm.donothing()
-; CHECK-NEXT:    [[TMP2:%.*]] = shl i32 [[TMP1]], 1
-; CHECK-NEXT:    [[TMP3:%.*]] = lshr i32 [[TMP2]], 1
-; CHECK-NEXT:    [[TMP4:%.*]] = xor i32 [[TMP1]], [[TMP3]]
-; CHECK-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP3]], -1
-; CHECK-NEXT:    [[TMP6:%.*]] = and i32 [[X]], [[TMP5]]
-; CHECK-NEXT:    [[TMP7:%.*]] = or i32 [[TMP6]], [[TMP4]]
-; CHECK-NEXT:    [[TMP8:%.*]] = icmp sge i32 [[TMP7]], 0
-; CHECK-NEXT:    [[TMP9:%.*]] = shl i32 [[TMP1]], 1
-; CHECK-NEXT:    [[TMP10:%.*]] = lshr i32 [[TMP9]], 1
-; CHECK-NEXT:    [[TMP11:%.*]] = xor i32 [[TMP1]], [[TMP10]]
-; CHECK-NEXT:    [[TMP12:%.*]] = xor i32 [[TMP11]], -1
-; CHECK-NEXT:    [[TMP13:%.*]] = and i32 [[X]], [[TMP12]]
-; CHECK-NEXT:    [[TMP14:%.*]] = or i32 [[TMP13]], [[TMP10]]
-; CHECK-NEXT:    [[TMP15:%.*]] = icmp sge i32 [[TMP14]], 0
-; CHECK-NEXT:    [[TMP16:%.*]] = xor i1 [[TMP8]], [[TMP15]]
+; CHECK-NEXT:    [[TMP16:%.*]] = icmp slt i32 [[TMP1]], 0
 ; CHECK-NEXT:    [[TMP17:%.*]] = icmp sge i32 [[X]], 0
 ; CHECK-NEXT:    store i1 [[TMP16]], ptr @__msan_retval_tls, align 8
 ; CHECK-NEXT:    ret i1 [[TMP17]]
@@ -1725,21 +1669,7 @@ define zeroext i1 @ICmpSGEZero(i32 %x) nounwind uwtable readnone sanitize_memory
 ; ORIGIN-NEXT:    [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8
 ; ORIGIN-NEXT:    [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4
 ; ORIGIN-NEXT:    call void @llvm.donothing()
-; ORIGIN-NEXT:    [[TMP3:%.*]] = shl i32 [[TMP1]], 1
-; ORIGIN-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 1
-; ORIGIN-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]]
-; ORIGIN-NEXT:    [[TMP6:%.*]] = xor i32 [[TMP4]], -1
-; ORIGIN-NEXT:    [[TMP7:%.*]] = and i32 [[X]], [[TMP6]]
-; ORIGIN-NEXT:    [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP5]]
-; ORIGIN-NEXT:    [[TMP9:%.*]] = icmp sge i32 [[TMP8]], 0
-; ORIGIN-NEXT:    [[TMP10:%.*]] = shl i32 [[TMP1]], 1
-; ORIGIN-NEXT:    [[TMP11:%.*]] = lshr i32 [[TMP10]], 1
-; ORIGIN-NEXT:    [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]]
-; ORIGIN-NEXT:    [[TMP13:%.*]] = xor i32 [[TMP12]], -1
-; ORIGIN-NEXT:    [[TMP14:%.*]] = and i32 [[X]], [[TMP13]]
-; ORIGIN-NEXT:    [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP11]]
-; ORIGIN-NEXT:    [[TMP16:%.*]] = icmp sge i32 [[TMP15]], 0
-; ORIGIN-NEXT:    [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]]
+; ORIGIN-NEXT:    [[TMP17:%.*]] = icmp slt i32 [[TMP1]], 0
 ; ORIGIN-NEXT:    [[TMP18:%.*]] = icmp sge i32 [[X]], 0
 ; ORIGIN-NEXT:    store i1 [[TMP17]], ptr @__msan_retval_tls, align 8
 ; ORIGIN-NEXT:    store i32 [[TMP2]], ptr @__msan_retval_origin_tls, align 4
@@ -1750,21 +1680,7 @@ define zeroext i1 @ICmpSGEZero(i32 %x) nounwind uwtable readnone sanitize_memory
 ; CALLS-NEXT:    [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8
 ; CALLS-NEXT:    [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4
 ; CALLS-NEXT:    call void @llvm.donothing()
-; CALLS-NEXT:    [[TMP3:%.*]] = shl i32 [[TMP1]], 1
-; CALLS-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 1
-; CALLS-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]]
-; CALLS-NEXT:    [[TMP6:%.*]] = xor i32 [[TMP4]], -1
-; CALLS-NEXT:    [[TMP7:%.*]] = and i32 [[X]], [[TMP6]]
-; CALLS-NEXT:    [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP5]]
-; CALLS-NEXT:    [[TMP9:%.*]] = icmp sge i32 [[TMP8]], 0
-; CALLS-NEXT:    [[TMP10:%.*]] = shl i32 [[TMP1]], 1
-; CALLS-NEXT:    [[TMP11:%.*]] = lshr i32 [[TMP10]], 1
-; CALLS-NEXT:    [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]]
-; CALLS-NEXT:    [[TMP13:%.*]] = xor i32 [[TMP12]], -1
-; CALLS-NEXT:    [[TMP14:%.*]] = and i32 [[X]], [[TMP13]]
-; CALLS-NEXT:    [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP11]]
-; CALLS-NEXT:    [[TMP16:%.*]] = icmp sge i32 [[TMP15]], 0
-; CALLS-NEXT:    [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]]
+; CALLS-NEXT:    [[TMP17:%.*]] = icmp slt i32 [[TMP1]], 0
 ; CALLS-NEXT:    [[TMP18:%.*]] = icmp sge i32 [[X]], 0
 ; CALLS-NEXT:    store i1 [[TMP17]], ptr @__msan_retval_tls, align 8
 ; CALLS-NEXT:    store i32 [[TMP2]], ptr @__msan_retval_origin_tls, align 4
@@ -1780,21 +1696,7 @@ define zeroext i1 @ICmpSGTZero(i32 %x) nounwind uwtable readnone sanitize_memory
 ; CHECK-SAME: i32 [[X:%.*]]) #[[ATTR0]] {
 ; CHECK-NEXT:    [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8
 ; CHECK-NEXT:    call void @llvm.donothing()
-; CHECK-NEXT:    [[TMP2:%.*]] = shl i32 [[TMP1]], 1
-; CHECK-NEXT:    [[TMP3:%.*]] = lshr i32 [[TMP2]], 1
-; CHECK-NEXT:    [[TMP4:%.*]] = xor i32 [[TMP1]], [[TMP3]]
-; CHECK-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP4]], -1
-; CHECK-NEXT:    [[TMP6:%.*]] = and i32 [[X]], [[TMP5]]
-; CHECK-NEXT:    [[TMP7:%.*]] = or i32 [[TMP6]], [[TMP3]]
-; CHECK-NEXT:    [[TMP8:%.*]] = icmp sgt i32 0, [[TMP7]]
-; CHECK-NEXT:    [[TMP9:%.*]] = shl i32 [[TMP1]], 1
-; CHECK-NEXT:    [[TMP10:%.*]] = lshr i32 [[TMP9]], 1
-; CHECK-NEXT:    [[TMP11:%.*]] = xor i32 [[TMP1]], [[TMP10]]
-; CHECK-NEXT:    [[TMP12:%.*]] = xor i32 [[TMP10]], -1
-; CHECK-NEXT:    [[TMP13:%.*]] = and i32 [[X]], [[TMP12]]
-; CHECK-NEXT:    [[TMP14:%.*]] = or i32 [[TMP13]], [[TMP11]]
-; CHECK-NEXT:    [[TMP15:%.*]] = icmp sgt i32 0, [[TMP14]]
-; CHECK-NEXT:    [[TMP16:%.*]] = xor i1 [[TMP8]], [[TMP15]]
+; CHECK-NEXT:    [[TMP16:%.*]] = icmp slt i32 [[TMP1]], 0
 ; CHECK-NEXT:    [[TMP17:%.*]] = icmp sgt i32 0, [[X]]
 ; CHECK-NEXT:    store i1 [[TMP16]], ptr @__msan_retval_tls, align 8
 ; CHECK-NEXT:    ret i1 [[TMP17]]
@@ -1804,26 +1706,10 @@ define zeroext i1 @ICmpSGTZero(i32 %x) nounwind uwtable readnone sanitize_memory
 ; ORIGIN-NEXT:    [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8
 ; ORIGIN-NEXT:    [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4
 ; ORIGIN-NEXT:    call void @llvm.donothing()
-; ORIGIN-NEXT:    [[TMP3:%.*]] = shl i32 [[TMP1]], 1
-; ORIGIN-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 1
-; ORIGIN-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]]
-; ORIGIN-NEXT:    [[TMP6:%.*]] = xor i32 [[TMP5]], -1
-; ORIGIN-NEXT:    [[TMP7:%.*]] = and i32 [[X]], [[TMP6]]
-; ORIGIN-NEXT:    [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP4]]
-; ORIGIN-NEXT:    [[TMP9:%.*]] = icmp sgt i32 0, [[TMP8]]
-; ORIGIN-NEXT:    [[TMP10:%.*]] = shl i32 [[TMP1]], 1
-; ORIGIN-NEXT:    [[TMP11:%.*]] = lshr i32 [[TMP10]], 1
-; ORIGIN-NEXT:    [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]]
-; ORIGIN-NEXT:    [[TMP13:%.*]] = xor i32 [[TMP11]], -1
-; ORIGIN-NEXT:    [[TMP14:%.*]] = and i32 [[X]], [[TMP13]]
-; ORIGIN-NEXT:    [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP12]]
-; ORIGIN-NEXT:    [[TMP16:%.*]] = icmp sgt i32 0, [[TMP15]]
-; ORIGIN-NEXT:    [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]]
-; ORIGIN-NEXT:    [[TMP18:%.*]] = icmp ne i32 [[TMP1]], 0
-; ORIGIN-NEXT:    [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP2]], i32 0
+; ORIGIN-NEXT:    [[TMP17:%.*]] = icmp slt i32 [[TMP1]], 0
 ; ORIGIN-NEXT:    [[TMP20:%.*]] = icmp sgt i32 0, [[X]]
 ; ORIGIN-NEXT:    store i1 [[TMP17]], ptr @__msan_retval_tls, align 8
-; ORIGIN-NEXT:    store i32 [[TMP19]], ptr @__msan_retval_origin_tls, align 4
+; ORIGIN-NEXT:    store i32 [[TMP2]], ptr @__msan_retval_origin_tls, align 4
 ; ORIGIN-NEXT:    ret i1 [[TMP20]]
 ;
 ; CALLS-LABEL: define zeroext i1 @ICmpSGTZero(
@@ -1831,26 +1717,10 @@ define zeroext i1 @ICmpSGTZero(i32 %x) nounwind uwtable readnone sanitize_memory
 ; CALLS-NEXT:    [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8
 ; CALLS-NEXT:    [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4
 ; CALLS-NEXT:    call void @llvm.donothing()
-; CALLS-NEXT:    [[TMP3:%.*]] = shl i32 [[TMP1]], 1
-; CALLS-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 1
-; CALLS-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]]
-; CALLS-NEXT:    [[TMP6:%.*]] = xor i32 [[TMP5]], -1
-; CALLS-NEXT:    [[TMP7:%.*]] = and i32 [[X]], [[TMP6]]
-; CALLS-NEXT:    [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP4]]
-; CALLS-NEXT:    [[TMP9:%.*]] = icmp sgt i32 0, [[TMP8]]
-; CALLS-NEXT:    [[TMP10:%.*]] = shl i32 [[TMP1]], 1
-; CALLS-NEXT:    [[TMP11:%.*]] = lshr i32 [[TMP10]], 1
-; CALLS-NEXT:    [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]]
-; CALLS-NEXT:    [[TMP13:%.*]] = xor i32 [[TMP11]], -1
-; CALLS-NEXT:    [[TMP14:%.*]] = and i32 [[X]], [[TMP13]]
-; CALLS-NEXT:    [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP12]]
-; CALLS-NEXT:    [[TMP16:%.*]] = icmp sgt i32 0, [[TMP15]]
-; CALLS-NEXT:    [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]]
-; CALLS-NEXT:    [[TMP18:%.*]] = icmp ne i32 [[TMP1]], 0
-; CALLS-NEXT:    [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP2]], i32 0
+; CALLS-NEXT:    [[TMP17:%.*]] = icmp slt i32 [[TMP1]], 0
 ; CALLS-NEXT:    [[TMP20:%.*]] = icmp sgt i32 0, [[X]]
 ; CALLS-NEXT:    store i1 [[TMP17]], ptr @__msan_retval_tls, align 8
-; CALLS-NEXT:    store i32 [[TMP19]], ptr @__msan_retval_origin_tls, align 4
+; CALLS-NEXT:    store i32 [[TMP2]], ptr @__msan_retval_origin_tls, align 4
 ; CALLS-NEXT:    ret i1 [[TMP20]]
 ;
   %1 = icmp sgt i32 0, %x
@@ -1863,21 +1733,7 @@ define zeroext i1 @ICmpSLEZero(i32 %x) nounwind uwtable readnone sanitize_memory
 ; CHECK-SAME: i32 [[X:%.*]]) #[[ATTR0]] {
 ; CHECK-NEXT:    [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8
 ; CHECK-NEXT:    call void @llvm.donothing()
-; CHECK-NEXT:    [[TMP2:%.*]] = shl i32 [[TMP1]], 1
-; CHECK-NEXT:    [[TMP3:%.*]] = lshr i32 [[TMP2]], 1
-; CHECK-NEXT:    [[TMP4:%.*]] = xor i32 [[TMP1]], [[TMP3]]
-; CHECK-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP4]], -1
-; CHECK-NEXT:    [[TMP6:%.*]] = and i32 [[X]], [[TMP5]]
-; CHECK-NEXT:    [[TMP7:%.*]] = or i32 [[TMP6]], [[TMP3]]
-; CHECK-NEXT:    [[TMP8:%.*]] = icmp sle i32 0, [[TMP7]]
-; CHECK-NEXT:    [[TMP9:%.*]] = shl i32 [[TMP1]], 1
-; CHECK-NEXT:    [[TMP10:%.*]] = lshr i32 [[TMP9]], 1
-; CHECK-NEXT:    [[TMP11:%.*]] = xor i32 [[TMP1]], [[TMP10]]
-; CHECK-NEXT:    [[TMP12:%.*]] = xor i32 [[TMP10]], -1
-; CHECK-NEXT:    [[TMP13:%.*]] = and i32 [[X]], [[TMP12]]
-; CHECK-NEXT:    [[TMP14:%.*]] = or i32 [[TMP13]], [[TMP11]]
-; CHECK-NEXT:    [[TMP15:%.*]] = icmp sle i32 0, [[TMP14]]
-; CHECK-NEXT:    [[TMP16:%.*]] = xor i1 [[TMP8]], [[TMP15]]
+; CHECK-NEXT:    [[TMP16:%.*]] = icmp slt i32 [[TMP1]], 0
 ; CHECK-NEXT:    [[TMP17:%.*]] = icmp sle i32 0, [[X]]
 ; CHECK-NEXT:    store i1 [[TMP16]], ptr @__msan_retval_tls, align 8
 ; CHECK-NEXT:    ret i1 [[TMP17]]
@@ -1887,26 +1743,10 @@ define zeroext i1 @ICmpSLEZero(i32 %x) nounwind uwtable readnone sanitize_memory
 ; ORIGIN-NEXT:    [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8
 ; ORIGIN-NEXT:    [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4
 ; ORIGIN-NEXT:    call void @llvm.donothing()
-; ORIGIN-NEXT:    [[TMP3:%.*]] = shl i32 [[TMP1]], 1
-; ORIGIN-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 1
-; ORIGIN-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]]
-; ORIGIN-NEXT:    [[TMP6:%.*]] = xor i32 [[TMP5]], -1
-; ORIGIN-NEXT:    [[TMP7:%.*]] = and i32 [[X]], [[TMP6]]
-; ORIGIN-NEXT:    [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP4]]
-; ORIGIN-NEXT:    [[TMP9:%.*]] = icmp sle i32 0, [[TMP8]]
-; ORIGIN-NEXT:    [[TMP10:%.*]] = shl i32 [[TMP1]], 1
-; ORIGIN-NEXT:    [[TMP11:%.*]] = lshr i32 [[TMP10]], 1
-; ORIGIN-NEXT:    [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]]
-; ORIGIN-NEXT:    [[TMP13:%.*]] = xor i32 [[TMP11]], -1
-; ORIGIN-NEXT:    [[TMP14:%.*]] = and i32 [[X]], [[TMP13]]
-; ORIGIN-NEXT:    [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP12]]
-; ORIGIN-NEXT:    [[TMP16:%.*]] = icmp sle i32 0, [[TMP15]]
-; ORIGIN-NEXT:    [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]]
-; ORIGIN-NEXT:    [[TMP18:%.*]] = icmp ne i32 [[TMP1]], 0
-; ORIGIN-NEXT:    [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP2]], i32 0
+; ORIGIN-NEXT:    [[TMP17:%.*]] = icmp slt i32 [[TMP1]], 0
 ; ORIGIN-NEXT:    [[TMP20:%.*]] = icmp sle i32 0, [[X]]
 ; ORIGIN-NEXT:    store i1 [[TMP17]], ptr @__msan_retval_tls, align 8
-; ORIGIN-NEXT:    store i32 [[TMP19]], ptr @__msan_retval_origin_tls, align 4
+; ORIGIN-NEXT:    store i32 [[TMP2]], ptr @__msan_retval_origin_tls, align 4
 ; ORIGIN-NEXT:    ret i1 [[TMP20]]
 ;
 ; CALLS-LABEL: define zeroext i1 @ICmpSLEZero(
@@ -1914,26 +1754,10 @@ define zeroext i1 @ICmpSLEZero(i32 %x) nounwind uwtable readnone sanitize_memory
 ; CALLS-NEXT:    [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8
 ; CALLS-NEXT:    [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4
 ; CALLS-NEXT:    call void @llvm.donothing()
-; CALLS-NEXT:    [[TMP3:%.*]] = shl i32 [[TMP1]], 1
-; CALLS-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 1
-; CALLS-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]]
-; CALLS-NEXT:    [[TMP6:%.*]] = xor i32 [[TMP5]], -1
-; CALLS-NEXT:    [[TMP7:%.*]] = and i32 [[X]], [[TMP6]]
-; CALLS-NEXT:    [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP4]]
-; CALLS-NEXT:    [[TMP9:%.*]] = icmp sle i32 0, [[TMP8]]
-; CALLS-NEXT:    [[TMP10:%.*]] = shl i32 [[TMP1]], 1
-; CALLS-NEXT:    [[TMP11:%.*]] = lshr i32 [[TMP10]], 1
-; CALLS-NEXT:    [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]]
-; CALLS-NEXT:    [[TMP13:%.*]] = xor i32 [[TMP11]], -1
-; CALLS-NEXT:    [[TMP14:%.*]] = and i32 [[X]], [[TMP13]]
-; CALLS-NEXT:    [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP12]]
-; CALLS-NEXT:    [[TMP16:%.*]] = icmp sle i32 0, [[TMP15]]
-; CALLS-NEXT:    [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]]
-; CALLS-NEXT:    [[TMP18:%.*]] = icmp ne i32 [[TMP1]], 0
-; CALLS-NEXT:    [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP2]], i32 0
+; CALLS-NEXT:    [[TMP17:%.*]] = icmp slt i32 [[TMP1]], 0
 ; CALLS-NEXT:    [[TMP20:%.*]] = icmp sle i32 0, [[X]]
 ; CALLS-NEXT:    store i1 [[TMP17]], ptr @__msan_retval_tls, align 8
-; CALLS-NEXT:    store i32 [[TMP19]], ptr @__msan_retval_origin_tls, align 4
+; CALLS-NEXT:    store i32 [[TMP2]], ptr @__msan_retval_origin_tls, align 4
 ; CALLS-NEXT:    ret i1 [[TMP20]]
 ;
   %1 = icmp sle i32 0, %x
@@ -1949,21 +1773,7 @@ define zeroext i1 @ICmpSLTAllOnes(i32 %x) nounwind uwtable readnone sanitize_mem
 ; CHECK-SAME: i32 [[X:%.*]]) #[[ATTR0]] {
 ; CHECK-NEXT:    [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8
 ; CHECK-NEXT:    call void @llvm.donothing()
-; CHECK-NEXT:    [[TMP2:%.*]] = shl i32 [[TMP1]], 1
-; CHECK-NEXT:    [[TMP3:%.*]] = lshr i32 [[TMP2]], 1
-; CHECK-NEXT:    [[TMP4:%.*]] = xor i32 [[TMP1]], [[TMP3]]
-; CHECK-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP4]], -1
-; CHECK-NEXT:    [[TMP6:%.*]] = and i32 [[X]], [[TMP5]]
-; CHECK-NEXT:    [[TMP7:%.*]] = or i32 [[TMP6]], [[TMP3]]
-; CHECK-NEXT:    [[TMP8:%.*]] = icmp slt i32 -1, [[TMP7]]
-; CHECK-NEXT:    [[TMP9:%.*]] = shl i32 [[TMP1]], 1
-; CHECK-NEXT:    [[TMP10:%.*]] = lshr i32 [[TMP9]], 1
-; CHECK-NEXT:    [[TMP11:%.*]] = xor i32 [[TMP1]], [[TMP10]]
-; CHECK-NEXT:    [[TMP12:%.*]] = xor i32 [[TMP10]], -1
-; CHECK-NEXT:    [[TMP13:%.*]] = and i32 [[X]], [[TMP12]]
-; CHECK-NEXT:    [[TMP14:%.*]] = or i32 [[TMP13]], [[TMP11]]
-; CHECK-NEXT:    [[TMP15:%.*]] = icmp slt i32 -1, [[TMP14]]
-; CHECK-NEXT:    [[TMP16:%.*]] = xor i1 [[TMP8]], [[TMP15]]
+; CHECK-NEXT:    [[TMP16:%.*]] = icmp slt i32 [[TMP1]], 0
 ; CHECK-NEXT:    [[TMP17:%.*]] = icmp slt i32 -1, [[X]]
 ; CHECK-NEXT:    store i1 [[TMP16]], ptr @__msan_retval_tls, align 8
 ; CHECK-NEXT:    ret i1 [[TMP17]]
@@ -1973,26 +1783,10 @@ define zeroext i1 @ICmpSLTAllOnes(i32 %x) nounwind uwtable readnone sanitize_mem
 ; ORIGIN-NEXT:    [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8
 ; ORIGIN-NEXT:    [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4
 ; ORIGIN-NEXT:    call void @llvm.donothing()
-; ORIGIN-NEXT:    [[TMP3:%.*]] = shl i32 [[TMP1]], 1
-; ORIGIN-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 1
-; ORIGIN-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]]
-; ORIGIN-NEXT:    [[TMP6:%.*]] = xor i32 [[TMP5]], -1
-; ORIGIN-NEXT:    [[TMP7:%.*]] = and i32 [[X]], [[TMP6]]
-; ORIGIN-NEXT:    [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP4]]
-; ORIGIN-NEXT:    [[TMP9:%.*]] = icmp slt i32 -1, [[TMP8]]
-; ORIGIN-NEXT:    [[TMP10:%.*]] = shl i32 [[TMP1]], 1
-; ORIGIN-NEXT:    [[TMP11:%.*]] = lshr i32 [[TMP10]], 1
-; ORIGIN-NEXT:    [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]]
-; ORIGIN-NEXT:    [[TMP13:%.*]] = xor i32 [[TMP11]], -1
-; ORIGIN-NEXT:    [[TMP14:%.*]] = and i32 [[X]], [[TMP13]]
-; ORIGIN-NEXT:    [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP12]]
-; ORIGIN-NEXT:    [[TMP16:%.*]] = icmp slt i32 -1, [[TMP15]]
-; ORIGIN-NEXT:    [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]]
-; ORIGIN-NEXT:    [[TMP18:%.*]] = icmp ne i32 [[TMP1]], 0
-; ORIGIN-NEXT:    [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP2]], i32 0
+; ORIGIN-NEXT:    [[TMP17:%.*]] = icmp slt i32 [[TMP1]], 0
 ; ORIGIN-NEXT:    [[TMP20:%.*]] = icmp slt i32 -1, [[X]]
 ; ORIGIN-NEXT:    store i1 [[TMP17]], ptr @__msan_retval_tls, align 8
-; ORIGIN-NEXT:    store i32 [[TMP19]], ptr @__msan_retval_origin_tls, align 4
+; ORIGIN-NEXT:    store i32 [[TMP2]], ptr @__msan_retval_origin_tls, align 4
 ; ORIGIN-NEXT:    ret i1 [[TMP20]]
 ;
 ; CALLS-LABEL: define zeroext i1 @ICmpSLTAllOnes(
@@ -2000,26 +1794,10 @@ define zeroext i1 @ICmpSLTAllOnes(i32 %x) nounwind uwtable readnone sanitize_mem
 ; CALLS-NEXT:    [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8
 ; CALLS-NEXT:    [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4
 ; CALLS-NEXT:    call void @llvm.donothing()
-; CALLS-NEXT:    [[TMP3:%.*]] = shl i32 [[TMP1]], 1
-; CALLS-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 1
-; CALLS-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]]
-; CALLS-NEXT:    [[TMP6:%.*]] = xor i32 [[TMP5]], -1
-; CALLS-NEXT:    [[TMP7:%.*]] = and i32 [[X]], [[TMP6]]
-; CALLS-NEXT:    [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP4]]
-; CALLS-NEXT:    [[TMP9:%.*]] = icmp slt i32 -1, [[TMP8]]
-; CALLS-NEXT:    [[TMP10:%.*]] = shl i32 [[TMP1]], 1
-; CALLS-NEXT:    [[TMP11:%.*]] = lshr i32 [[TMP10]], 1
-; CALLS-NEXT:    [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]]
-; CALLS-NEXT:    [[TMP13:%.*]] = xor i32 [[TMP11]], -1
-; CALLS-NEXT:    [[TMP14:%.*]] = and i32 [[X]], [[TMP13]]
-; CALLS-NEXT:    [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP12]]
-; CALLS-NEXT:    [[TMP16:%.*]] = icmp slt i32 -1, [[TMP15]]
-; CALLS-NEXT:    [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]]
-; CALLS-NEXT:    [[TMP18:%.*]] = icmp ne i32 [[TMP1]], 0
-; CALLS-NEXT:    [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP2]], i32 0
+; CALLS-NEXT:    [[TMP17:%.*]] = icmp slt i32 [[TMP1]], 0
 ; CALLS-NEXT:    [[TMP20:%.*]] = icmp slt i32 -1, [[X]]
 ; CALLS-NEXT:    store i1 [[TMP17]], ptr @__msan_retval_tls, align 8
-; CALLS-NEXT:    store i32 [[TMP19]], ptr @__msan_retval_origin_tls, align 4
+; CALLS-NEXT:    store i32 [[TMP2]], ptr @__msan_retval_origin_tls, align 4
 ; CALLS-NEXT:    ret i1 [[TMP20]]
 ;
   %1 = icmp slt i32 -1, %x
@@ -2032,21 +1810,7 @@ define zeroext i1 @ICmpSGEAllOnes(i32 %x) nounwind uwtable readnone sanitize_mem
 ; CHECK-SAME: i32 [[X:%.*]]) #[[ATTR0]] {
 ; CHECK-NEXT:    [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8
 ; CHECK-NEXT:    call void @llvm.donothing()
-; CHECK-NEXT:    [[TMP2:%.*]] = shl i32 [[TMP1]], 1
-; CHECK-NEXT:    [[TMP3:%.*]] = lshr i32 [[TMP2]], 1
-; CHECK-NEXT:    [[TMP4:%.*]] = xor i32 [[TMP1]], [[TMP3]]
-; CHECK-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP4]], -1
-; CHECK-NEXT:    [[TMP6:%.*]] = and i32 [[X]], [[TMP5]]
-; CHECK-NEXT:    [[TMP7:%.*]] = or i32 [[TMP6]], [[TMP3]]
-; CHECK-NEXT:    [[TMP8:%.*]] = icmp sge i32 -1, [[TMP7]]
-; CHECK-NEXT:    [[TMP9:%.*]] = shl i32 [[TMP1]], 1
-; CHECK-NEXT:    [[TMP10:%.*]] = lshr i32 [[TMP9]], 1
-; CHECK-NEXT:    [[TMP11:%.*]] = xor i32 [[TMP1]], [[TMP10]]
-; CHECK-NEXT:    [[TMP12:%.*]] = xor i32 [[TMP10]], -1
-; CHECK-NEXT:    [[TMP13:%.*]] = and i32 [[X]], [[TMP12]]
-; CHECK-NEXT:    [[TMP14:%.*]] = or i32 [[TMP13]], [[TMP11]]
-; CHECK-NEXT:    [[TMP15:%.*]] = icmp sge i32 -1, [[TMP14]]
-; CHECK-NEXT:    [[TMP16:%.*]] = xor i1 [[TMP8]], [[TMP15]]
+; CHECK-NEXT:    [[TMP16:%.*]] = icmp slt i32 [[TMP1]], 0
 ; CHECK-NEXT:    [[TMP17:%.*]] = icmp sge i32 -1, [[X]]
 ; CHECK-NEXT:    store i1 [[TMP16]], ptr @__msan_retval_tls, align 8
 ; CHECK-NEXT:    ret i1 [[TMP17]]
@@ -2056,26 +1820,10 @@ define zeroext i1 @ICmpSGEAllOnes(i32 %x) nounwind uwtable readnone sanitize_mem
 ; ORIGIN-NEXT:    [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8
 ; ORIGIN-NEXT:    [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4
 ; ORIGIN-NEXT:    call void @llvm.donothing()
-; ORIGIN-NEXT:    [[TMP3:%.*]] = shl i32 [[TMP1]], 1
-; ORIGIN-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 1
-; ORIGIN-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]]
-; ORIGIN-NEXT:    [[TMP6:%.*]] = xor i32 [[TMP5]], -1
-; ORIGIN-NEXT:    [[TMP7:%.*]] = and i32 [[X]], [[TMP6]]
-; ORIGIN-NEXT:    [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP4]]
-; ORIGIN-NEXT:    [[TMP9:%.*]] = icmp sge i32 -1, [[TMP8]]
-; ORIGIN-NEXT:    [[TMP10:%.*]] = shl i32 [[TMP1]], 1
-; ORIGIN-NEXT:    [[TMP11:%.*]] = lshr i32 [[TMP10]], 1
-; ORIGIN-NEXT:    [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]]
-; ORIGIN-NEXT:    [[TMP13:%.*]] = xor i32 [[TMP11]], -1
-; ORIGIN-NEXT:    [[TMP14:%.*]] = and i32 [[X]], [[TMP13]]
-; ORIGIN-NEXT:    [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP12]]
-; ORIGIN-NEXT:    [[TMP16:%.*]] = icmp sge i32 -1, [[TMP15]]
-; ORIGIN-NEXT:    [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]]
-; ORIGIN-NEXT:    [[TMP18:%.*]] = icmp ne i32 [[TMP1]], 0
-; ORIGIN-NEXT:    [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP2]], i32 0
+; ORIGIN-NEXT:    [[TMP17:%.*]] = icmp slt i32 [[TMP1]], 0
 ; ORIGIN-NEXT:    [[TMP20:%.*]] = icmp sge i32 -1, [[X]]
 ; ORIGIN-NEXT:    store i1 [[TMP17]], ptr @__msan_retval_tls, align 8
-; ORIGIN-NEXT:    store i32 [[TMP19]], ptr @__msan_retval_origin_tls, align 4
+; ORIGIN-NEXT:    store i32 [[TMP2]], ptr @__msan_retval_origin_tls, align 4
 ; ORIGIN-NEXT:    ret i1 [[TMP20]]
 ;
 ; CALLS-LABEL: define zeroext i1 @ICmpSGEAllOnes(
@@ -2083,26 +1831,10 @@ define zeroext i1 @ICmpSGEAllOnes(i32 %x) nounwind uwtable readnone sanitize_mem
 ; CALLS-NEXT:    [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8
 ; CALLS-NEXT:    [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4
 ; CALLS-NEXT:    call void @llvm.donothing()
-; CALLS-NEXT:    [[TMP3:%.*]] = shl i32 [[TMP1]], 1
-; CALLS-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 1
-; CALLS-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]]
-; CALLS-NEXT:    [[TMP6:%.*]] = xor i32 [[TMP5]], -1
-; CALLS-NEXT:    [[TMP7:%.*]] = and i32 [[X]], [[TMP6]]
-; CALLS-NEXT:    [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP4]]
-; CALLS-NEXT:    [[TMP9:%.*]] = icmp sge i32 -1, [[TMP8]]
-; CALLS-NEXT:    [[TMP10:%.*]] = shl i32 [[TMP1]], 1
-; CALLS-NEXT:    [[TMP11:%.*]] = lshr i32 [[TMP10]], 1
-; CALLS-NEXT:    [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]]
-; CALLS-NEXT:    [[TMP13:%.*]] = xor i32 [[TMP11]], -1
-; CALLS-NEXT:    [[TMP14:%.*]] = and i32 [[X]], [[TMP13]]
-; CALLS-NEXT:    [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP12]]
-; CALLS-NEXT:    [[TMP16:%.*]] = icmp sge i32 -1, [[TMP15]]
-; CALLS-NEXT:    [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]]
-; CALLS-NEXT:    [[TMP18:%.*]] = icmp ne i32 [[TMP1]], 0
-; CALLS-NEXT:    [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP2]], i32 0
+; CALLS-NEXT:    [[TMP17:%.*]] = icmp slt i32 [[TMP1]], 0
 ; CALLS-NEXT:    [[TMP20:%.*]] = icmp sge i32 -1, [[X]]
 ; CALLS-NEXT:    store i1 [[TMP17]], ptr @__msan_retval_tls, align 8
-; CALLS-NEXT:    store i32 [[TMP19]], ptr @__msan_retval_origin_tls, align 4
+; CALLS-NEXT:    store i32 [[TMP2]], ptr @__msan_retval_origin_tls, align 4
 ; CALLS-NEXT:    ret i1 [[TMP20]]
 ;
   %1 = icmp sge i32 -1, %x
@@ -2115,21 +1847,7 @@ define zeroext i1 @ICmpSGTAllOnes(i32 %x) nounwind uwtable readnone sanitize_mem
 ; CHECK-SAME: i32 [[X:%.*]]) #[[ATTR0]] {
 ; CHECK-NEXT:    [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8
 ; CHECK-NEXT:    call void @llvm.donothing()
-; CHECK-NEXT:    [[TMP2:%.*]] = shl i32 [[TMP1]], 1
-; CHECK-NEXT:    [[TMP3:%.*]] = lshr i32 [[TMP2]], 1
-; CHECK-NEXT:    [[TMP4:%.*]] = xor i32 [[TMP1]], [[TMP3]]
-; CHECK-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP3]], -1
-; CHECK-NEXT:    [[TMP6:%.*]] = and i32 [[X]], [[TMP5]]
-; CHECK-NEXT:    [[TMP7:%.*]] = or i32 [[TMP6]], [[TMP4]]
-; CHECK-NEXT:    [[TMP8:%.*]] = icmp sgt i32 [[TMP7]], -1
-; CHECK-NEXT:    [[TMP9:%.*]] = shl i32 [[TMP1]], 1
-; CHECK-NEXT:    [[TMP10:%.*]] = lshr i32 [[TMP9]], 1
-; CHECK-NEXT:    [[TMP11:%.*]] = xor i32 [[TMP1]], [[TMP10]]
-; CHECK-NEXT:    [[TMP12:%.*]] = xor i32 [[TMP11]], -1
-; CHECK-NEXT:    [[TMP13:%.*]] = and i32 [[X]], [[TMP12]]
-; CHECK-NEXT:    [[TMP14:%.*]] = or i32 [[TMP13]], [[TMP10]]
-; CHECK-NEXT:    [[TMP15:%.*]] = icmp sgt i32 [[TMP14]], -1
-; CHECK-NEXT:    [[TMP16:%.*]] = xor i1 [[TMP8]], [[TMP15]]
+; CHECK-NEXT:    [[TMP16:%.*]] = icmp slt i32 [[TMP1]], 0
 ; CHECK-NEXT:    [[TMP17:%.*]] = icmp sgt i32 [[X]], -1
 ; CHECK-NEXT:    store i1 [[TMP16]], ptr @__msan_retval_tls, align 8
 ; CHECK-NEXT:    ret i1 [[TMP17]]
@@ -2139,21 +1857,7 @@ define zeroext i1 @ICmpSGTAllOnes(i32 %x) nounwind uwtable readnone sanitize_mem
 ; ORIGIN-NEXT:    [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8
 ; ORIGIN-NEXT:    [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4
 ; ORIGIN-NEXT:    call void @llvm.donothing()
-; ORIGIN-NEXT:    [[TMP3:%.*]] = shl i32 [[TMP1]], 1
-; ORIGIN-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 1
-; ORIGIN-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]]
-; ORIGIN-NEXT:    [[TMP6:%.*]] = xor i32 [[TMP4]], -1
-; ORIGIN-NEXT:    [[TMP7:%.*]] = and i32 [[X]], [[TMP6]]
-; ORIGIN-NEXT:    [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP5]]
-; ORIGIN-NEXT:    [[TMP9:%.*]] = icmp sgt i32 [[TMP8]], -1
-; ORIGIN-NEXT:    [[TMP10:%.*]] = shl i32 [[TMP1]], 1
-; ORIGIN-NEXT:    [[TMP11:%.*]] = lshr i32 [[TMP10]], 1
-; ORIGIN-NEXT:    [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]]
-; ORIGIN-NEXT:    [[TMP13:%.*]] = xor i32 [[TMP12]], -1
-; ORIGIN-NEXT:    [[TMP14:%.*]] = and i32 [[X]], [[TMP13]]
-; ORIGIN-NEXT:    [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP11]]
-; ORIGIN-NEXT:    [[TMP16:%.*]] = icmp sgt i32 [[TMP15]], -1
-; ORIGIN-NEXT:    [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]]
+; ORIGIN-NEXT:    [[TMP17:%.*]] = icmp slt i32 [[TMP1]], 0
 ; ORIGIN-NEXT:    [[TMP18:%.*]] = icmp sgt i32 [[X]], -1
 ; ORIGIN-NEXT:    store i1 [[TMP17]], ptr @__msan_retval_tls, align 8
 ; ORIGIN-NEXT:    store i32 [[TMP2]], ptr @__msan_retval_origin_tls, align 4
@@ -2164,21 +1868,7 @@ define zeroext i1 @ICmpSGTAllOnes(i32 %x) nounwind uwtable readnone sanitize_mem
 ; CALLS-NEXT:    [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8
 ; CALLS-NEXT:    [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4
 ; CALLS-NEXT:    call void @llvm.donothing()
-; CALLS-NEXT:    [[TMP3:%.*]] = shl i32 [[TMP1]], 1
-; CALLS-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 1
-; CALLS-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]]
-; CALLS-NEXT:    [[TMP6:%.*]] = xor i32 [[TMP4]], -1
-; CALLS-NEXT:    [[TMP7:%.*]] = and i32 [[X]], [[TMP6]]
-; CALLS-NEXT:    [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP5]]
-; CALLS-NEXT:    [[TMP9:%.*]] = icmp sgt i32 [[TMP8]], -1
-; CALLS-NEXT:    [[TMP10:%.*]] = shl i32 [[TMP1]], 1
-; CALLS-NEXT:    [[TMP11:%.*]] = lshr i32 [[TMP10]], 1
-; CALLS-NEXT:    [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]]
-; CALLS-NEXT:    [[TMP13:%.*]] = xor i32 [[TMP12]], -1
-; CALLS-NEXT:    [[TMP14:%.*]] = and i32 [[X]], [[TMP13]]
-; CALLS-NEXT:    [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP11]]
-; CALLS-NEXT:    [[TMP16:%.*]] = icmp sgt i32 [[TMP15]], -1
-; CALLS-NEXT:    [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]]
+; CALLS-NEXT:    [[TMP17:%.*]] = icmp slt i32 [[TMP1]], 0
 ; CALLS-NEXT:    [[TMP18:%.*]] = icmp sgt i32 [[X]], -1
 ; CALLS-NEXT:    store i1 [[TMP17]], ptr @__msan_retval_tls, align 8
 ; CALLS-NEXT:    store i32 [[TMP2]], ptr @__msan_retval_origin_tls, align 4
@@ -2194,21 +1884,7 @@ define zeroext i1 @ICmpSLEAllOnes(i32 %x) nounwind uwtable readnone sanitize_mem
 ; CHECK-SAME: i32 [[X:%.*]]) #[[ATTR0]] {
 ; CHECK-NEXT:    [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8
 ; CHECK-NEXT:    call void @llvm.donothing()
-; CHECK-NEXT:    [[TMP2:%.*]] = shl i32 [[TMP1]], 1
-; CHECK-NEXT:    [[TMP3:%.*]] = lshr i32 [[TMP2]], 1
-; CHECK-NEXT:    [[TMP4:%.*]] = xor i32 [[TMP1]], [[TMP3]]
-; CHECK-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP3]], -1
-; CHECK-NEXT:    [[TMP6:%.*]] = and i32 [[X]], [[TMP5]]
-; CHECK-NEXT:    [[TMP7:%.*]] = or i32 [[TMP6]], [[TMP4]]
-; CHECK-NEXT:    [[TMP8:%.*]] = icmp sle i32 [[TMP7]], -1
-; CHECK-NEXT:    [[TMP9:%.*]] = shl i32 [[TMP1]], 1
-; CHECK-NEXT:    [[TMP10:%.*]] = lshr i32 [[TMP9]], 1
-; CHECK-NEXT:    [[TMP11:%.*]] = xor i32 [[TMP1]], [[TMP10]]
-; CHECK-NEXT:    [[TMP12:%.*]] = xor i32 [[TMP11]], -1
-; CHECK-NEXT:    [[TMP13:%.*]] = and i32 [[X]], [[TMP12]]
-; CHECK-NEXT:    [[TMP14:%.*]] = or i32 [[TMP13]], [[TMP10]]
-; CHECK-NEXT:    [[TMP15:%.*]] = icmp sle i32 [[TMP14]], -1
-; CHECK-NEXT:    [[TMP16:%.*]] = xor i1 [[TMP8]], [[TMP15]]
+; CHECK-NEXT:    [[TMP16:%.*]] = icmp slt i32 [[TMP1]], 0
 ; CHECK-NEXT:    [[TMP17:%.*]] = icmp sle i32 [[X]], -1
 ; CHECK-NEXT:    store i1 [[TMP16]], ptr @__msan_retval_tls, align 8
 ; CHECK-NEXT:    ret i1 [[TMP17]]
@@ -2218,21 +1894,7 @@ define zeroext i1 @ICmpSLEAllOnes(i32 %x) nounwind uwtable readnone sanitize_mem
 ; ORIGIN-NEXT:    [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8
 ; ORIGIN-NEXT:    [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4
 ; ORIGIN-NEXT:    call void @llvm.donothing()
-; ORIGIN-NEXT:    [[TMP3:%.*]] = shl i32 [[TMP1]], 1
-; ORIGIN-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 1
-; ORIGIN-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]]
-; ORIGIN-NEXT:    [[TMP6:%.*]] = xor i32 [[TMP4]], -1
-; ORIGIN-NEXT:    [[TMP7:%.*]] = and i32 [[X]], [[TMP6]]
-; ORIGIN-NEXT:    [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP5]]
-; ORIGIN-NEXT:    [[TMP9:%.*]] = icmp sle i32 [[TMP8]], -1
-; ORIGIN-NEXT:    [[TMP10:%.*]] = shl i32 [[TMP1]], 1
-; ORIGIN-NEXT:    [[TMP11:%.*]] = lshr i32 [[TMP10]], 1
-; ORIGIN-NEXT:    [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]]
-; ORIGIN-NEXT:    [[TMP13:%.*]] = xor i32 [[TMP12]], -1
-; ORIGIN-NEXT:    [[TMP14:%.*]] = and i32 [[X]], [[TMP13]]
-; ORIGIN-NEXT:    [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP11]]
-; ORIGIN-NEXT:    [[TMP16:%.*]] = icmp sle i32 [[TMP15]], -1
-; ORIGIN-NEXT:    [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]]
+; ORIGIN-NEXT:    [[TMP17:%.*]] = icmp slt i32 [[TMP1]], 0
 ; ORIGIN-NEXT:    [[TMP18:%.*]] = icmp sle i32 [[X]], -1
 ; ORIGIN-NEXT:    store i1 [[TMP17]], ptr @__msan_retval_tls, align 8
 ; ORIGIN-NEXT:    store i32 [[TMP2]], ptr @__msan_retval_origin_tls, align 4
@@ -2243,21 +1905,7 @@ define zeroext i1 @ICmpSLEAllOnes(i32 %x) nounwind uwtable readnone sanitize_mem
 ; CALLS-NEXT:    [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8
 ; CALLS-NEXT:    [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4
 ; CALLS-NEXT:    call void @llvm.donothing()
-; CALLS-NEXT:    [[TMP3:%.*]] = shl i32 [[TMP1]], 1
-; CALLS-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 1
-; CALLS-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]]
-; CALLS-NEXT:    [[TMP6:%.*]] = xor i32 [[TMP4]], -1
-; CALLS-NEXT:    [[TMP7:%.*]] = and i32 [[X]], [[TMP6]]
-; CALLS-NEXT:    [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP5]]
-; CALLS-NEXT:    [[TMP9:%.*]] = icmp sle i32 [[TMP8]], -1
-; CALLS-NEXT:    [[TMP10:%.*]] = shl i32 [[TMP1]], 1
-; CALLS-NEXT:    [[TMP11:%.*]] = lshr i32 [[TMP10]], 1
-; CALLS-NEXT:    [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]]
-; CALLS-NEXT:    [[TMP13:%.*]] = xor i32 [[TMP12]], -1
-; CALLS-NEXT:    [[TMP14:%.*]] = and i32 [[X]], [[TMP13]]
-; CALLS-NEXT:    [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP11]]
-; CALLS-NEXT:    [[TMP16:%.*]] = icmp sle i32 [[TMP15]], -1
-; CALLS-NEXT:    [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]]
+; CALLS-NEXT:    [[TMP17:%.*]] = icmp slt i32 [[TMP1]], 0
 ; CALLS-NEXT:    [[TMP18:%.*]] = icmp sle i32 [[X]], -1
 ; CALLS-NEXT:    store i1 [[TMP17]], ptr @__msan_retval_tls, align 8
 ; CALLS-NEXT:    store i32 [[TMP2]], ptr @__msan_retval_origin_tls, align 4
@@ -2277,22 +1925,7 @@ define <2 x i1> @ICmpSLT_vector_Zero(<2 x ptr> %x) nounwind uwtable readnone san
 ; CHECK-SAME: <2 x ptr> [[X:%.*]]) #[[ATTR0]] {
 ; CHECK-NEXT:    [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8
 ; CHECK-NEXT:    call void @llvm.donothing()
-; CHECK-NEXT:    [[TMP2:%.*]] = ptrtoint <2 x ptr> [[X]] to <2 x i64>
-; CHECK-NEXT:    [[TMP3:%.*]] = shl <2 x i64> [[TMP1]], <i64 1, i64 1>
-; CHECK-NEXT:    [[TMP4:%.*]] = lshr <2 x i64> [[TMP3]], <i64 1, i64 1>
-; CHECK-NEXT:    [[TMP5:%.*]] = xor <2 x i64> [[TMP1]], [[TMP4]]
-; CHECK-NEXT:    [[TMP6:%.*]] = xor <2 x i64> [[TMP4]], <i64 -1, i64 -1>
-; CHECK-NEXT:    [[TMP7:%.*]] = and <2 x i64> [[TMP2]], [[TMP6]]
-; CHECK-NEXT:    [[TMP8:%.*]] = or <2 x i64> [[TMP7]], [[TMP5]]
-; CHECK-NEXT:    [[TMP9:%.*]] = icmp slt <2 x i64> [[TMP8]], zeroinitializer
-; CHECK-NEXT:    [[TMP10:%.*]] = shl <2 x i64> [[TMP1]], <i64 1, i64 1>
-; CHECK-NEXT:    [[TMP11:%.*]] = lshr <2 x i64> [[TMP10]], <i64 1, i64 1>
-; CHECK-NEXT:    [[TMP12:%.*]] = xor <2 x i64> [[TMP1]], [[TMP11]]
-; CHECK-NEXT:    [[TMP13:%.*]] = xor <2 x i64> [[TMP12]], <i64 -1, i64 -1>
-; CHECK-NEXT:    [[TMP14:%.*]] = and <2 x i64> [[TMP2]], [[TMP13]]
-; CHECK-NEXT:    [[TMP15:%.*]] = or <2 x i64> [[TMP14]], [[TMP11]]
-; CHECK-NEXT:    [[TMP16:%.*]] = icmp slt <2 x i64> [[TMP15]], zeroinitializer
-; CHECK-NEXT:    [[TMP17:%.*]] = xor <2 x i1> [[TMP9]], [[TMP16]]
+; CHECK-NEXT:    [[TMP17:%.*]] = icmp slt <2 x i64> [[TMP1]], zeroinitializer
 ; CHECK-NEXT:    [[TMP18:%.*]] = icmp slt <2 x ptr> [[X]], zeroinitializer
 ; CHECK-NEXT:    store <2 x i1> [[TMP17]], ptr @__msan_retval_tls, align 8
 ; CHECK-NEXT:    ret <2 x i1> [[TMP18]]
@@ -2302,22 +1935,7 @@ define <2 x i1> @ICmpSLT_vector_Zero(<2 x ptr> %x) nounwind uwtable readnone san
 ; ORIGIN-NEXT:    [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8
 ; ORIGIN-NEXT:    [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4
 ; ORIGIN-NEXT:    call void @llvm.donothing()
-; ORIGIN-NEXT:    [[TMP3:%.*]] = ptrtoint <2 x ptr> [[X]] to <2 x i64>
-; ORIGIN-NEXT:    [[TMP4:%.*]] = shl <2 x i64> [[TMP1]], <i64 1, i64 1>
-; ORIGIN-NEXT:    [[TMP5:%.*]] = lshr <2 x i64> [[TMP4]], <i64 1, i64 1>
-; ORIGIN-NEXT:    [[TMP6:%.*]] = xor <2 x i64> [[TMP1]], [[TMP5]]
-; ORIGIN-NEXT:    [[TMP7:%.*]] = xor <2 x i64> [[TMP5]], <i64 -1, i64 -1>
-; ORIGIN-NEXT:    [[TMP8:%.*]] = and <2 x i64> [[TMP3]], [[TMP7]]
-; ORIGIN-NEXT:    [[TMP9:%.*]] = or <2 x i64> [[TMP8]], [[TMP6]]
-; ORIGIN-NEXT:    [[TMP10:%.*]] = icmp slt <2 x i64> [[TMP9]], zeroinitializer
-; ORIGIN-NEXT:    [[TMP11:%.*]] = shl <2 x i64> [[TMP1]], <i64 1, i64 1>
-; ORIGIN-NEXT:    [[TMP12:%.*]] = lshr <2 x i64> [[TMP11]], <i64 1, i64 1>
-; ORIGIN-NEXT:    [[TMP13:%.*]] = xor <2 x i64> [[TMP1]], [[TMP12]]
-; ORIGIN-NEXT:    [[TMP14:%.*]] = xor <2 x i64> [[TMP13]], <i64 -1, i64 -1>
-; ORIGIN-NEXT:    [[TMP15:%.*]] = and <2 x i64> [[TMP3]], [[TMP14]]
-; ORIGIN-NEXT:    [[TMP16:%.*]] = or <2 x i64> [[TMP15]], [[TMP12]]
-; ORIGIN-NEXT:    [[TMP17:%.*]] = icmp slt <2 x i64> [[TMP16]], zeroinitializer
-; ORIGIN-NEXT:    [[TMP18:%.*]] = xor <2 x i1> [[TMP10]], [[TMP17]]
+; ORIGIN-NEXT:    [[TMP18:%.*]] = icmp slt <2 x i64> [[TMP1]], zeroinitializer
 ; ORIGIN-NEXT:    [[TMP19:%.*]] = icmp slt <2 x ptr> [[X]], zeroinitializer
 ; ORIGIN-NEXT:    store <2 x i1> [[TMP18]], ptr @__msan_retval_tls, align 8
 ; ORIGIN-NEXT:    store i32 [[TMP2]], ptr @__msan_retval_origin_tls, align 4
@@ -2328,22 +1946,7 @@ define <2 x i1> @ICmpSLT_vector_Zero(<2 x ptr> %x) nounwind uwtable readnone san
 ; CALLS-NEXT:    [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8
 ; CALLS-NEXT:    [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4
 ; CALLS-NEXT:    call void @llvm.donothing()
-; CALLS-NEXT:    [[TMP3:%.*]] = ptrtoint <2 x ptr> [[X]] to <2 x i64>
-; CALLS-NEXT:    [[TMP4:%.*]] = shl <2 x i64> [[TMP1]], <i64 1, i64 1>
-; CALLS-NEXT:    [[TMP5:%.*]] = lshr <2 x i64> [[TMP4]], <i64 1, i64 1>
-; CALLS-NEXT:    [[TMP6:%.*]] = xor <2 x i64> [[TMP1]], [[TMP5]]
-; CALLS-NEXT:    [[TMP7:%.*]] = xor <2 x i64> [[TMP5]], <i64 -1, i64 -1>
-; CALLS-NEXT:    [[TMP8:%.*]] = and <2 x i64> [[TMP3]], [[TMP7]]
-; CALLS-NEXT:    [[TMP9:%.*]] = or <2 x i64> [[TMP8]], [[TMP6]]
-; CALLS-NEXT:    [[TMP10:%.*]] = icmp slt <2 x i64> [[TMP9]], zeroinitializer
-; CALLS-NEXT:    [[TMP11:%.*]] = shl <2 x i64> [[TMP1]], <i64 1, i64 1>
-; CALLS-NEXT:    [[TMP12:%.*]] = lshr <2 x i64> [[TMP11]], <i64 1, i64 1>
-; CALLS-NEXT:    [[TMP13:%.*]] = xor <2 x i64> [[TMP1]], [[TMP12]]
-; CALLS-NEXT:    [[TMP14:%.*]] = xor <2 x i64> [[TMP13]], <i64 -1, i64 -1>
-; CALLS-NEXT:    [[TMP15:%.*]] = and <2 x i64> [[TMP3]], [[TMP14]]
-; CALLS-NEXT:    [[TMP16:%.*]] = or <2 x i64> [[TMP15]], [[TMP12]]
-; CALLS-NEXT:    [[TMP17:%.*]] = icmp slt <2 x i64> [[TMP16]], zeroinitializer
-; CALLS-NEXT:    [[TMP18:%.*]] = xor <2 x i1> [[TMP10]], [[TMP17]]
+; CALLS-NEXT:    [[TMP18:%.*]] = icmp slt <2 x i64> [[TMP1]], zeroinitializer
 ; CALLS-NEXT:    [[TMP19:%.*]] = icmp slt <2 x ptr> [[X]], zeroinitializer
 ; CALLS-NEXT:    store <2 x i1> [[TMP18]], ptr @__msan_retval_tls, align 8
 ; CALLS-NEXT:    store i32 [[TMP2]], ptr @__msan_retval_origin_tls, align 4
@@ -2362,21 +1965,7 @@ define <2 x i1> @ICmpSLT_vector_AllOnes(<2 x i32> %x) nounwind uwtable readnone
 ; CHECK-SAME: <2 x i32> [[X:%.*]]) #[[ATTR0]] {
 ; CHECK-NEXT:    [[TMP1:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 8
 ; CHECK-NEXT:    call void @llvm.donothing()
-; CHECK-NEXT:    [[TMP2:%.*]] = shl <2 x i32> [[TMP1]], <i32 1, i32 1>
-; CHECK-NEXT:    [[TMP3:%.*]] = lshr <2 x i32> [[TMP2]], <i32 1, i32 1>
-; CHECK-NEXT:    [[TMP4:%.*]] = xor <2 x i32> [[TMP1]], [[TMP3]]
-; CHECK-NEXT:    [[TMP5:%.*]] = xor <2 x i32> [[TMP4]], <i32 -1, i32 -1>
-; CHECK-NEXT:    [[TMP6:%.*]] = and <2 x i32> [[X]], [[TMP5]]
-; CHECK-NEXT:    [[TMP7:%.*]] = or <2 x i32> [[TMP6]], [[TMP3]]
-; CHECK-NEXT:    [[TMP8:%.*]] = icmp slt <2 x i32> <i32 -1, i32 -1>, [[TMP7]]
-; CHECK-NEXT:    [[TMP9:%.*]] = shl <2 x i32> [[TMP1]], <i32 1, i32 1>
-; CHECK-NEXT:    [[TMP10:%.*]] = lshr <2 x i32> [[TMP9]], <i32 1, i32 1>
-; CHECK-NEXT:    [[TMP11:%.*]] = xor <2 x i32> [[TMP1]], [[TMP10]]
-; CHECK-NEXT:    [[TMP12:%.*]] = xor <2 x i32> [[TMP10]], <i32 -1, i32 -1>
-; CHECK-NEXT:    [[TMP13:%.*]] = and <2 x i32> [[X]], [[TMP12]]
-; CHECK-NEXT:    [[TMP14:%.*]] = or <2 x i32> [[TMP13]], [[TMP11]]
-; CHECK-NEXT:    [[TMP15:%.*]] = icmp slt <2 x i32> <i32 -1, i32 -1>, [[TMP14]]
-; CHECK-NEXT:    [[TMP16:%.*]] = xor <2 x i1> [[TMP8]], [[TMP15]]
+; CHECK-NEXT:    [[TMP16:%.*]] = icmp slt <2 x i32> [[TMP1]], zeroinitializer
 ; CHECK-NEXT:    [[TMP17:%.*]] = icmp slt <2 x i32> <i32 -1, i32 -1>, [[X]]
 ; CHECK-NEXT:    store <2 x i1> [[TMP16]], ptr @__msan_retval_tls, align 8
 ; CHECK-NEXT:    ret <2 x i1> [[TMP17]]
@@ -2386,27 +1975,10 @@ define <2 x i1> @ICmpSLT_vector_AllOnes(<2 x i32> %x) nounwind uwtable readnone
 ; ORIGIN-NEXT:    [[TMP1:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 8
 ; ORIGIN-NEXT:    [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4
 ; ORIGIN-NEXT:    call void @llvm.donothing()
-; ORIGIN-NEXT:    [[TMP3:%.*]] = shl <2 x i32> [[TMP1]], <i32 1, i32 1>
-; ORIGIN-NEXT:    [[TMP4:%.*]] = lshr <2 x i32> [[TMP3]], <i32 1, i32 1>
-; ORIGIN-NEXT:    [[TMP5:%.*]] = xor <2 x i32> [[TMP1]], [[TMP4]]
-; ORIGIN-NEXT:    [[TMP6:%.*]] = xor <2 x i32> [[TMP5]], <i32 -1, i32 -1>
-; ORIGIN-NEXT:    [[TMP7:%.*]] = and <2 x i32> [[X]], [[TMP6]]
-; ORIGIN-NEXT:    [[TMP8:%.*]] = or <2 x i32> [[TMP7]], [[TMP4]]
-; ORIGIN-NEXT:    [[TMP9:%.*]] = icmp slt <2 x i32> <i32 -1, i32 -1>, [[TMP8]]
-; ORIGIN-NEXT:    [[TMP10:%.*]] = shl <2 x i32> [[TMP1]], <i32 1, i32 1>
-; ORIGIN-NEXT:    [[TMP11:%.*]] = lshr <2 x i32> [[TMP10]], <i32 1, i32 1>
-; ORIGIN-NEXT:    [[TMP12:%.*]] = xor <2 x i32> [[TMP1]], [[TMP11]]
-; ORIGIN-NEXT:    [[TMP13:%.*]] = xor <2 x i32> [[TMP11]], <i32 -1, i32 -1>
-; ORIGIN-NEXT:    [[TMP14:%.*]] = and <2 x i32> [[X]], [[TMP13]]
-; ORIGIN-NEXT:    [[TMP15:%.*]] = or <2 x i32> [[TMP14]], [[TMP12]]
-; ORIGIN-NEXT:    [[TMP16:%.*]] = icmp slt <2 x i32> <i32 -1, i32 -1>, [[TMP15]]
-; ORIGIN-NEXT:    [[TMP17:%.*]] = xor <2 x i1> [[TMP9]], [[TMP16]]
-; ORIGIN-NEXT:    [[TMP18:%.*]] = bitcast <2 x i32> [[TMP1]] to i64
-; ORIGIN-NEXT:    [[TMP19:%.*]] = icmp ne i64 [[TMP18]], 0
-; ORIGIN-NEXT:    [[TMP20:%.*]] = select i1 [[TMP19]], i32 [[TMP2]], i32 0
+; ORIGIN-NEXT:    [[TMP17:%.*]] = icmp slt <2 x i32> [[TMP1]], zeroinitializer
 ; ORIGIN-NEXT:    [[TMP21:%.*]] = icmp slt <2 x i32> <i32 -1, i32 -1>, [[X]]
 ; ORIGIN-NEXT:    store <2 x i1> [[TMP17]], ptr @__msan_retval_tls, align 8
-; ORIGIN-NEXT:    store i32 [[TMP20]], ptr @__msan_retval_origin_tls, align 4
+; ORIGIN-NEXT:    store i32 [[TMP2]], ptr @__msan_retval_origin_tls, align 4
 ; ORIGIN-NEXT:    ret <2 x i1> [[TMP21]]
 ;
 ; CALLS-LABEL: define <2 x i1> @ICmpSLT_vector_AllOnes(
@@ -2414,27 +1986,10 @@ define <2 x i1> @ICmpSLT_vector_AllOnes(<2 x i32> %x) nounwind uwtable readnone
 ; CALLS-NEXT:    [[TMP1:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 8
 ; CALLS-NEXT:    [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4
 ; CALLS-NEXT:    call void @llvm.donothing()
-; CALLS-NEXT:    [[TMP3:%.*]] = shl <2 x i32> [[TMP1]], <i32 1, i32 1>
-; CALLS-NEXT:    [[TMP4:%.*]] = lshr <2 x i32> [[TMP3]], <i32 1, i32 1>
-; CALLS-NEXT:    [[TMP5:%.*]] = xor <2 x i32> [[TMP1]], [[TMP4]]
-; CALLS-NEXT:    [[TMP6:%.*]] = xor <2 x i32> [[TMP5]], <i32 -1, i32 -1>
-; CALLS-NEXT:    [[TMP7:%.*]] = and <2 x i32> [[X]], [[TMP6]]
-; CALLS-NEXT:    [[TMP8:%.*]] = or <2 x i32> [[TMP7]], [[TMP4]]
-; CALLS-NEXT:    [[TMP9:%.*]] = icmp slt <2 x i32> <i32 -1, i32 -1>, [[TMP8]]
-; CALLS-NEXT:    [[TMP10:%.*]] = shl <2 x i32> [[TMP1]], <i32 1, i32 1>
-; CALLS-NEXT:    [[TMP11:%.*]] = lshr <2 x i32> [[TMP10]], <i32 1, i32 1>
-; CALLS-NEXT:    [[TMP12:%.*]] = xor <2 x i32> [[TMP1]], [[TMP11]]
-; CALLS-NEXT:    [[TMP13:%.*]] = xor <2 x i32> [[TMP11]], <i32 -1, i32 -1>
-; CALLS-NEXT:    [[TMP14:%.*]] = and <2 x i32> [[X]], [[TMP13]]
-; CALLS-NEXT:    [[TMP15:%.*]] = or <2 x i32> [[TMP14]], [[TMP12]]
-; CALLS-NEXT:    [[TMP16:%.*]] = icmp slt <2 x i32> <i32 -1, i32 -1>, [[TMP15]]
-; CALLS-NEXT:    [[TMP17:%.*]] = xor <2 x i1> [[TMP9]], [[TMP16]]
-; CALLS-NEXT:    [[TMP18:%.*]] = bitcast <2 x i32> [[TMP1]] to i64
-; CALLS-NEXT:    [[TMP19:%.*]] = icmp ne i64 [[TMP18]], 0
-; CALLS-NEXT:    [[TMP20:%.*]] = select i1 [[TMP19]], i32 [[TMP2]], i32 0
+; CALLS-NEXT:    [[TMP17:%.*]] = icmp slt <2 x i32> [[TMP1]], zeroinitializer
 ; CALLS-NEXT:    [[TMP21:%.*]] = icmp slt <2 x i32> <i32 -1, i32 -1>, [[X]]
 ; CALLS-NEXT:    store <2 x i1> [[TMP17]], ptr @__msan_retval_tls, align 8
-; CALLS-NEXT:    store i32 [[TMP20]], ptr @__msan_retval_origin_tls, align 4
+; CALLS-NEXT:    store i32 [[TMP2]], ptr @__msan_retval_origin_tls, align 4
 ; CALLS-NEXT:    ret <2 x i1> [[TMP21]]
 ;
   %1 = icmp slt <2 x i32> <i32 -1, i32 -1>, %x
diff --git a/llvm/test/Instrumentation/MemorySanitizer/pr32842.ll b/llvm/test/Instrumentation/MemorySanitizer/pr32842.ll
index 17fe78d292bd0..a0ff11d93631c 100644
--- a/llvm/test/Instrumentation/MemorySanitizer/pr32842.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/pr32842.ll
@@ -15,33 +15,8 @@ define zeroext i1 @_Z1fii(i32 %x, i32 %y) sanitize_memory {
 ; CHECK-NEXT:    [[TMP0:%.*]] = load i32, ptr @__msan_param_tls, align 8
 ; CHECK-NEXT:    [[TMP1:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
 ; CHECK-NEXT:    call void @llvm.donothing()
-; CHECK-NEXT:    [[TMP28:%.*]] = shl i32 [[TMP0]], 1
-; CHECK-NEXT:    [[TMP3:%.*]] = lshr i32 [[TMP28]], 1
-; CHECK-NEXT:    [[TMP4:%.*]] = xor i32 [[TMP0]], [[TMP3]]
-; CHECK-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP3]], -1
-; CHECK-NEXT:    [[TMP6:%.*]] = and i32 [[X]], [[TMP5]]
-; CHECK-NEXT:    [[TMP7:%.*]] = or i32 [[TMP6]], [[TMP4]]
-; CHECK-NEXT:    [[TMP8:%.*]] = shl i32 [[TMP1]], 1
-; CHECK-NEXT:    [[TMP9:%.*]] = lshr i32 [[TMP8]], 1
-; CHECK-NEXT:    [[TMP10:%.*]] = xor i32 [[TMP1]], [[TMP9]]
-; CHECK-NEXT:    [[TMP11:%.*]] = xor i32 [[TMP10]], -1
-; CHECK-NEXT:    [[TMP12:%.*]] = and i32 [[Y]], [[TMP11]]
-; CHECK-NEXT:    [[TMP13:%.*]] = or i32 [[TMP12]], [[TMP9]]
-; CHECK-NEXT:    [[TMP14:%.*]] = icmp slt i32 [[TMP7]], [[TMP13]]
-; CHECK-NEXT:    [[TMP15:%.*]] = shl i32 [[TMP0]], 1
-; CHECK-NEXT:    [[TMP16:%.*]] = lshr i32 [[TMP15]], 1
-; CHECK-NEXT:    [[TMP17:%.*]] = xor i32 [[TMP0]], [[TMP16]]
-; CHECK-NEXT:    [[TMP18:%.*]] = xor i32 [[TMP17]], -1
-; CHECK-NEXT:    [[TMP19:%.*]] = and i32 [[X]], [[TMP18]]
-; CHECK-NEXT:    [[TMP20:%.*]] = or i32 [[TMP19]], [[TMP16]]
-; CHECK-NEXT:    [[TMP21:%.*]] = shl i32 [[TMP1]], 1
-; CHECK-NEXT:    [[TMP22:%.*]] = lshr i32 [[TMP21]], 1
-; CHECK-NEXT:    [[TMP23:%.*]] = xor i32 [[TMP1]], [[TMP22]]
-; CHECK-NEXT:    [[TMP24:%.*]] = xor i32 [[TMP22]], -1
-; CHECK-NEXT:    [[TMP25:%.*]] = and i32 [[Y]], [[TMP24]]
-; CHECK-NEXT:    [[TMP26:%.*]] = or i32 [[TMP25]], [[TMP23]]
-; CHECK-NEXT:    [[TMP27:%.*]] = icmp slt i32 [[TMP20]], [[TMP26]]
-; CHECK-NEXT:    [[TMP2:%.*]] = xor i1 [[TMP14]], [[TMP27]]
+; CHECK-NEXT:    [[_MSPROP:%.*]] = or i32 [[TMP0]], [[TMP1]]
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp ne i32 [[_MSPROP]], 0
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X]], [[Y]]
 ; CHECK-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; CHECK-NEXT:    ret i1 [[CMP]]