[AMDGPU] Fix buffer offset validation per PR feedback

Resolving comments from review.

Author: aleksandar-amd

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

@@ -4548,24 +4548,19 @@ bool AMDGPUAsmParser::validateSMEMOffset(const MCInst &Inst,
 
   uint64_t Offset = Op.getImm();
   bool IsBuffer = AMDGPU::getSMEMIsBuffer(Opcode);
-  // GFX12+ S_BUFFER_*: InstOffset is signed 24, but must be positive
-  if (isGFX12Plus() && IsBuffer) {
-    const unsigned OffsetSize = 24;
-    if (!isUIntN(OffsetSize, Offset)) {
-      Error(getSMEMOffsetLoc(Operands),
-            Twine("expected a ") + Twine(OffsetSize - 1) + "-bit positive offset for S_BUFFER ops");
-      return false;
-    }
-    return true;
-  }
   if (AMDGPU::isLegalSMRDEncodedUnsignedOffset(getSTI(), Offset) ||
       AMDGPU::isLegalSMRDEncodedSignedOffset(getSTI(), Offset, IsBuffer))
     return true;
 
-  Error(getSMEMOffsetLoc(Operands),
-        isGFX12Plus()          ? "expected a 24-bit signed offset"
-        : (isVI() || IsBuffer) ? "expected a 20-bit unsigned offset"
-                               : "expected a 21-bit signed offset");
+  // Generate appropriate error message based on generation and buffer type
+  if (isGFX12Plus() && IsBuffer)
+    Error(getSMEMOffsetLoc(Operands),
+          "expected a 23-bit positive offset for S_BUFFER ops");
+  else
+    Error(getSMEMOffsetLoc(Operands),
+          isGFX12Plus()          ? "expected a 24-bit signed offset"
+          : (isVI() || IsBuffer) ? "expected a 20-bit unsigned offset"
+                                 : "expected a 21-bit signed offset");
 
   return false;
 }

llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

@@ -806,15 +806,14 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
   // Validate buffer offset for GFX12+ - must be positive
   if ((MCII->get(MI.getOpcode()).TSFlags &
        (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF)) &&
-      AMDGPU::isGFX12Plus(STI)) {
+      isGFX12Plus()) {
     int OffsetIdx =
         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::offset);
     if (OffsetIdx != -1) {
       uint32_t Imm = MI.getOperand(OffsetIdx).getImm();
       int64_t SignedOffset = SignExtend64<24>(Imm);
-      if (SignedOffset < 0) {
+      if (SignedOffset < 0)
         return MCDisassembler::Fail;
-      }
     }
   }
 

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

@@ -2945,8 +2945,14 @@ bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST,
 
 bool isLegalSMRDEncodedSignedOffset(const MCSubtargetInfo &ST,
                                     int64_t EncodedOffset, bool IsBuffer) {
-  if (isGFX12Plus(ST))
+  if (isGFX12Plus(ST)) {
+          // GFX12+ S_BUFFER_*: InstOffset is signed 24, but must be positive (23-bit)
+      if (IsBuffer) {
+        constexpr const unsigned OffsetSize = 23;
+        return isUIntN(OffsetSize, EncodedOffset);
+      }
     return isInt<24>(EncodedOffset);
+  }
 
   return !IsBuffer && hasSMRDSignedImmOffset(ST) && isInt<21>(EncodedOffset);
 }

llvm/test/MC/AMDGPU/gfx12_err.s

@@ -382,4 +382,4 @@ s_buffer_load_u16 s5, s[4:7], s0 offset:-1
 // GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: expected a 23-bit positive offset for S_BUFFER ops
 
 s_buffer_prefetch_data s[20:23], -1, s10, 7
-// GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: expected a 23-bit positive offset for S_BUFFER ops
+// GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: expected a 23-bit positive offset for S_BUFFER ops

llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_buffer_err.txt

@@ -22,4 +22,4 @@
 
 # tbuffer_load_format_x v0, off, s[4:7], s8 format:0 offset:-1
 # GFX12: warning: invalid instruction encoding
-[0x08,0x00,0x20,0xc4,0x00,0x08,0x00,0x00,0xff,0xff,0xff,0xff]
+[0x08,0x00,0x20,0xc4,0x00,0x08,0x00,0x00,0xff,0xff,0xff,0xff]