Merge pull request #295 from icedland/erets-update

Update `ERETS` instruction with info from latest Intel docs `346446-003.pdf`

Author: wtfsck

src/UnitTests/Intel/InstructionInfo/InstructionInfoTest_64.txt

@@ -19236,7 +19236,7 @@ F2 48 0F00 30, Lkgs_r64m16, Legacy, LKGS, priv op0=r r=rax w=gs rm=ds:rax;UInt16
 # eretu
 F3 0F 01 CA, Eretu, Legacy, FRED, priv flow=Return fw=acopszidA w=cs;ss;rsp rw=xsp rm=ss:xsp;UInt64 rm=ss:xsp+8;UInt64 rm=ss:xsp+0x10;UInt64 rm=ss:xsp+0x18;UInt64 rm=ss:xsp+0x20;UInt64 stack=40
 # erets
-F2 0F 01 CA, Erets, Legacy, FRED, priv flow=Return fw=acopszidA w=rsp rw=xsp rm=ss:xsp;UInt64 rm=ss:xsp+8;UInt64 rm=ss:xsp+0x10;UInt64 rm=ss:xsp+0x18;UInt64 rm=ss:xsp+0x20;UInt64 stack=40
+F2 0F 01 CA, Erets, Legacy, FRED, priv flow=Return fw=acopszidA w=rsp rw=xsp r=cs;ss rm=ss:xsp;UInt64 rm=ss:xsp+8;UInt64 rm=ss:xsp+0x10;UInt64 rm=ss:xsp+0x18;UInt64 rm=ss:xsp+0x20;UInt64 stack=40
 # vaddph xmm2,xmm6,[rax+10h]
 62 F54C08 58 50 01, EVEX_Vaddph_xmm_k1z_xmm_xmmm128b16, EVEX, AVX512VL;AVX512_FP16, op0=w op1=r op2=r w=vmm2 r=xmm6 r=rax rm=ds:rax+0x10;Packed128_Float16
 # vaddph xmm2{k3},xmm6,xmm3

src/csharp/Intel/Generator/Tables/InstructionDefs.txt

@@ -30110,7 +30110,7 @@ END
 
 # Code: Erets
 INSTRUCTION: F2 0F 01 CA | ERETS | FRED
-	implied: pop=5x8 w=rsp
+	implied: pop=5x8 w=rsp r=cs;ss
 	rflags: w=oszacpdiA
 	flags: 64 cpl0 sp=pop;40 cflow=ret
 END

src/csharp/Intel/Iced/Intel/InstructionInfoFactory.cs

@@ -1658,8 +1658,10 @@ void AddImpliedAccesses(ImpliedAccess impliedAccess, in Instruction instruction,
 				}
 				CommandPop(instruction, flags, 5, 8);
 				break;
-			case ImpliedAccess.t_Wrsp_pop5x8:
+			case ImpliedAccess.t_Rcs_Rss_Wrsp_pop5x8:
 				if ((flags & Flags.NoRegisterUsage) == 0) {
+					AddRegister(flags, Register.CS, OpAccess.Read);
+					AddRegister(flags, Register.SS, OpAccess.Read);
 					AddRegister(flags, Register.RSP, OpAccess.Write);
 				}
 				CommandPop(instruction, flags, 5, 8);

src/csharp/Intel/Iced/Intel/InstructionInfoInternal/InfoHandlerFlags.cs

@@ -329,7 +329,7 @@ enum ImpliedAccess {
 		t_CRmem_CRmem_CRmem_CWmem_CRrax_CRrdx_CRrbx_CRrsi_CRrdi_CRes_CWrsi_CWrdi_RCWrcx,
 		t_gpr16_Wgs,
 		t_Wrsp_Wcs_Wss_pop5x8,
-		t_Wrsp_pop5x8,
+		t_Rcs_Rss_Wrsp_pop5x8,
 		t_Reax_Recx_Wedx_Webx,
 		t_Reax_Recx_Redx_CRebx_CWedx_CWebx,
 		t_memdisplm64,

src/rust/iced-x86/src/info/enums.rs

@@ -482,7 +482,7 @@ pub(crate) enum ImpliedAccess {
 	t_CRmem_CRmem_CRmem_CWmem_CRrax_CRrdx_CRrbx_CRrsi_CRrdi_CRes_CWrsi_CWrdi_RCWrcx,
 	t_gpr16_Wgs,
 	t_Wrsp_Wcs_Wss_pop5x8,
-	t_Wrsp_pop5x8,
+	t_Rcs_Rss_Wrsp_pop5x8,
 	t_Reax_Recx_Wedx_Webx,
 	t_Reax_Recx_Redx_CRebx_CWedx_CWebx,
 	t_memdisplm64,
@@ -683,7 +683,7 @@ static GEN_DEBUG_IMPLIED_ACCESS: [&str; 197] = [
 	"t_CRmem_CRmem_CRmem_CWmem_CRrax_CRrdx_CRrbx_CRrsi_CRrdi_CRes_CWrsi_CWrdi_RCWrcx",
 	"t_gpr16_Wgs",
 	"t_Wrsp_Wcs_Wss_pop5x8",
-	"t_Wrsp_pop5x8",
+	"t_Rcs_Rss_Wrsp_pop5x8",
 	"t_Reax_Recx_Wedx_Webx",
 	"t_Reax_Recx_Redx_CRebx_CWedx_CWebx",
 	"t_memdisplm64",

src/rust/iced-x86/src/info/factory.rs

@@ -1844,8 +1844,10 @@ impl InstructionInfoFactory {
 				}
 				Self::command_pop(instruction, info, flags, 5, 8);
 			}
-			ImpliedAccess::t_Wrsp_pop5x8 => {
+			ImpliedAccess::t_Rcs_Rss_Wrsp_pop5x8 => {
 				if (flags & Flags::NO_REGISTER_USAGE) == 0 {
+					Self::add_register(flags, info, Register::CS, OpAccess::Read);
+					Self::add_register(flags, info, Register::SS, OpAccess::Read);
 					Self::add_register(flags, info, Register::RSP, OpAccess::Write);
 				}
 				Self::command_pop(instruction, info, flags, 5, 8);