Adding SystemVerilog versions of the demos

Author: fpgacademy

demos/accumulate/Accumulate.sv

@@ -0,0 +1,45 @@
+// Copyright (c) 2020 FPGAcademy
+// Please see license at https://github.com/fpgacademy/DESim
+
+// Protect against undefined nets
+`default_nettype none
+
+// This module represents an accumulator controlled by a down-counter.  The data being 
+// accumulated is from the SW[4:0] switches. KEY[0] is the active-low synchronous load
+// input. When KEY[0] is low the counter is loaded from switches SW[9:5]. When KEY[0] is 
+// high the circuit accumulates each clock cycle until the counter reaches 0
+module Accumulate (CLOCK, RESETn, SW, LEDR);
+    input   logic         CLOCK;
+    input   logic         RESETn;
+    input   logic [ 9: 0] SW;
+    output  logic [ 9: 0] LEDR;
+
+
+    logic         [ 4: 0] count;
+    logic         [ 9: 0] sum;
+    logic         [ 4: 0] x, y;
+    logic                 z;
+
+    assign x = SW[4:0];
+    assign y = SW[9:5];
+
+
+    // the accumulator
+    always_ff @(posedge CLOCK)
+        if (RESETn  == 1'b0)        // synchronous clear
+            sum <= 0;
+        else if (z == 1'b1)
+            sum <= sum + x;
+
+    // the counter
+    always_ff @(posedge CLOCK)
+        if (RESETn  == 1'b0)        // synchronous load
+            count <= y;
+        else if (z == 1'b1)
+            count <= count - 1'b1;
+
+
+    assign z    = | count;
+    assign LEDR = sum;
+
+endmodule

demos/accumulate/Top.sv

@@ -0,0 +1,16 @@
+// Copyright (c) 2020 FPGAcademy
+// Please see license at https://github.com/fpgacademy/DESim
+
+// Protect against undefined nets
+`default_nettype none
+
+module Top (CLOCK_50, KEY, SW, LEDR);
+    input  logic         CLOCK_50;   // DE-series 50 MHz clock signal
+    input  logic [ 3: 0] KEY;        // DE-series pushbuttons
+    input  logic [ 9: 0] SW;         // DE-series switches
+    output logic [ 9: 0] LEDR;       // DE-series LEDs
+
+    Accumulate U1 (CLOCK_50, KEY[0], SW, LEDR);
+
+endmodule
+

demos/accumulate/sim/run_compile.bat

@@ -5,6 +5,9 @@ vlog ../tb/*.v
 if exist ../*.v (
 	vlog ../*.v
 )
+if exist ../*.sv (
+	vlog ../*.sv
+)
 if exist ../*.vhd (
 	vcom ../*.vhd
 )

demos/accumulate/sim/run_compile.sh

@@ -10,6 +10,10 @@ if [ -f ../Top.v ]
 then
 	vlog ../*.v
 fi
+if [ -f ../Top.sv ]
+then
+	vlog ../*.sv
+fi
 if [ -f ../Top.vhd ]
 then
 	vcom ../*.vhd

demos/addern/Addern.sv

@@ -0,0 +1,18 @@
+// Copyright (c) 2020 FPGAcademy
+// Please see license at https://github.com/fpgacademy/DESim
+
+// Protect against undefined nets
+`default_nettype none
+
+// A multi-bit adder
+module Addern (Cin, X, Y, Sum, Cout);
+    parameter n = 4;
+
+    input  logic         Cin;
+    input  logic [n-1:0] X, Y;
+    output logic [n-1:0] Sum;
+    output logic         Cout;
+
+    assign {Cout, Sum} = X + Y + Cin;
+
+endmodule

demos/addern/Top.sv

@@ -0,0 +1,15 @@
+// Copyright (c) 2020 FPGAcademy
+// Please see license at https://github.com/fpgacademy/DESim
+
+// Protect against undefined nets
+`default_nettype none
+
+module Top (KEY, SW, LEDR);
+    input  logic [ 3: 0] KEY;        // DE-series pushbuttons
+    input  logic [ 9: 0] SW;         // DE-series switches
+    output logic [ 9: 0] LEDR;       // DE-series LEDs
+
+    Addern U1 (SW[9], SW[3:0], SW[7:4], LEDR[3:0], LEDR[4]);
+
+endmodule
+

demos/addern/sim/run_compile.bat

@@ -5,6 +5,9 @@ vlog ../tb/*.v
 if exist ../*.v (
 	vlog ../*.v
 )
+if exist ../*.sv (
+	vlog ../*.sv
+)
 if exist ../*.vhd (
 	vcom ../*.vhd
 )

demos/addern/sim/run_compile.sh

@@ -10,6 +10,10 @@ if [ -f ../Top.v ]
 then
 	vlog ../*.v
 fi
+if [ -f ../Top.sv ]
+then
+	vlog ../*.sv
+fi
 if [ -f ../Top.vhd ]
 then
 	vcom ../*.vhd

demos/counter/Counter.sv

@@ -0,0 +1,27 @@
+// Copyright (c) 2020 FPGAcademy
+// Please see license at https://github.com/fpgacademy/DESim
+
+// Protect against undefined nets
+`default_nettype none
+
+// This module implements an n-bit counter. Upper bits of the counter, driven by the 
+// 50 MHz clock signal, are displayed on the LEDR lights. The counter can be reset to 0
+// using KEY[0]. 
+module Counter (CLOCK, RESETn, LEDR);
+    input  logic         CLOCK;
+    input  logic         RESETn;
+    output logic [ 9: 0] LEDR;
+
+	parameter n = 24;
+   
+    logic         [n-1:0] count;
+
+    // the counter
+    always_ff @(posedge CLOCK)
+        if (RESETn  == 1'b0)        // synchronous clear
+            count <= 0;
+        else
+            count <= count + 1;
+
+    assign LEDR = count[n-1:n-10];
+endmodule

demos/counter/Top.sv

@@ -0,0 +1,15 @@
+// Copyright (c) 2020 FPGAcademy
+// Please see license at https://github.com/fpgacademy/DESim
+
+// Protect against undefined nets
+`default_nettype none
+
+module Top (CLOCK_50, KEY, LEDR);
+    input  logic         CLOCK_50;   // DE-series 50 MHz clock signal
+    input  logic [ 3: 0] KEY;        // DE-series pushbuttons
+    output logic [ 9: 0] LEDR;       // DE-series LEDs
+
+    Counter U1 (CLOCK_50, KEY[0], LEDR);
+
+endmodule
+