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| 1 | +-- megafunction wizard: %ROM: 1-PORT% |
| 2 | +-- GENERATION: STANDARD |
| 3 | +-- VERSION: WM1.0 |
| 4 | +-- MODULE: altsyncram |
| 5 | + |
| 6 | +-- ============================================================ |
| 7 | +-- File Name: inst_mem.vhd |
| 8 | +-- Megafunction Name(s): |
| 9 | +-- altsyncram |
| 10 | +-- |
| 11 | +-- Simulation Library Files(s): |
| 12 | +-- altera_mf |
| 13 | +-- ============================================================ |
| 14 | +-- ************************************************************ |
| 15 | +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! |
| 16 | +-- |
| 17 | +-- 21.1.0 Build 842 10/21/2021 SJ Standard Edition |
| 18 | +-- ************************************************************ |
| 19 | + |
| 20 | + |
| 21 | +--Copyright (C) 2021 Intel Corporation. All rights reserved. |
| 22 | +--Your use of Intel Corporation's design tools, logic functions |
| 23 | +--and other software and tools, and any partner logic |
| 24 | +--functions, and any output files from any of the foregoing |
| 25 | +--(including device programming or simulation files), and any |
| 26 | +--associated documentation or information are expressly subject |
| 27 | +--to the terms and conditions of the Intel Program License |
| 28 | +--Subscription Agreement, the Intel Quartus Prime License Agreement, |
| 29 | +--the Intel FPGA IP License Agreement, or other applicable license |
| 30 | +--agreement, including, without limitation, that your use is for |
| 31 | +--the sole purpose of programming logic devices manufactured by |
| 32 | +--Intel and sold by Intel or its authorized distributors. Please |
| 33 | +--refer to the applicable agreement for further details, at |
| 34 | +--https://fpgasoftware.intel.com/eula. |
| 35 | + |
| 36 | + |
| 37 | +LIBRARY ieee; |
| 38 | +USE ieee.std_logic_1164.all; |
| 39 | + |
| 40 | +LIBRARY altera_mf; |
| 41 | +USE altera_mf.altera_mf_components.all; |
| 42 | + |
| 43 | +ENTITY inst_mem IS |
| 44 | + PORT |
| 45 | + ( |
| 46 | + address : IN STD_LOGIC_VECTOR (4 DOWNTO 0); |
| 47 | + clock : IN STD_LOGIC := '1'; |
| 48 | + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) |
| 49 | + ); |
| 50 | +END inst_mem; |
| 51 | + |
| 52 | + |
| 53 | +ARCHITECTURE SYN OF inst_mem IS |
| 54 | + |
| 55 | + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); |
| 56 | + |
| 57 | +BEGIN |
| 58 | + q <= sub_wire0(7 DOWNTO 0); |
| 59 | + |
| 60 | + altsyncram_component : altsyncram |
| 61 | + GENERIC MAP ( |
| 62 | + address_aclr_a => "NONE", |
| 63 | + clock_enable_input_a => "BYPASS", |
| 64 | + clock_enable_output_a => "BYPASS", |
| 65 | + init_file => "inst_mem.mif", |
| 66 | + intended_device_family => "MAX 10", |
| 67 | + lpm_hint => "ENABLE_RUNTIME_MOD=NO", |
| 68 | + lpm_type => "altsyncram", |
| 69 | + numwords_a => 32, |
| 70 | + operation_mode => "ROM", |
| 71 | + outdata_aclr_a => "NONE", |
| 72 | + outdata_reg_a => "UNREGISTERED", |
| 73 | + widthad_a => 5, |
| 74 | + width_a => 8, |
| 75 | + width_byteena_a => 1 |
| 76 | + ) |
| 77 | + PORT MAP ( |
| 78 | + address_a => address, |
| 79 | + clock0 => clock, |
| 80 | + q_a => sub_wire0 |
| 81 | + ); |
| 82 | + |
| 83 | + |
| 84 | + |
| 85 | +END SYN; |
| 86 | + |
| 87 | +-- ============================================================ |
| 88 | +-- CNX file retrieval info |
| 89 | +-- ============================================================ |
| 90 | +-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" |
| 91 | +-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" |
| 92 | +-- Retrieval info: PRIVATE: AclrByte NUMERIC "0" |
| 93 | +-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" |
| 94 | +-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" |
| 95 | +-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" |
| 96 | +-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" |
| 97 | +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" |
| 98 | +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" |
| 99 | +-- Retrieval info: PRIVATE: Clken NUMERIC "0" |
| 100 | +-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" |
| 101 | +-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" |
| 102 | +-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" |
| 103 | +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10" |
| 104 | +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" |
| 105 | +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" |
| 106 | +-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" |
| 107 | +-- Retrieval info: PRIVATE: MIFfilename STRING "inst_mem.mif" |
| 108 | +-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32" |
| 109 | +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" |
| 110 | +-- Retrieval info: PRIVATE: RegAddr NUMERIC "1" |
| 111 | +-- Retrieval info: PRIVATE: RegOutput NUMERIC "0" |
| 112 | +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" |
| 113 | +-- Retrieval info: PRIVATE: SingleClock NUMERIC "1" |
| 114 | +-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" |
| 115 | +-- Retrieval info: PRIVATE: WidthAddr NUMERIC "5" |
| 116 | +-- Retrieval info: PRIVATE: WidthData NUMERIC "8" |
| 117 | +-- Retrieval info: PRIVATE: rden NUMERIC "0" |
| 118 | +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all |
| 119 | +-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" |
| 120 | +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" |
| 121 | +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" |
| 122 | +-- Retrieval info: CONSTANT: INIT_FILE STRING "inst_mem.mif" |
| 123 | +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10" |
| 124 | +-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" |
| 125 | +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" |
| 126 | +-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32" |
| 127 | +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" |
| 128 | +-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" |
| 129 | +-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" |
| 130 | +-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5" |
| 131 | +-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" |
| 132 | +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" |
| 133 | +-- Retrieval info: USED_PORT: address 0 0 5 0 INPUT NODEFVAL "address[4..0]" |
| 134 | +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" |
| 135 | +-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" |
| 136 | +-- Retrieval info: CONNECT: @address_a 0 0 5 0 address 0 0 5 0 |
| 137 | +-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 |
| 138 | +-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 |
| 139 | +-- Retrieval info: GEN_FILE: TYPE_NORMAL inst_mem.vhd TRUE |
| 140 | +-- Retrieval info: GEN_FILE: TYPE_NORMAL inst_mem.inc FALSE |
| 141 | +-- Retrieval info: GEN_FILE: TYPE_NORMAL inst_mem.cmp FALSE |
| 142 | +-- Retrieval info: GEN_FILE: TYPE_NORMAL inst_mem.bsf FALSE |
| 143 | +-- Retrieval info: GEN_FILE: TYPE_NORMAL inst_mem_inst.vhd FALSE |
| 144 | +-- Retrieval info: LIB_FILE: altera_mf |
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