Generation of .xclbin using Vitis backend on Alveo u280

[rajib216]

Hi!
I am trying to figure out how to generate a .xclbin file for my model while using Vitis backend with Xilinx 2023.1 version (my target hardware is alveo u280 acceleration card). For VivadoAccelerator backend there was this option to call the make_xclbin method to do the job but I do not how to do the same with the Vitis backend. Following is my hls4ml config:

import hls4ml
from hls4ml.model.profiling import numerical
from utils import plotting
hls4ml.model.optimizer.get_optimizer('output_rounding_saturation_mode').configure(layers=['softmax'], rounding_mode='AP_RND', saturation_mode='AP_SAT')

Trace = True

config = hls4ml.utils.config_from_keras_model(model, granularity='name')

config['Model'] = {}
config['Model']['ReuseFactor'] = 36
config['Model']['Strategy'] = 'Resource'
config['Model']['Precision'] = 'ap_fixed<16,6>'

config['LayerName']['layer0']['Precision'] = 'ap_ufixed<8,3>'

config['LayerName']['q_dense']['ReuseFactor'] = 28
config['LayerName']['q_dense']['Precision']['result'] = 'ap_fixed<9,4>'
config['LayerName']['q_dense']['Trace'] = Trace

config['LayerName']['q_dense_1']['ReuseFactor'] = 20
config['LayerName']['q_dense_1']['Precision']['result'] = 'ap_fixed<8,4>'
config['LayerName']['q_dense_1']['Trace'] = Trace

config['LayerName']['softmax']['exp_table_t'] = 'ap_fixed<12,4>'
config['LayerName']['softmax']['inv_table_t'] = 'ap_fixed<12,2>'
config['LayerName']['softmax']['table_size'] = 1024
config['LayerName']['softmax']['Precision'] = 'ap_fixed<14,2>'
config['LayerName']['softmax']['Strategy'] = 'Stable'
config['LayerName']['softmax']['Trace'] = Trace

cfg = hls4ml.converters.create_config(board='alveo-u280', clock_period= 2, part='xcu280-fsvh2892-2L-e', backend='Vitis')
cfg['HLSConfig'] = config

cfg['IOType']= 'io_stream'I4 master ports
cfg['KerasModel'] = model
cfg['OutputDir'] = PROJECT_PATH + 'Qkeras_pruned_Dense/hls4ml_PYNQ_prj'

print("-----------------------------------")
print("..........Plotting Config.........")
plotting.print_dict(cfg)
print("-----------------------------------")
hls_model = hls4ml.converters.keras_to_hls(cfg)
hls4ml.model.optimizer.get_optimizer('output_rounding_saturation_mode').configure(layers=[])
numerical(model=model, hls_model=hls_model, X=x_test[:1000])

hls_model.build(csim=False,synth=True,export=True)

After that I use the following command to generate the .xo file:
vitis_hls -f export_both.tcl -l export_xo.log -nolog

[I am also attaching the tcl script]

export_both.tcl.txt
After that I run the following command to generate my .xclbin file:

export PLATFORM=xilinx_u280_gen3x16_xdma_1_202211_1
v++ --link -t hw --platform $PLATFORM
xo_files/myproject.xo
-o myproject.xclbin

I could get upto the .xo file generation, but while running command for .xclbin generation I face the following errors:
INFO: [CFGEN 83-0] Kernel Specs:
INFO: [CFGEN 83-0] kernel: myproject, num: 1 {myproject_1}
ERROR: [CFGEN 83-2284] No stream resources found that can accomodate compute unit "myproject_1.layer0"
ERROR: [SYSTEM_LINK 82-36] [19:11:21] cfgen failed
Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 439.691 ; gain = 0.000 ; free physical = 567555 ; f>ERROR: [SYSTEM_LINK 82-62] Error generating design file for /var/services/homes/bhasan/Alveo-tutorial/training/MNIST_Te>ERROR: [SYSTEM_LINK 82-96] Error applying explicit connections to the system connectivity graph
ERROR: [SYSTEM_LINK 82-79] Unable to create system connectivity graph
INFO: [v++ 60-1442] [19:11:21] Run run_link: Step system_link: Failed
Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 456.398 ; gain = 0.000 ; free physical = 567761 ; f>ERROR: [v++ 60-661] v++ link run 'run_link' failed
ERROR: [v++ 60-626] Kernel link failed to complete
ERROR: [v++ 60-703] Failed to finish linking

[bo3z]

You can check out the Vitis Accelerator backend, in PR #991.