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We can also design circuits with the existing gates (see [this example](./tests/circuits_test.rs)) and then print a wire that you have to see its gates, everything is composed of `+` and `*` gates only!
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We can also design circuits with the existing gates (see [this example](./tests/circuits_test.rs)) and then print a wire's lavel to see its gates, everything is composed of `+` and `*` only!
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