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amanasifkhalidamanasifkhalid
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JIT: Fix ARM64 emitter tests (#117768)
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‎src/coreclr/jit/codegenarm64test.cpp‎

Lines changed: 34 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -4685,11 +4685,13 @@ void CodeGen::genArm64EmitterUnitTestsSve()
46854685
theEmitter->emitIns_R_R_R(INS_sve_urshlr, EA_SCALABLE, REG_V15, REG_P2, REG_V20,
46864686
INS_OPTS_SCALABLE_D); // URSHLR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
46874687

4688+
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
46884689
// IF_SVE_AB_3B
46894690
theEmitter->emitIns_R_R_R(INS_sve_addpt, EA_SCALABLE, REG_V0, REG_P1, REG_V2,
46904691
INS_OPTS_SCALABLE_D); // ADDPT <Zdn>.D, <Pg>/M, <Zdn>.D, <Zm>.D
46914692
theEmitter->emitIns_R_R_R(INS_sve_subpt, EA_SCALABLE, REG_V0, REG_P1, REG_V2,
46924693
INS_OPTS_SCALABLE_D); // SUBPT <Zdn>.D, <Pg>/M, <Zdn>.D, <Zm>.D
4694+
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
46934695

46944696
// IF_SVE_AC_3A
46954697
theEmitter->emitIns_R_R_R(INS_sve_sdiv, EA_SCALABLE, REG_V3, REG_P2, REG_V9,
@@ -5117,10 +5119,12 @@ void CodeGen::genArm64EmitterUnitTestsSve()
51175119
INS_OPTS_SCALABLE_H); // FABD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
51185120
theEmitter->emitIns_R_R_R(INS_sve_fadd, EA_SCALABLE, REG_V25, REG_P2, REG_V10,
51195121
INS_OPTS_SCALABLE_S); // FADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
5122+
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
51205123
theEmitter->emitIns_R_R_R(INS_sve_famax, EA_SCALABLE, REG_V26, REG_P1, REG_V9,
51215124
INS_OPTS_SCALABLE_D); // FAMAX <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
51225125
theEmitter->emitIns_R_R_R(INS_sve_famin, EA_SCALABLE, REG_V27, REG_P0, REG_V8,
51235126
INS_OPTS_SCALABLE_H); // FAMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
5127+
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
51245128
theEmitter->emitIns_R_R_R(INS_sve_fdiv, EA_SCALABLE, REG_V28, REG_P0, REG_V7,
51255129
INS_OPTS_SCALABLE_S); // FDIV <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
51265130
theEmitter->emitIns_R_R_R(INS_sve_fdivr, EA_SCALABLE, REG_V29, REG_P1, REG_V6,
@@ -5288,6 +5292,7 @@ void CodeGen::genArm64EmitterUnitTestsSve()
52885292
theEmitter->emitIns_R_R_R(INS_sve_orv, EA_SCALABLE, REG_V3, REG_P3, REG_V3,
52895293
INS_OPTS_SCALABLE_D); // ORV <V><d>, <Pg>, <Zn>.<T>
52905294

5295+
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
52915296
// IF_SVE_AG_3A
52925297
theEmitter->emitIns_R_R_R(INS_sve_andqv, EA_8BYTE, REG_V4, REG_P4, REG_V4,
52935298
INS_OPTS_SCALABLE_B); // ANDQV <Vd>.<T>, <Pg>, <Zn>.<Tb>
@@ -5298,6 +5303,11 @@ void CodeGen::genArm64EmitterUnitTestsSve()
52985303
theEmitter->emitIns_R_R_R(INS_sve_orqv, EA_8BYTE, REG_V7, REG_P7, REG_V7,
52995304
INS_OPTS_SCALABLE_D); // ORQV <Vd>.<T>, <Pg>, <Zn>.<Tb>
53005305

5306+
// IF_SVE_AJ_3A
5307+
theEmitter->emitIns_R_R_R(INS_sve_addqv, EA_8BYTE, REG_V21, REG_P7, REG_V22,
5308+
INS_OPTS_SCALABLE_B); // ADDQV <Vd>.<T>, <Pg>, <Zn>.<Tb>
5309+
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
5310+
53015311
// IF_SVE_AI_3A
53025312
theEmitter->emitIns_R_R_R(INS_sve_saddv, EA_SCALABLE, REG_V1, REG_P4, REG_V2,
53035313
INS_OPTS_SCALABLE_B); // SADDV <Dd>, <Pg>, <Zn>.<T>
@@ -5306,10 +5316,6 @@ void CodeGen::genArm64EmitterUnitTestsSve()
53065316
theEmitter->emitIns_R_R_R(INS_sve_uaddv, EA_SCALABLE, REG_V3, REG_P6, REG_V4,
53075317
INS_OPTS_SCALABLE_S); // UADDV <Dd>, <Pg>, <Zn>.<T>
53085318

5309-
// IF_SVE_AJ_3A
5310-
theEmitter->emitIns_R_R_R(INS_sve_addqv, EA_8BYTE, REG_V21, REG_P7, REG_V22,
5311-
INS_OPTS_SCALABLE_B); // ADDQV <Vd>.<T>, <Pg>, <Zn>.<Tb>
5312-
53135319
// IF_SVE_AK_3A
53145320
theEmitter->emitIns_R_R_R(INS_sve_smaxv, EA_SCALABLE, REG_V15, REG_P7, REG_V4,
53155321
INS_OPTS_SCALABLE_D); // SMAXV <V><d>, <Pg>, <Zn>.<T>
@@ -5320,6 +5326,7 @@ void CodeGen::genArm64EmitterUnitTestsSve()
53205326
theEmitter->emitIns_R_R_R(INS_sve_uminv, EA_SCALABLE, REG_V18, REG_P4, REG_V31,
53215327
INS_OPTS_SCALABLE_B); // UMINV <V><d>, <Pg>, <Zn>.<T>
53225328

5329+
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
53235330
// IF_SVE_AL_3A
53245331
theEmitter->emitIns_R_R_R(INS_sve_smaxqv, EA_8BYTE, REG_V0, REG_P5, REG_V25,
53255332
INS_OPTS_SCALABLE_B); // SMAXQV <Vd>.<T>, <Pg>, <Zn>.<Tb>
@@ -5329,6 +5336,7 @@ void CodeGen::genArm64EmitterUnitTestsSve()
53295336
INS_OPTS_SCALABLE_S); // UMAXQV <Vd>.<T>, <Pg>, <Zn>.<Tb>
53305337
theEmitter->emitIns_R_R_R(INS_sve_uminqv, EA_8BYTE, REG_V3, REG_P2, REG_V22,
53315338
INS_OPTS_SCALABLE_D); // UMINQV <Vd>.<T>, <Pg>, <Zn>.<Tb>
5339+
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
53325340

53335341
// IF_SVE_AP_3A
53345342
theEmitter->emitIns_R_R_R(INS_sve_cls, EA_SCALABLE, REG_V31, REG_P0, REG_V0,
@@ -5884,11 +5892,13 @@ void CodeGen::genArm64EmitterUnitTestsSve()
58845892
theEmitter->emitIns_R_R_R(INS_sve_bfsub, EA_SCALABLE, REG_V6, REG_V7, REG_V8,
58855893
INS_OPTS_SCALABLE_H); // BFSUB <Zd>.H, <Zn>.H, <Zm>.H
58865894

5895+
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
58875896
// IF_SVE_AT_3B
58885897
theEmitter->emitIns_R_R_R(INS_sve_addpt, EA_SCALABLE, REG_V0, REG_V1, REG_V2,
58895898
INS_OPTS_SCALABLE_D); // ADDPT <Zd>.D, <Zn>.D, <Zm>.D
58905899
theEmitter->emitIns_R_R_R(INS_sve_subpt, EA_SCALABLE, REG_V3, REG_V4, REG_V5,
58915900
INS_OPTS_SCALABLE_D); // SUBPT <Zd>.D, <Zn>.D, <Zm>.D
5901+
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
58925902

58935903
// IF_SVE_AU_3A
58945904
theEmitter->emitIns_R_R_R(INS_sve_and, EA_SCALABLE, REG_V0, REG_V1, REG_V2, INS_OPTS_SCALABLE_D); // AND <Zd>.D,
@@ -6093,6 +6103,7 @@ void CodeGen::genArm64EmitterUnitTestsSve()
60936103
theEmitter->emitIns_R_PATTERN_I(INS_sve_uqincw, EA_SCALABLE, REG_V11, SVE_PATTERN_ALL, 16,
60946104
INS_OPTS_SCALABLE_S); // UQINCW <Zdn>.S{, <pattern>{, MUL #<imm>}}
60956105

6106+
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
60966107
// IF_SVE_BQ_2A
60976108
theEmitter->emitIns_R_R_I(INS_sve_ext, EA_SCALABLE, REG_V0, REG_V1, 0, INS_OPTS_SCALABLE_B,
60986109
INS_SCALABLE_OPTS_WITH_VECTOR_PAIR); // EXT <Zd>.B, {<Zn1>.B, <Zn2>.B }, #<imm>
@@ -6102,6 +6113,7 @@ void CodeGen::genArm64EmitterUnitTestsSve()
61026113
INS_SCALABLE_OPTS_WITH_VECTOR_PAIR); // EXT <Zd>.B, {<Zn1>.B, <Zn2>.B }, #<imm>
61036114
theEmitter->emitIns_R_R_I(INS_sve_ext, EA_SCALABLE, REG_V6, REG_FP_LAST, 255, INS_OPTS_SCALABLE_B,
61046115
INS_SCALABLE_OPTS_WITH_VECTOR_PAIR); // EXT <Zd>.B, {<Zn1>.B, <Zn2>.B }, #<imm>
6116+
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
61056117

61066118
// IF_SVE_BQ_2B
61076119
theEmitter->emitIns_R_R_I(INS_sve_ext, EA_SCALABLE, REG_V0, REG_V1, 0,
@@ -6283,11 +6295,13 @@ void CodeGen::genArm64EmitterUnitTestsSve()
62836295
theEmitter->emitIns_R_R(INS_sve_sqcvtun, EA_SCALABLE, REG_V6, REG_V8); // SQCVTUN <Zd>.H, {<Zn1>.S-<Zn2>.S }
62846296
theEmitter->emitIns_R_R(INS_sve_uqcvtn, EA_SCALABLE, REG_V14, REG_V16); // UQCVTN <Zd>.H, {<Zn1>.S-<Zn2>.S }
62856297

6298+
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
62866299
// IF_SVE_HG_2A
62876300
theEmitter->emitIns_R_R(INS_sve_bfcvtn, EA_SCALABLE, REG_V0, REG_V2); // BFCVTN <Zd>.B, {<Zn1>.H-<Zn2>.H }
62886301
theEmitter->emitIns_R_R(INS_sve_fcvtn, EA_SCALABLE, REG_V2, REG_V4); // FCVTN <Zd>.B, {<Zn1>.H-<Zn2>.H }
62896302
theEmitter->emitIns_R_R(INS_sve_fcvtnb, EA_SCALABLE, REG_V6, REG_V8); // FCVTNB <Zd>.B, {<Zn1>.S-<Zn2>.S }
62906303
theEmitter->emitIns_R_R(INS_sve_fcvtnt, EA_SCALABLE, REG_V14, REG_V16); // FCVTNT <Zd>.B, {<Zn1>.S-<Zn2>.S }
6304+
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
62916305

62926306
// IF_SVE_GA_2A
62936307
theEmitter->emitIns_R_R_I(INS_sve_sqrshrn, EA_SCALABLE, REG_V0, REG_V0, 5,
@@ -6522,6 +6536,7 @@ void CodeGen::genArm64EmitterUnitTestsSve()
65226536
theEmitter->emitIns_R(INS_sve_aesimc, EA_SCALABLE, REG_V0); // AESIMC <Zdn>.B, <Zdn>.B
65236537
theEmitter->emitIns_R(INS_sve_aesmc, EA_SCALABLE, REG_V5); // AESMC <Zdn>.B, <Zdn>.B
65246538

6539+
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
65256540
// IF_SVE_GN_3A
65266541
theEmitter->emitIns_R_R_R(INS_sve_fmlalb, EA_SCALABLE, REG_V0, REG_V1, REG_V2,
65276542
INS_OPTS_SCALABLE_B); // FMLALB <Zda>.H, <Zn>.B, <Zm>.B
@@ -6549,6 +6564,7 @@ void CodeGen::genArm64EmitterUnitTestsSve()
65496564
INS_OPTS_SCALABLE_H); // FMINNMQV <Vd>.<T>, <Pg>, <Zn>.<Tb>
65506565
theEmitter->emitIns_R_R_R(INS_sve_fminqv, EA_8BYTE, REG_V20, REG_P5, REG_V8,
65516566
INS_OPTS_SCALABLE_D); // FMINQV <Vd>.<T>, <Pg>, <Zn>.<Tb>
6567+
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
65526568

65536569
// IF_SVE_GU_3A
65546570
theEmitter->emitIns_R_R_R_I(INS_sve_fmla, EA_SCALABLE, REG_V0, REG_V2, REG_V1, 0,
@@ -6630,6 +6646,7 @@ void CodeGen::genArm64EmitterUnitTestsSve()
66306646
theEmitter->emitIns_R_R_R_I(INS_sve_bfdot, EA_SCALABLE, REG_V12, REG_V14, REG_V7, 3,
66316647
INS_OPTS_SCALABLE_H); // BFDOT <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
66326648

6649+
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
66336650
// IF_SVE_GY_3A
66346651
theEmitter->emitIns_R_R_R_I(INS_sve_fdot, EA_SCALABLE, REG_V0, REG_V2, REG_V1,
66356652
1); // FDOT <Zda>.H, <Zn>.B, <Zm>.B[<imm>]
@@ -6649,6 +6666,7 @@ void CodeGen::genArm64EmitterUnitTestsSve()
66496666
INS_OPTS_SCALABLE_B); // FDOT <Zda>.S, <Zn>.B, <Zm>.B[<imm>]
66506667
theEmitter->emitIns_R_R_R_I(INS_sve_fdot, EA_SCALABLE, REG_V12, REG_V14, REG_V7, 3,
66516668
INS_OPTS_SCALABLE_B); // FDOT <Zda>.S, <Zn>.B, <Zm>.B[<imm>]
6669+
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
66526670

66536671
// IF_SVE_GZ_3A
66546672
theEmitter->emitIns_R_R_R_I(INS_sve_bfmlalb, EA_SCALABLE, REG_V0, REG_V1, REG_V0, 0,
@@ -6674,12 +6692,14 @@ void CodeGen::genArm64EmitterUnitTestsSve()
66746692
theEmitter->emitIns_R_R_R(INS_sve_fdot, EA_SCALABLE, REG_V3, REG_V4, REG_V5,
66756693
INS_OPTS_SCALABLE_H); // FDOT <Zda>.S, <Zn>.H, <Zm>.H
66766694

6695+
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
66776696
// IF_SVE_HA_3A_E
66786697
theEmitter->emitIns_R_R_R(INS_sve_fdot, EA_SCALABLE, REG_V6, REG_V7, REG_V8,
66796698
INS_OPTS_SCALABLE_B); // FDOT <Zda>.H, <Zn>.B, <Zm>.B
66806699

66816700
// IF_SVE_HA_3A_F
66826701
theEmitter->emitIns_R_R_R(INS_sve_fdot, EA_SCALABLE, REG_V9, REG_V10, REG_V11); // FDOT <Zda>.S, <Zn>.B, <Zm>.B
6702+
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
66836703

66846704
// IF_SVE_HB_3A
66856705
theEmitter->emitIns_R_R_R(INS_sve_bfmlalb, EA_SCALABLE, REG_V0, REG_V1, REG_V2,
@@ -6703,9 +6723,11 @@ void CodeGen::genArm64EmitterUnitTestsSve()
67036723
theEmitter->emitIns_R_R_R(INS_sve_bfmmla, EA_SCALABLE, REG_V0, REG_V1, REG_V2,
67046724
INS_OPTS_SCALABLE_H); // BFMMLA <Zda>.S, <Zn>.H, <Zm>.H
67056725

6726+
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
67066727
// IF_SVE_HD_3A_A
67076728
theEmitter->emitIns_R_R_R(INS_sve_fmmla, EA_SCALABLE, REG_V3, REG_V4, REG_V5,
67086729
INS_OPTS_SCALABLE_D); // FMMLA <Zda>.D, <Zn>.D, <Zm>.D
6730+
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
67096731

67106732
// IF_SVE_HE_3A
67116733
theEmitter->emitIns_R_R_R(INS_sve_faddv, EA_SCALABLE, REG_V21, REG_P7, REG_V7,
@@ -6793,6 +6815,7 @@ void CodeGen::genArm64EmitterUnitTestsSve()
67936815
theEmitter->emitIns_R_R_R(INS_sve_whilewr, EA_8BYTE, REG_P7, REG_R14, REG_R15,
67946816
INS_OPTS_SCALABLE_D); // WHILEWR <Pd>.<T>, <Xn>, <Xm>
67956817

6818+
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
67966819
// IF_SVE_DV_4A
67976820
theEmitter->emitIns_R_R_R_R_I(INS_sve_psel, EA_SCALABLE, REG_P0, REG_P1, REG_P2, REG_R12, 15,
67986821
INS_OPTS_SCALABLE_B); // PSEL <Pd>, <Pn>, <Pm>.<T>[<Wv>, <imm>]
@@ -6802,6 +6825,7 @@ void CodeGen::genArm64EmitterUnitTestsSve()
68026825
INS_OPTS_SCALABLE_S); // PSEL <Pd>, <Pn>, <Pm>.<T>[<Wv>, <imm>]
68036826
theEmitter->emitIns_R_R_R_R_I(INS_sve_psel, EA_SCALABLE, REG_P9, REG_P10, REG_P11, REG_R15, 1,
68046827
INS_OPTS_SCALABLE_D); // PSEL <Pd>, <Pn>, <Pm>.<T>[<Wv>, <imm>]
6828+
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
68056829

68066830
// IF_SVE_DW_2A
68076831
theEmitter->emitIns_R_R_I(INS_sve_pext, EA_SCALABLE, REG_P0, REG_P8, 0,
@@ -6968,11 +6992,13 @@ void CodeGen::genArm64EmitterUnitTestsSve()
69686992
theEmitter->emitIns_R_R_R_I(INS_sve_sqrdcmlah, EA_SCALABLE, REG_V21, REG_V22, REG_V23, 270,
69696993
INS_OPTS_SCALABLE_D); // SQRDCMLAH <Zda>.<T>, <Zn>.<T>, <Zm>.<T>, <const>
69706994

6995+
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
69716996
// IF_SVE_EW_3A
69726997
theEmitter->emitIns_R_R_R(INS_sve_mlapt, EA_SCALABLE, REG_V0, REG_V1, REG_V2); // MLAPT <Zda>.D, <Zn>.D, <Zm>.D
69736998

69746999
// IF_SVE_EW_3B
69757000
theEmitter->emitIns_R_R_R(INS_sve_madpt, EA_SCALABLE, REG_V3, REG_V4, REG_V5); // MADPT <Zdn>.D, <Zm>.D, <Za>.D
7001+
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
69767002

69777003
// IF_SVE_EY_3A
69787004
theEmitter->emitIns_R_R_R_I(INS_sve_sdot, EA_SCALABLE, REG_V9, REG_V10, REG_V4, 0,
@@ -8512,6 +8538,7 @@ void CodeGen::genArm64EmitterUnitTestsSve()
85128538
theEmitter->emitIns_R_R_I(INS_sve_str, EA_SCALABLE, REG_V2, REG_R3, -256, INS_OPTS_NONE);
85138539
theEmitter->emitIns_R_R_I(INS_sve_str, EA_SCALABLE, REG_V2, REG_R3, 255, INS_OPTS_NONE);
85148540

8541+
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
85158542
// IF_SVE_GG_3A
85168543
// LUTI2 <Zd>.B, {<Zn>.B }, <Zm>[<index>]
85178544
// luti2 z0.b, {z0.b}, z0[0] // 01000101-00100000-10110000-00000000
@@ -8581,6 +8608,7 @@ void CodeGen::genArm64EmitterUnitTestsSve()
85818608
// CHECK-INST: luti4 z31.b, { z31.b }, z31[1]
85828609
// CHECK-ENCODING: [0xff,0xa7,0xff,0x45]
85838610
theEmitter->emitIns_R_R_R_I(INS_sve_luti4, EA_SCALABLE, REG_V31, REG_V31, REG_V31, 1, INS_OPTS_SCALABLE_B);
8611+
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
85848612

85858613
// IF_SVE_HY_3A
85868614
theEmitter->emitIns_PRFOP_R_R_R(INS_sve_prfb, EA_SCALABLE, SVE_PRFOP_PLDL1KEEP, REG_P1, REG_R2, REG_V3,
@@ -8876,6 +8904,7 @@ void CodeGen::genArm64EmitterUnitTestsSve()
88768904
// FEXPA <Zd>.<T>, <Zn>.<T>
88778905
theEmitter->emitIns_R_R(INS_sve_fexpa, EA_SCALABLE, REG_V1, REG_V0, INS_OPTS_SCALABLE_D);
88788906

8907+
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
88798908
// IF_SVE_HH_2A
88808909
// BF1CVT <Zd>.H, <Zn>.B
88818910
theEmitter->emitIns_R_R(INS_sve_bf1cvt, EA_SCALABLE, REG_V2, REG_V3, INS_OPTS_SCALABLE_H);
@@ -8893,6 +8922,7 @@ void CodeGen::genArm64EmitterUnitTestsSve()
88938922
theEmitter->emitIns_R_R(INS_sve_f2cvt, EA_SCALABLE, REG_V3, REG_V4, INS_OPTS_SCALABLE_H);
88948923
// F2CVTLT <Zd>.H, <Zn>.B
88958924
theEmitter->emitIns_R_R(INS_sve_f2cvtlt, EA_SCALABLE, REG_V1, REG_V2, INS_OPTS_SCALABLE_H);
8925+
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
88968926

88978927
// IF_SVE_BI_2A
88988928
// MOVPRFX <Zd>, <Zn>

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