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jacob-crawleyjacob-crawley
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Remove ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED flag
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+27
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‎src/coreclr/jit/codegenarm64test.cpp‎

Lines changed: 27 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -4685,13 +4685,11 @@ void CodeGen::genArm64EmitterUnitTestsSve()
46854685
theEmitter->emitIns_R_R_R(INS_sve_urshlr, EA_SCALABLE, REG_V15, REG_P2, REG_V20,
46864686
INS_OPTS_SCALABLE_D); // URSHLR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
46874687

4688-
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
46894688
// IF_SVE_AB_3B
46904689
theEmitter->emitIns_R_R_R(INS_sve_addpt, EA_SCALABLE, REG_V0, REG_P1, REG_V2,
46914690
INS_OPTS_SCALABLE_D); // ADDPT <Zdn>.D, <Pg>/M, <Zdn>.D, <Zm>.D
46924691
theEmitter->emitIns_R_R_R(INS_sve_subpt, EA_SCALABLE, REG_V0, REG_P1, REG_V2,
46934692
INS_OPTS_SCALABLE_D); // SUBPT <Zdn>.D, <Pg>/M, <Zdn>.D, <Zm>.D
4694-
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
46954693

46964694
// IF_SVE_AC_3A
46974695
theEmitter->emitIns_R_R_R(INS_sve_sdiv, EA_SCALABLE, REG_V3, REG_P2, REG_V9,
@@ -5119,12 +5117,10 @@ void CodeGen::genArm64EmitterUnitTestsSve()
51195117
INS_OPTS_SCALABLE_H); // FABD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
51205118
theEmitter->emitIns_R_R_R(INS_sve_fadd, EA_SCALABLE, REG_V25, REG_P2, REG_V10,
51215119
INS_OPTS_SCALABLE_S); // FADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
5122-
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
5123-
theEmitter->emitIns_R_R_R(INS_sve_famax, EA_SCALABLE, REG_V26, REG_P1, REG_V9, INS_OPTS_SCALABLE_D);
5124-
// FAMAX <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
5125-
theEmitter->emitIns_R_R_R(INS_sve_famin, EA_SCALABLE, REG_V27, REG_P0, REG_V8, INS_OPTS_SCALABLE_H);
5126-
// FAMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
5127-
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
5120+
theEmitter->emitIns_R_R_R(INS_sve_famax, EA_SCALABLE, REG_V26, REG_P1, REG_V9,
5121+
INS_OPTS_SCALABLE_D); // FAMAX <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
5122+
theEmitter->emitIns_R_R_R(INS_sve_famin, EA_SCALABLE, REG_V27, REG_P0, REG_V8,
5123+
INS_OPTS_SCALABLE_H); // FAMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
51285124
theEmitter->emitIns_R_R_R(INS_sve_fdiv, EA_SCALABLE, REG_V28, REG_P0, REG_V7,
51295125
INS_OPTS_SCALABLE_S); // FDIV <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
51305126
theEmitter->emitIns_R_R_R(INS_sve_fdivr, EA_SCALABLE, REG_V29, REG_P1, REG_V6,
@@ -5292,17 +5288,15 @@ void CodeGen::genArm64EmitterUnitTestsSve()
52925288
theEmitter->emitIns_R_R_R(INS_sve_orv, EA_SCALABLE, REG_V3, REG_P3, REG_V3,
52935289
INS_OPTS_SCALABLE_D); // ORV <V><d>, <Pg>, <Zn>.<T>
52945290

5295-
// IF_SVE_AG_3A
5296-
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
5297-
theEmitter->emitIns_R_R_R(INS_sve_andqv, EA_8BYTE, REG_V4, REG_P4, REG_V4, INS_OPTS_SCALABLE_B);
5298-
// ANDQV <Vd>.<T>, <Pg>, <Zn>.<Tb>
5299-
theEmitter->emitIns_R_R_R(INS_sve_eorqv, EA_8BYTE, REG_V5, REG_P5, REG_V5, INS_OPTS_SCALABLE_H);
5300-
// EORQV <Vd>.<T>, <Pg>, <Zn>.<Tb>
5301-
theEmitter->emitIns_R_R_R(INS_sve_orqv, EA_8BYTE, REG_V6, REG_P6, REG_V6, INS_OPTS_SCALABLE_S);
5302-
// ORQV <Vd>.<T>, <Pg>, <Zn>.<Tb>
5303-
theEmitter->emitIns_R_R_R(INS_sve_orqv, EA_8BYTE, REG_V7, REG_P7, REG_V7, INS_OPTS_SCALABLE_D);
5304-
// ORQV <Vd>.<T>, <Pg>, <Zn>.<Tb>
5305-
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
5291+
// IF_SVE_AG_3A
5292+
theEmitter->emitIns_R_R_R(INS_sve_andqv, EA_8BYTE, REG_V4, REG_P4, REG_V4,
5293+
INS_OPTS_SCALABLE_B); // ANDQV <Vd>.<T>, <Pg>, <Zn>.<Tb>
5294+
theEmitter->emitIns_R_R_R(INS_sve_eorqv, EA_8BYTE, REG_V5, REG_P5, REG_V5,
5295+
INS_OPTS_SCALABLE_H); // EORQV <Vd>.<T>, <Pg>, <Zn>.<Tb>
5296+
theEmitter->emitIns_R_R_R(INS_sve_orqv, EA_8BYTE, REG_V6, REG_P6, REG_V6,
5297+
INS_OPTS_SCALABLE_S); // ORQV <Vd>.<T>, <Pg>, <Zn>.<Tb>
5298+
theEmitter->emitIns_R_R_R(INS_sve_orqv, EA_8BYTE, REG_V7, REG_P7, REG_V7,
5299+
INS_OPTS_SCALABLE_D); // ORQV <Vd>.<T>, <Pg>, <Zn>.<Tb>
53065300

53075301
// IF_SVE_AI_3A
53085302
theEmitter->emitIns_R_R_R(INS_sve_saddv, EA_SCALABLE, REG_V1, REG_P4, REG_V2,
@@ -5312,11 +5306,9 @@ void CodeGen::genArm64EmitterUnitTestsSve()
53125306
theEmitter->emitIns_R_R_R(INS_sve_uaddv, EA_SCALABLE, REG_V3, REG_P6, REG_V4,
53135307
INS_OPTS_SCALABLE_S); // UADDV <Dd>, <Pg>, <Zn>.<T>
53145308

5315-
// IF_SVE_AJ_3A
5316-
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
5317-
theEmitter->emitIns_R_R_R(INS_sve_addqv, EA_8BYTE, REG_V21, REG_P7, REG_V22, INS_OPTS_SCALABLE_B);
5318-
// ADDQV <Vd>.<T>, <Pg>, <Zn>.<Tb>
5319-
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
5309+
// IF_SVE_AJ_3A
5310+
theEmitter->emitIns_R_R_R(INS_sve_addqv, EA_8BYTE, REG_V21, REG_P7, REG_V22,
5311+
INS_OPTS_SCALABLE_B); // ADDQV <Vd>.<T>, <Pg>, <Zn>.<Tb>
53205312

53215313
// IF_SVE_AK_3A
53225314
theEmitter->emitIns_R_R_R(INS_sve_smaxv, EA_SCALABLE, REG_V15, REG_P7, REG_V4,
@@ -5328,17 +5320,15 @@ void CodeGen::genArm64EmitterUnitTestsSve()
53285320
theEmitter->emitIns_R_R_R(INS_sve_uminv, EA_SCALABLE, REG_V18, REG_P4, REG_V31,
53295321
INS_OPTS_SCALABLE_B); // UMINV <V><d>, <Pg>, <Zn>.<T>
53305322

5331-
// IF_SVE_AL_3A
5332-
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
5333-
theEmitter->emitIns_R_R_R(INS_sve_smaxqv, EA_8BYTE, REG_V0, REG_P5, REG_V25, INS_OPTS_SCALABLE_B);
5334-
// SMAXQV <Vd>.<T>, <Pg>, <Zn>.<Tb>
5335-
theEmitter->emitIns_R_R_R(INS_sve_sminqv, EA_8BYTE, REG_V1, REG_P4, REG_V24, INS_OPTS_SCALABLE_H);
5336-
// SMINQV <Vd>.<T>, <Pg>, <Zn>.<Tb>
5337-
theEmitter->emitIns_R_R_R(INS_sve_umaxqv, EA_8BYTE, REG_V2, REG_P3, REG_V23, INS_OPTS_SCALABLE_S);
5338-
// UMAXQV <Vd>.<T>, <Pg>, <Zn>.<Tb>
5339-
theEmitter->emitIns_R_R_R(INS_sve_uminqv, EA_8BYTE, REG_V3, REG_P2, REG_V22, INS_OPTS_SCALABLE_D);
5340-
// UMINQV <Vd>.<T>, <Pg>, <Zn>.<Tb>
5341-
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
5323+
// IF_SVE_AL_3A
5324+
theEmitter->emitIns_R_R_R(INS_sve_smaxqv, EA_8BYTE, REG_V0, REG_P5, REG_V25,
5325+
INS_OPTS_SCALABLE_B); // SMAXQV <Vd>.<T>, <Pg>, <Zn>.<Tb>
5326+
theEmitter->emitIns_R_R_R(INS_sve_sminqv, EA_8BYTE, REG_V1, REG_P4, REG_V24,
5327+
INS_OPTS_SCALABLE_H); // SMINQV <Vd>.<T>, <Pg>, <Zn>.<Tb>
5328+
theEmitter->emitIns_R_R_R(INS_sve_umaxqv, EA_8BYTE, REG_V2, REG_P3, REG_V23,
5329+
INS_OPTS_SCALABLE_S); // UMAXQV <Vd>.<T>, <Pg>, <Zn>.<Tb>
5330+
theEmitter->emitIns_R_R_R(INS_sve_uminqv, EA_8BYTE, REG_V3, REG_P2, REG_V22,
5331+
INS_OPTS_SCALABLE_D); // UMINQV <Vd>.<T>, <Pg>, <Zn>.<Tb>
53425332

53435333
// IF_SVE_AP_3A
53445334
theEmitter->emitIns_R_R_R(INS_sve_cls, EA_SCALABLE, REG_V31, REG_P0, REG_V0,
@@ -5509,7 +5499,8 @@ void CodeGen::genArm64EmitterUnitTestsSve()
55095499
INS_OPTS_SCALABLE_B); // PMUL <Zd>.B, <Zn>.B, <Zm>.B
55105500

55115501
// IF_SVE_BG_3A
5512-
theEmitter->emitIns_R_R_R(INS_sve_asr, EA_SCALABLE, REG_V9, REG_V31, REG_V2,
5502+
theEmitter->emitIns_R_R_R(INS_sve_asr, EA_SCALABLE, REG_V9, REG_V31, REG_V2, // UMINQV <Vd>.<T>, <Pg>, <Zn>.<Tb>
5503+
55135504
INS_OPTS_SCALABLE_B); // ASR <Zd>.<T>, <Zn>.<T>, <Zm>.D
55145505
theEmitter->emitIns_R_R_R(INS_sve_lsl, EA_SCALABLE, REG_V19, REG_V0, REG_V12,
55155506
INS_OPTS_SCALABLE_H); // LSL <Zd>.<T>, <Zn>.<T>, <Zm>.D
@@ -5859,7 +5850,6 @@ void CodeGen::genArm64EmitterUnitTestsSve()
58595850
theEmitter->emitIns_R_R_R(INS_sve_uaba, EA_SCALABLE, REG_V9, REG_V10, REG_V11,
58605851
INS_OPTS_SCALABLE_D); // UABA <Zda>.<T>, <Zn>.<T>, <Zm>.<T>
58615852

5862-
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
58635853
// IF_SVE_GC_3A
58645854
theEmitter->emitIns_R_R_R(INS_sve_addhnb, EA_SCALABLE, REG_V0, REG_V1, REG_V2,
58655855
INS_OPTS_SCALABLE_B); // ADDHNB <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
@@ -5877,7 +5867,6 @@ void CodeGen::genArm64EmitterUnitTestsSve()
58775867
INS_OPTS_SCALABLE_B); // SUBHNB <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
58785868
theEmitter->emitIns_R_R_R(INS_sve_subhnt, EA_SCALABLE, REG_V21, REG_V22, REG_V23,
58795869
INS_OPTS_SCALABLE_H); // SUBHNT <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
5880-
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
58815870

58825871
// IF_SVE_GF_3A
58835872
theEmitter->emitIns_R_R_R(INS_sve_histseg, EA_SCALABLE, REG_V0, REG_V1, REG_V2,
@@ -5895,13 +5884,11 @@ void CodeGen::genArm64EmitterUnitTestsSve()
58955884
theEmitter->emitIns_R_R_R(INS_sve_bfsub, EA_SCALABLE, REG_V6, REG_V7, REG_V8,
58965885
INS_OPTS_SCALABLE_H); // BFSUB <Zd>.H, <Zn>.H, <Zm>.H
58975886

5898-
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
58995887
// IF_SVE_AT_3B
59005888
theEmitter->emitIns_R_R_R(INS_sve_addpt, EA_SCALABLE, REG_V0, REG_V1, REG_V2,
59015889
INS_OPTS_SCALABLE_D); // ADDPT <Zd>.D, <Zn>.D, <Zm>.D
59025890
theEmitter->emitIns_R_R_R(INS_sve_subpt, EA_SCALABLE, REG_V3, REG_V4, REG_V5,
59035891
INS_OPTS_SCALABLE_D); // SUBPT <Zd>.D, <Zn>.D, <Zm>.D
5904-
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
59055892

59065893
// IF_SVE_AU_3A
59075894
theEmitter->emitIns_R_R_R(INS_sve_and, EA_SCALABLE, REG_V0, REG_V1, REG_V2, INS_OPTS_SCALABLE_D); // AND <Zd>.D,
@@ -6106,7 +6093,6 @@ void CodeGen::genArm64EmitterUnitTestsSve()
61066093
theEmitter->emitIns_R_PATTERN_I(INS_sve_uqincw, EA_SCALABLE, REG_V11, SVE_PATTERN_ALL, 16,
61076094
INS_OPTS_SCALABLE_S); // UQINCW <Zdn>.S{, <pattern>{, MUL #<imm>}}
61086095

6109-
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
61106096
// IF_SVE_BQ_2A
61116097
theEmitter->emitIns_R_R_I(INS_sve_ext, EA_SCALABLE, REG_V0, REG_V1, 0, INS_OPTS_SCALABLE_B,
61126098
INS_SCALABLE_OPTS_WITH_VECTOR_PAIR); // EXT <Zd>.B, {<Zn1>.B, <Zn2>.B }, #<imm>
@@ -6116,7 +6102,6 @@ void CodeGen::genArm64EmitterUnitTestsSve()
61166102
INS_SCALABLE_OPTS_WITH_VECTOR_PAIR); // EXT <Zd>.B, {<Zn1>.B, <Zn2>.B }, #<imm>
61176103
theEmitter->emitIns_R_R_I(INS_sve_ext, EA_SCALABLE, REG_V6, REG_FP_LAST, 255, INS_OPTS_SCALABLE_B,
61186104
INS_SCALABLE_OPTS_WITH_VECTOR_PAIR); // EXT <Zd>.B, {<Zn1>.B, <Zn2>.B }, #<imm>
6119-
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
61206105

61216106
// IF_SVE_BQ_2B
61226107
theEmitter->emitIns_R_R_I(INS_sve_ext, EA_SCALABLE, REG_V0, REG_V1, 0,
@@ -6298,13 +6283,11 @@ void CodeGen::genArm64EmitterUnitTestsSve()
62986283
theEmitter->emitIns_R_R(INS_sve_sqcvtun, EA_SCALABLE, REG_V6, REG_V8); // SQCVTUN <Zd>.H, {<Zn1>.S-<Zn2>.S }
62996284
theEmitter->emitIns_R_R(INS_sve_uqcvtn, EA_SCALABLE, REG_V14, REG_V16); // UQCVTN <Zd>.H, {<Zn1>.S-<Zn2>.S }
63006285

6301-
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
63026286
// IF_SVE_HG_2A
63036287
theEmitter->emitIns_R_R(INS_sve_bfcvtn, EA_SCALABLE, REG_V0, REG_V2); // BFCVTN <Zd>.B, {<Zn1>.H-<Zn2>.H }
63046288
theEmitter->emitIns_R_R(INS_sve_fcvtn, EA_SCALABLE, REG_V2, REG_V4); // FCVTN <Zd>.B, {<Zn1>.H-<Zn2>.H }
63056289
theEmitter->emitIns_R_R(INS_sve_fcvtnb, EA_SCALABLE, REG_V6, REG_V8); // FCVTNB <Zd>.B, {<Zn1>.S-<Zn2>.S }
63066290
theEmitter->emitIns_R_R(INS_sve_fcvtnt, EA_SCALABLE, REG_V14, REG_V16); // FCVTNT <Zd>.B, {<Zn1>.S-<Zn2>.S }
6307-
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
63086291

63096292
// IF_SVE_GA_2A
63106293
theEmitter->emitIns_R_R_I(INS_sve_sqrshrn, EA_SCALABLE, REG_V0, REG_V0, 5,
@@ -6539,7 +6522,6 @@ void CodeGen::genArm64EmitterUnitTestsSve()
65396522
theEmitter->emitIns_R(INS_sve_aesimc, EA_SCALABLE, REG_V0); // AESIMC <Zdn>.B, <Zdn>.B
65406523
theEmitter->emitIns_R(INS_sve_aesmc, EA_SCALABLE, REG_V5); // AESMC <Zdn>.B, <Zdn>.B
65416524

6542-
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
65436525
// IF_SVE_GN_3A
65446526
theEmitter->emitIns_R_R_R(INS_sve_fmlalb, EA_SCALABLE, REG_V0, REG_V1, REG_V2,
65456527
INS_OPTS_SCALABLE_B); // FMLALB <Zda>.H, <Zn>.B, <Zm>.B
@@ -6567,7 +6549,6 @@ void CodeGen::genArm64EmitterUnitTestsSve()
65676549
INS_OPTS_SCALABLE_H); // FMINNMQV <Vd>.<T>, <Pg>, <Zn>.<Tb>
65686550
theEmitter->emitIns_R_R_R(INS_sve_fminqv, EA_8BYTE, REG_V20, REG_P5, REG_V8,
65696551
INS_OPTS_SCALABLE_D); // FMINQV <Vd>.<T>, <Pg>, <Zn>.<Tb>
6570-
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
65716552

65726553
// IF_SVE_GU_3A
65736554
theEmitter->emitIns_R_R_R_I(INS_sve_fmla, EA_SCALABLE, REG_V0, REG_V2, REG_V1, 0,
@@ -6649,7 +6630,6 @@ void CodeGen::genArm64EmitterUnitTestsSve()
66496630
theEmitter->emitIns_R_R_R_I(INS_sve_bfdot, EA_SCALABLE, REG_V12, REG_V14, REG_V7, 3,
66506631
INS_OPTS_SCALABLE_H); // BFDOT <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
66516632

6652-
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
66536633
// IF_SVE_GY_3A
66546634
theEmitter->emitIns_R_R_R_I(INS_sve_fdot, EA_SCALABLE, REG_V0, REG_V2, REG_V1,
66556635
1); // FDOT <Zda>.H, <Zn>.B, <Zm>.B[<imm>]
@@ -6669,7 +6649,6 @@ void CodeGen::genArm64EmitterUnitTestsSve()
66696649
INS_OPTS_SCALABLE_B); // FDOT <Zda>.S, <Zn>.B, <Zm>.B[<imm>]
66706650
theEmitter->emitIns_R_R_R_I(INS_sve_fdot, EA_SCALABLE, REG_V12, REG_V14, REG_V7, 3,
66716651
INS_OPTS_SCALABLE_B); // FDOT <Zda>.S, <Zn>.B, <Zm>.B[<imm>]
6672-
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
66736652

66746653
// IF_SVE_GZ_3A
66756654
theEmitter->emitIns_R_R_R_I(INS_sve_bfmlalb, EA_SCALABLE, REG_V0, REG_V1, REG_V0, 0,
@@ -6695,14 +6674,12 @@ void CodeGen::genArm64EmitterUnitTestsSve()
66956674
theEmitter->emitIns_R_R_R(INS_sve_fdot, EA_SCALABLE, REG_V3, REG_V4, REG_V5,
66966675
INS_OPTS_SCALABLE_H); // FDOT <Zda>.S, <Zn>.H, <Zm>.H
66976676

6698-
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
66996677
// IF_SVE_HA_3A_E
67006678
theEmitter->emitIns_R_R_R(INS_sve_fdot, EA_SCALABLE, REG_V6, REG_V7, REG_V8,
67016679
INS_OPTS_SCALABLE_B); // FDOT <Zda>.H, <Zn>.B, <Zm>.B
67026680

67036681
// IF_SVE_HA_3A_F
67046682
theEmitter->emitIns_R_R_R(INS_sve_fdot, EA_SCALABLE, REG_V9, REG_V10, REG_V11); // FDOT <Zda>.S, <Zn>.B, <Zm>.B
6705-
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
67066683

67076684
// IF_SVE_HB_3A
67086685
theEmitter->emitIns_R_R_R(INS_sve_bfmlalb, EA_SCALABLE, REG_V0, REG_V1, REG_V2,
@@ -6726,11 +6703,9 @@ void CodeGen::genArm64EmitterUnitTestsSve()
67266703
theEmitter->emitIns_R_R_R(INS_sve_bfmmla, EA_SCALABLE, REG_V0, REG_V1, REG_V2,
67276704
INS_OPTS_SCALABLE_H); // BFMMLA <Zda>.S, <Zn>.H, <Zm>.H
67286705

6729-
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
67306706
// IF_SVE_HD_3A_A
67316707
theEmitter->emitIns_R_R_R(INS_sve_fmmla, EA_SCALABLE, REG_V3, REG_V4, REG_V5,
67326708
INS_OPTS_SCALABLE_D); // FMMLA <Zda>.D, <Zn>.D, <Zm>.D
6733-
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
67346709

67356710
// IF_SVE_HE_3A
67366711
theEmitter->emitIns_R_R_R(INS_sve_faddv, EA_SCALABLE, REG_V21, REG_P7, REG_V7,
@@ -6818,7 +6793,6 @@ void CodeGen::genArm64EmitterUnitTestsSve()
68186793
theEmitter->emitIns_R_R_R(INS_sve_whilewr, EA_8BYTE, REG_P7, REG_R14, REG_R15,
68196794
INS_OPTS_SCALABLE_D); // WHILEWR <Pd>.<T>, <Xn>, <Xm>
68206795

6821-
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
68226796
// IF_SVE_DV_4A
68236797
theEmitter->emitIns_R_R_R_R_I(INS_sve_psel, EA_SCALABLE, REG_P0, REG_P1, REG_P2, REG_R12, 15,
68246798
INS_OPTS_SCALABLE_B); // PSEL <Pd>, <Pn>, <Pm>.<T>[<Wv>, <imm>]
@@ -6828,7 +6802,6 @@ void CodeGen::genArm64EmitterUnitTestsSve()
68286802
INS_OPTS_SCALABLE_S); // PSEL <Pd>, <Pn>, <Pm>.<T>[<Wv>, <imm>]
68296803
theEmitter->emitIns_R_R_R_R_I(INS_sve_psel, EA_SCALABLE, REG_P9, REG_P10, REG_P11, REG_R15, 1,
68306804
INS_OPTS_SCALABLE_D); // PSEL <Pd>, <Pn>, <Pm>.<T>[<Wv>, <imm>]
6831-
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
68326805

68336806
// IF_SVE_DW_2A
68346807
theEmitter->emitIns_R_R_I(INS_sve_pext, EA_SCALABLE, REG_P0, REG_P8, 0,
@@ -6995,13 +6968,11 @@ void CodeGen::genArm64EmitterUnitTestsSve()
69956968
theEmitter->emitIns_R_R_R_I(INS_sve_sqrdcmlah, EA_SCALABLE, REG_V21, REG_V22, REG_V23, 270,
69966969
INS_OPTS_SCALABLE_D); // SQRDCMLAH <Zda>.<T>, <Zn>.<T>, <Zm>.<T>, <const>
69976970

6998-
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
69996971
// IF_SVE_EW_3A
70006972
theEmitter->emitIns_R_R_R(INS_sve_mlapt, EA_SCALABLE, REG_V0, REG_V1, REG_V2); // MLAPT <Zda>.D, <Zn>.D, <Zm>.D
70016973

70026974
// IF_SVE_EW_3B
70036975
theEmitter->emitIns_R_R_R(INS_sve_madpt, EA_SCALABLE, REG_V3, REG_V4, REG_V5); // MADPT <Zdn>.D, <Zm>.D, <Za>.D
7004-
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
70056976

70066977
// IF_SVE_EY_3A
70076978
theEmitter->emitIns_R_R_R_I(INS_sve_sdot, EA_SCALABLE, REG_V9, REG_V10, REG_V4, 0,
@@ -8541,7 +8512,6 @@ void CodeGen::genArm64EmitterUnitTestsSve()
85418512
theEmitter->emitIns_R_R_I(INS_sve_str, EA_SCALABLE, REG_V2, REG_R3, -256, INS_OPTS_NONE);
85428513
theEmitter->emitIns_R_R_I(INS_sve_str, EA_SCALABLE, REG_V2, REG_R3, 255, INS_OPTS_NONE);
85438514

8544-
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
85458515
// IF_SVE_GG_3A
85468516
// LUTI2 <Zd>.B, {<Zn>.B }, <Zm>[<index>]
85478517
// luti2 z0.b, {z0.b}, z0[0] // 01000101-00100000-10110000-00000000
@@ -8611,7 +8581,6 @@ void CodeGen::genArm64EmitterUnitTestsSve()
86118581
// CHECK-INST: luti4 z31.b, { z31.b }, z31[1]
86128582
// CHECK-ENCODING: [0xff,0xa7,0xff,0x45]
86138583
theEmitter->emitIns_R_R_R_I(INS_sve_luti4, EA_SCALABLE, REG_V31, REG_V31, REG_V31, 1, INS_OPTS_SCALABLE_B);
8614-
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
86158584

86168585
// IF_SVE_HY_3A
86178586
theEmitter->emitIns_PRFOP_R_R_R(INS_sve_prfb, EA_SCALABLE, SVE_PRFOP_PLDL1KEEP, REG_P1, REG_R2, REG_V3,
@@ -8907,7 +8876,6 @@ void CodeGen::genArm64EmitterUnitTestsSve()
89078876
// FEXPA <Zd>.<T>, <Zn>.<T>
89088877
theEmitter->emitIns_R_R(INS_sve_fexpa, EA_SCALABLE, REG_V1, REG_V0, INS_OPTS_SCALABLE_D);
89098878

8910-
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
89118879
// IF_SVE_HH_2A
89128880
// BF1CVT <Zd>.H, <Zn>.B
89138881
theEmitter->emitIns_R_R(INS_sve_bf1cvt, EA_SCALABLE, REG_V2, REG_V3, INS_OPTS_SCALABLE_H);
@@ -8925,7 +8893,6 @@ void CodeGen::genArm64EmitterUnitTestsSve()
89258893
theEmitter->emitIns_R_R(INS_sve_f2cvt, EA_SCALABLE, REG_V3, REG_V4, INS_OPTS_SCALABLE_H);
89268894
// F2CVTLT <Zd>.H, <Zn>.B
89278895
theEmitter->emitIns_R_R(INS_sve_f2cvtlt, EA_SCALABLE, REG_V1, REG_V2, INS_OPTS_SCALABLE_H);
8928-
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
89298896

89308897
// IF_SVE_BI_2A
89318898
// MOVPRFX <Zd>, <Zn>

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