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Commit 5975887

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minor cleanup
1 parent 5c66924 commit 5975887

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+5
-46
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+5
-46
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src/coreclr/jit/hwintrinsiccodegenarm64.cpp

Lines changed: 5 additions & 46 deletions
Original file line numberDiff line numberDiff line change
@@ -808,17 +808,10 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
808808
else if (HWIntrinsicInfo::IsScalable(intrin.id))
809809
{
810810
assert(!node->IsEmbMaskOp());
811-
if (HWIntrinsicInfo::IsExplicitMaskedOperation(intrin.id))
812-
{
813-
GetEmitter()->emitIns_R_R_R(ins, emitSize, targetReg, op1Reg, op2Reg, opt);
814-
}
815-
else
816-
{
817-
// This generates an unpredicated version
818-
// Implicitly predicated should be taken care above `intrin.op2->IsEmbMaskOp()`
819-
GetEmitter()->emitIns_R_R_R(ins, emitSize, targetReg, op1Reg, op2Reg, opt,
820-
INS_SCALABLE_OPTS_UNPREDICATED);
821-
}
811+
// This generates an unpredicated version
812+
// Predicated should be taken care above `intrin.op2->IsEmbMaskOp()`
813+
GetEmitter()->emitIns_R_R_R(ins, emitSize, targetReg, op1Reg, op2Reg, opt,
814+
INS_SCALABLE_OPTS_UNPREDICATED);
822815
}
823816
else if (isRMW)
824817
{
@@ -1496,7 +1489,7 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
14961489
{
14971490
assert(intrin.op3->IsIntegralConst());
14981491
GetEmitter()->emitIns_PRFOP_R_R_I(ins, emitSize, (insSvePrfop)intrin.op3->AsIntConCommon()->IconValue(),
1499-
op1Reg, op2Reg, 0, INS_OPTS_NONE);
1492+
op1Reg, op2Reg, 0);
15001493
break;
15011494
}
15021495

@@ -1856,18 +1849,11 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
18561849
break;
18571850
}
18581851

1859-
case NI_Sve_ReverseElement:
1860-
// Use non-predicated version explicitly
1861-
GetEmitter()->emitIns_R_R(ins, emitSize, targetReg, op1Reg, opt, INS_SCALABLE_OPTS_UNPREDICATED);
1862-
break;
1863-
18641852
case NI_Sve_StoreNarrowing:
18651853
opt = emitter::optGetSveInsOpt(emitTypeSize(intrin.baseType));
18661854
GetEmitter()->emitIns_R_R_R_I(ins, emitSize, op3Reg, op1Reg, op2Reg, 0, opt);
18671855
break;
18681856

1869-
case NI_Sve_TransposeEven:
1870-
case NI_Sve_TransposeOdd:
18711857
case NI_Sve_UnzipEven:
18721858
case NI_Sve_UnzipOdd:
18731859
case NI_Sve_ZipHigh:
@@ -1951,33 +1937,6 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
19511937
break;
19521938
}
19531939

1954-
case NI_Sve_SaturatingDecrementByActiveElementCount:
1955-
case NI_Sve_SaturatingIncrementByActiveElementCount:
1956-
{
1957-
// RMW semantics
1958-
if (targetReg != op1Reg)
1959-
{
1960-
assert(targetReg != op2Reg);
1961-
GetEmitter()->emitIns_Mov(INS_mov, emitTypeSize(node), targetReg, op1Reg, /* canSkip */ true);
1962-
}
1963-
1964-
// Switch instruction if arg1 is unsigned.
1965-
if (varTypeIsUnsigned(node->GetAuxiliaryType()))
1966-
{
1967-
ins =
1968-
(intrin.id == NI_Sve_SaturatingDecrementByActiveElementCount) ? INS_sve_uqdecp : INS_sve_uqincp;
1969-
}
1970-
1971-
// If this is the scalar variant, get the correct size.
1972-
if (!varTypeIsSIMD(node->gtType))
1973-
{
1974-
emitSize = emitActualTypeSize(intrin.op1);
1975-
}
1976-
1977-
GetEmitter()->emitIns_R_R(ins, emitSize, targetReg, op2Reg, opt);
1978-
break;
1979-
}
1980-
19811940
default:
19821941
unreached();
19831942
}

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