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Add a number of additional APIs to the various SIMD accelerated vector types (#111179)
* Add a number of additional APIs to the various SIMD accelerated vector types * Add tests for the new vector APIs * Fix the boolean logic for the vectorized IsEvenInteger * Try to fix the Mono build * Fixing some RyuJIT handling * Add some additional Mono handling and document what's hindering other support * Update src/libraries/System.Private.CoreLib/src/System/Half.cs * Fix mono interp * Ensure the handling of the Vector2/3 All/Any/None and Count/IndexOf/LastIndexOf methods is correct * Try and fix the mono build * Don't accelerate the new methods for Vector2/3 on Mono * Fix mono build warning * Ensure the right class name is resolved for Vector4
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src/coreclr/jit/compiler.h

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@@ -3377,6 +3377,26 @@ class Compiler
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CorInfoType simdBaseJitType,
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unsigned simdSize);
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GenTree* gtNewSimdIsEvenIntegerNode(var_types type,
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GenTree* op1,
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CorInfoType simdBaseJitType,
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unsigned simdSize);
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GenTree* gtNewSimdIsFiniteNode(var_types type,
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GenTree* op1,
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CorInfoType simdBaseJitType,
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unsigned simdSize);
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GenTree* gtNewSimdIsInfinityNode(var_types type,
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GenTree* op1,
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CorInfoType simdBaseJitType,
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unsigned simdSize);
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GenTree* gtNewSimdIsIntegerNode(var_types type,
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GenTree* op1,
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CorInfoType simdBaseJitType,
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unsigned simdSize);
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GenTree* gtNewSimdIsNaNNode(var_types type,
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GenTree* op1,
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CorInfoType simdBaseJitType,
@@ -3387,6 +3407,21 @@ class Compiler
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CorInfoType simdBaseJitType,
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unsigned simdSize);
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GenTree* gtNewSimdIsNegativeInfinityNode(var_types type,
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GenTree* op1,
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CorInfoType simdBaseJitType,
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unsigned simdSize);
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GenTree* gtNewSimdIsNormalNode(var_types type,
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GenTree* op1,
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CorInfoType simdBaseJitType,
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unsigned simdSize);
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GenTree* gtNewSimdIsOddIntegerNode(var_types type,
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GenTree* op1,
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CorInfoType simdBaseJitType,
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unsigned simdSize);
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GenTree* gtNewSimdIsPositiveNode(var_types type,
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GenTree* op1,
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CorInfoType simdBaseJitType,
@@ -3397,6 +3432,11 @@ class Compiler
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CorInfoType simdBaseJitType,
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unsigned simdSize);
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GenTree* gtNewSimdIsSubnormalNode(var_types type,
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GenTree* op1,
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CorInfoType simdBaseJitType,
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unsigned simdSize);
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GenTree* gtNewSimdIsZeroNode(var_types type,
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GenTree* op1,
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CorInfoType simdBaseJitType,

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