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jacob-crawleyjacob-crawley
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Correcting the naming of AddWidening intrinsics
1 parent b553655 commit 05751ce

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7 files changed

+204
-188
lines changed

7 files changed

+204
-188
lines changed

‎src/coreclr/jit/hwintrinsicarm64.cpp‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3405,6 +3405,8 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
34053405
break;
34063406
}
34073407

3408+
case NI_Sve2_AddWideningEven:
3409+
case NI_Sve2_AddWideningOdd:
34083410
case NI_Sve2_SubtractWideningEven:
34093411
case NI_Sve2_SubtractWideningOdd:
34103412
{

‎src/coreclr/jit/hwintrinsiccodegenarm64.cpp‎

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2719,6 +2719,31 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
27192719
GetEmitter()->emitInsSve_R_R_R(ins, emitSize, targetReg, op1Reg, op2Reg, opt);
27202720
break;
27212721

2722+
case NI_Sve2_AddWideningEven:
2723+
{
2724+
var_types returnType = node->AsHWIntrinsic()->GetSimdBaseType();
2725+
var_types op1Type = node->AsHWIntrinsic()->GetAuxiliaryType();
2726+
if (returnType != op1Type)
2727+
{
2728+
ins = varTypeIsUnsigned(intrin.baseType) ? INS_sve_uaddlb : INS_sve_saddlb;
2729+
}
2730+
2731+
GetEmitter()->emitInsSve_R_R_R(ins, emitSize, targetReg, op1Reg, op2Reg, opt);
2732+
break;
2733+
}
2734+
2735+
case NI_Sve2_AddWideningOdd:
2736+
{
2737+
var_types returnType = node->AsHWIntrinsic()->GetSimdBaseType();
2738+
var_types op1Type = node->AsHWIntrinsic()->GetAuxiliaryType();
2739+
if (returnType != op1Type)
2740+
{
2741+
ins = varTypeIsUnsigned(intrin.baseType) ? INS_sve_uaddlt : INS_sve_saddlt;
2742+
}
2743+
GetEmitter()->emitInsSve_R_R_R(ins, emitSize, targetReg, op1Reg, op2Reg, opt);
2744+
break;
2745+
}
2746+
27222747
case NI_Sve2_BitwiseClearXor:
27232748
case NI_Sve2_Xor:
27242749
if (targetReg != op1Reg)

‎src/coreclr/jit/hwintrinsiclistarm64sve.h‎

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -312,7 +312,6 @@ HARDWARE_INTRINSIC(Sve, ZipLow,
312312
// ISA Function name SIMD size NumArg Instructions Category Flags
313313
// {TYP_BYTE, TYP_UBYTE, TYP_SHORT, TYP_USHORT, TYP_INT, TYP_UINT, TYP_LONG, TYP_ULONG, TYP_FLOAT, TYP_DOUBLE}
314314
// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
315-
// SVE2 Intrinsics
316315
#define FIRST_NI_Sve2 NI_Sve2_AbsoluteDifferenceAdd
317316
HARDWARE_INTRINSIC(Sve2, AbsoluteDifferenceAdd, -1, 3, {INS_sve_saba, INS_sve_uaba, INS_sve_saba, INS_sve_uaba, INS_sve_saba, INS_sve_uaba, INS_sve_saba, INS_sve_uaba, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_HasRMWSemantics)
318317
HARDWARE_INTRINSIC(Sve2, AbsoluteDifferenceWideningEven, -1, 2, {INS_invalid, INS_invalid, INS_sve_sabdlb, INS_sve_uabdlb, INS_sve_sabdlb, INS_sve_uabdlb, INS_sve_sabdlb, INS_sve_uabdlb, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable)
@@ -328,11 +327,9 @@ HARDWARE_INTRINSIC(Sve2, AddPairwiseWidening,
328327
HARDWARE_INTRINSIC(Sve2, AddSaturate, -1, -1, {INS_sve_sqadd, INS_sve_uqadd, INS_sve_sqadd, INS_sve_uqadd, INS_sve_sqadd, INS_sve_uqadd, INS_sve_sqadd, INS_sve_uqadd, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_OptionalEmbeddedMaskedOperation|HW_Flag_HasRMWSemantics|HW_Flag_LowMaskedOperation)
329328
HARDWARE_INTRINSIC(Sve2, AddSaturateWithSignedAddend, -1, -1, {INS_invalid, INS_sve_usqadd, INS_invalid, INS_sve_usqadd, INS_invalid, INS_sve_usqadd, INS_invalid, INS_sve_usqadd, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_HasRMWSemantics|HW_Flag_LowMaskedOperation)
330329
HARDWARE_INTRINSIC(Sve2, AddSaturateWithUnsignedAddend, -1, -1, {INS_sve_suqadd, INS_invalid, INS_sve_suqadd, INS_invalid, INS_sve_suqadd, INS_invalid, INS_sve_suqadd, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_HasRMWSemantics|HW_Flag_LowMaskedOperation)
331-
HARDWARE_INTRINSIC(Sve2, AddWideLower, -1, 2, {INS_invalid, INS_invalid, INS_sve_saddwb, INS_sve_uaddwb, INS_sve_saddwb, INS_sve_uaddwb, INS_sve_saddwb, INS_sve_uaddwb, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_BaseTypeFromFirstArg)
332-
HARDWARE_INTRINSIC(Sve2, AddWideUpper, -1, 2, {INS_invalid, INS_invalid, INS_sve_saddwt, INS_sve_uaddwt, INS_sve_saddwt, INS_sve_uaddwt, INS_sve_saddwt, INS_sve_uaddwt, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_BaseTypeFromFirstArg)
333-
HARDWARE_INTRINSIC(Sve2, AddWideningLower, -1, 2, {INS_invalid, INS_invalid, INS_sve_saddlb, INS_sve_uaddlb, INS_sve_saddlb, INS_sve_uaddlb, INS_sve_saddlb, INS_sve_uaddlb, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable)
334-
HARDWARE_INTRINSIC(Sve2, AddWideningLowerUpper, -1, 2, {INS_invalid, INS_invalid, INS_sve_saddlbt, INS_invalid, INS_sve_saddlbt, INS_invalid, INS_sve_saddlbt, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable)
335-
HARDWARE_INTRINSIC(Sve2, AddWideningUpper, -1, 2, {INS_invalid, INS_invalid, INS_sve_saddlt, INS_sve_uaddlt, INS_sve_saddlt, INS_sve_uaddlt, INS_sve_saddlt, INS_sve_uaddlt, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable)
330+
HARDWARE_INTRINSIC(Sve2, AddWideningEven, -1, 2, {INS_invalid, INS_invalid, INS_sve_saddwb, INS_sve_uaddwb, INS_sve_saddwb, INS_sve_uaddwb, INS_sve_saddwb, INS_sve_uaddwb, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialImport|HW_Flag_SpecialCodeGen)
331+
HARDWARE_INTRINSIC(Sve2, AddWideningEvenOdd, -1, 2, {INS_invalid, INS_invalid, INS_sve_saddlbt, INS_invalid, INS_sve_saddlbt, INS_invalid, INS_sve_saddlbt, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable)
332+
HARDWARE_INTRINSIC(Sve2, AddWideningOdd, -1, 2, {INS_invalid, INS_invalid, INS_sve_saddwt, INS_sve_uaddwt, INS_sve_saddwt, INS_sve_uaddwt, INS_sve_saddwt, INS_sve_uaddwt, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialImport|HW_Flag_SpecialCodeGen)
336333
HARDWARE_INTRINSIC(Sve2, BitwiseClearXor, -1, 3, {INS_sve_bcax, INS_sve_bcax, INS_sve_bcax, INS_sve_bcax, INS_sve_bcax, INS_sve_bcax, INS_sve_bcax, INS_sve_bcax, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_HasRMWSemantics)
337334
HARDWARE_INTRINSIC(Sve2, BitwiseSelect, -1, 3, {INS_sve_bsl, INS_sve_bsl, INS_sve_bsl, INS_sve_bsl, INS_sve_bsl, INS_sve_bsl, INS_sve_bsl, INS_sve_bsl, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_HasRMWSemantics)
338335
HARDWARE_INTRINSIC(Sve2, BitwiseSelectLeftInverted, -1, 3, {INS_sve_bsl1n, INS_sve_bsl1n, INS_sve_bsl1n, INS_sve_bsl1n, INS_sve_bsl1n, INS_sve_bsl1n, INS_sve_bsl1n, INS_sve_bsl1n, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_HasRMWSemantics)

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