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SystemVerilog: chandle data type
This adds 1800 2017 6.14 chandle.
1 parent 6c6f411 commit 1fe25b6

14 files changed

+167
-4
lines changed

‎regression/verilog/data-types/chandle1.desc

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,8 @@
1+
CORE
2+
chandle1.sv
3+
--bound 0
4+
^\[main\.p0\] always main\.some_handle == null: PROVED up to bound 0$
5+
^\[main\.p1\] always 56'h6368616E646C65 == 56'h6368616E646C65: PROVED up to bound 0$
6+
^EXIT=0$
7+
^SIGNAL=0$
8+
--

‎regression/verilog/data-types/chandle1.sv

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,9 @@
1+
module main;
2+
3+
// IEEE 1800-2017 6.14
4+
chandle some_handle = null;
5+
6+
p0: assert final (some_handle == null);
7+
p1: assert final ($typename(some_handle) == "chandle");
8+
9+
endmodule

‎src/hw_cbmc_irep_ids.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -103,7 +103,8 @@ IREP_ID_ONE(verilog_value_range)
103103
IREP_ID_ONE(verilog_void)
104104
IREP_ID_ONE(verilog_streaming_concatenation_left_to_right)
105105
IREP_ID_ONE(verilog_streaming_concatenation_right_to_left)
106-
IREP_ID_ONE(chandle)
106+
IREP_ID_ONE(verilog_chandle)
107+
IREP_ID_ONE(verilog_null)
107108
IREP_ID_ONE(event)
108109
IREP_ID_ONE(reg)
109110
IREP_ID_ONE(macromodule)

‎src/verilog/Makefile

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,7 @@ SRC = aval_bval_encoding.cpp \
2626
verilog_typecheck_base.cpp \
2727
verilog_typecheck_expr.cpp \
2828
verilog_typecheck_sva.cpp \
29+
verilog_types.cpp \
2930
verilog_y.tab.cpp \
3031
vtype.cpp
3132

‎src/verilog/expr2verilog.cpp

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1208,6 +1208,15 @@ expr2verilogt::resultt expr2verilogt::convert_constant(
12081208
ieee_float.from_expr(tmp);
12091209
return {precedence, ieee_float.to_ansi_c_string()};
12101210
}
1211+
else if(type.id() == ID_verilog_chandle)
1212+
{
1213+
if(src.get_value() == ID_NULL)
1214+
{
1215+
dest = "null";
1216+
}
1217+
else
1218+
return convert_norep(src, precedence);
1219+
}
12111220
else
12121221
return convert_norep(src, precedence);
12131222

@@ -1978,6 +1987,8 @@ std::string expr2verilogt::convert(const typet &type)
19781987

19791988
return dest;
19801989
}
1990+
else if(type.id() == ID_verilog_chandle)
1991+
return "chandle";
19811992
else if(type.id() == ID_verilog_genvar)
19821993
return "genvar";
19831994
else if(type.id()==ID_integer)
@@ -1988,6 +1999,8 @@ std::string expr2verilogt::convert(const typet &type)
19881999
return "real";
19892000
else if(type.id()==ID_verilog_realtime)
19902001
return "realtime";
2002+
else if(type.id() == ID_verilog_null)
2003+
return "null";
19912004
else if(type.id() == ID_verilog_enum)
19922005
{
19932006
return "enum";

‎src/verilog/parser.y

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1473,7 +1473,7 @@ data_type:
14731473
| TOK_STRING
14741474
{ init($$, ID_string); }
14751475
| TOK_CHANDLE
1476-
{ init($$, ID_chandle); }
1476+
{ init($$, ID_verilog_chandle); }
14771477
| TOK_VIRTUAL interface_opt interface_identifier
14781478
{ init($$, "virtual_interface"); }
14791479
| /*scope_opt*/ type_identifier packed_dimension_brace
@@ -4018,7 +4018,7 @@ primary: primary_literal
40184018
| cast
40194019
| assignment_pattern_expression
40204020
| streaming_concatenation
4021-
| TOK_NULL { init($$, ID_NULL); }
4021+
| TOK_NULL { init($$, ID_verilog_null); }
40224022
| TOK_THIS { init($$, ID_this); }
40234023
;
40244024

‎src/verilog/verilog_elaborate_type.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -337,6 +337,10 @@ typet verilog_typecheck_exprt::elaborate_type(const typet &src)
337337
{
338338
return src;
339339
}
340+
else if(src.id() == ID_verilog_chandle)
341+
{
342+
return src;
343+
}
340344
else
341345
{
342346
throw errort().with_location(source_location)

‎src/verilog/verilog_lowering.cpp

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,7 @@ Author: Daniel Kroening, [email protected]
1717
#include "aval_bval_encoding.h"
1818
#include "verilog_bits.h"
1919
#include "verilog_expr.h"
20+
#include "verilog_types.h"
2021

2122
/// If applicable, lower the three Verilog real types to floatbv.
2223
typet lower_verilog_real_types(typet type)
@@ -183,9 +184,26 @@ exprt verilog_lowering(exprt expr)
183184
// no need to change value
184185
expr.type() = lower_verilog_real_types(expr.type());
185186
}
187+
else if(expr.type().id() == ID_verilog_chandle)
188+
{
189+
// this is 'null'
190+
return to_verilog_chandle_type(expr.type()).null_expr();
191+
}
186192

187193
return expr;
188194
}
195+
else if(expr.id() == ID_symbol)
196+
{
197+
auto &symbol_expr = to_symbol_expr(expr);
198+
if(expr.type().id() == ID_verilog_chandle)
199+
{
200+
auto &chandle_type = to_verilog_chandle_type(expr.type());
201+
return symbol_exprt{
202+
symbol_expr.get_identifier(), chandle_type.encoding()};
203+
}
204+
else
205+
return expr;
206+
}
189207
else if(expr.id() == ID_concatenation)
190208
{
191209
if(
@@ -421,6 +439,8 @@ typet verilog_lowering(typet type)
421439
{
422440
if(type.id() == ID_verilog_signedbv || type.id() == ID_verilog_unsignedbv)
423441
return lower_to_aval_bval(type);
442+
else if(type.id() == ID_verilog_chandle)
443+
return to_verilog_chandle_type(type).encoding();
424444
else
425445
return type;
426446
}

‎src/verilog/verilog_synthesis.cpp

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3346,7 +3346,14 @@ void verilog_synthesist::synth_assignments(
33463346
if(!symbol.is_state_var)
33473347
post_process_wire(symbol.name, new_value);
33483348

3349-
equal_exprt equality_expr{symbol_expr(symbol, curr_or_next), new_value};
3349+
auto lhs = symbol_expr(symbol, curr_or_next);
3350+
3351+
if(lhs.type() != new_value.type())
3352+
throw errort() << lhs.pretty() << "\nVS\n" << new_value.pretty();
3353+
DATA_INVARIANT(
3354+
lhs.type() == new_value.type(), "synth_assignments type consistency");
3355+
3356+
equal_exprt equality_expr{std::move(lhs), new_value};
33503357

33513358
constraints.add_to_operands(std::move(equality_expr));
33523359
}

‎src/verilog/verilog_typecheck_expr.cpp

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -735,6 +735,10 @@ exprt verilog_typecheck_exprt::typename_string(const exprt &expr)
735735
{
736736
s = "shortreal";
737737
}
738+
else if(type.id() == ID_verilog_chandle)
739+
{
740+
s = "chandle";
741+
}
738742
else
739743
s = "?";
740744

@@ -1003,6 +1007,11 @@ exprt verilog_typecheck_exprt::convert_nullary_expr(nullary_exprt expr)
10031007
throw errort().with_location(expr.source_location())
10041008
<< "'this' outside of method";
10051009
}
1010+
else if(expr.id() == ID_verilog_null)
1011+
{
1012+
return constant_exprt{ID_NULL, typet{ID_verilog_null}}.with_source_location(
1013+
expr.source_location());
1014+
}
10061015
else
10071016
{
10081017
throw errort().with_location(expr.source_location())
@@ -1932,6 +1941,17 @@ void verilog_typecheck_exprt::implicit_typecast(
19321941
return;
19331942
}
19341943
}
1944+
else if(src_type.id() == ID_verilog_null)
1945+
{
1946+
if(dest_type.id() == ID_verilog_chandle)
1947+
{
1948+
if(expr.id() == ID_constant)
1949+
{
1950+
expr.type() = dest_type;
1951+
return;
1952+
}
1953+
}
1954+
}
19351955

19361956
throw errort().with_location(expr.source_location())
19371957
<< "failed to convert `" << to_string(src_type) << "' to `"
@@ -2184,6 +2204,12 @@ typet verilog_typecheck_exprt::max_type(
21842204
vtypet vt0=vtypet(t0);
21852205
vtypet vt1=vtypet(t1);
21862206

2207+
if(vt0.is_null() || vt1.is_chandle())
2208+
return t1;
2209+
2210+
if(vt0.is_chandle() || vt1.is_null())
2211+
return t0;
2212+
21872213
if(vt0.is_other() || vt1.is_other())
21882214
return static_cast<const typet &>(get_nil_irep());
21892215

‎src/verilog/verilog_types.cpp

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,16 @@
1+
/*******************************************************************\
2+
3+
Module: Verilog Types
4+
5+
Author: Daniel Kroening, [email protected]
6+
7+
\*******************************************************************/
8+
9+
#include "verilog_types.h"
10+
11+
#include <util/std_expr.h>
12+
13+
constant_exprt verilog_chandle_typet::null_expr() const
14+
{
15+
return encoding().all_zeros_expr();
16+
}

‎src/verilog/verilog_types.h

Lines changed: 37 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -544,4 +544,41 @@ inline verilog_union_typet &to_verilog_union_type(typet &type)
544544
return static_cast<verilog_union_typet &>(type);
545545
}
546546

547+
/// a pointer type
548+
class verilog_chandle_typet : public typet
549+
{
550+
public:
551+
inline verilog_chandle_typet() : typet(ID_verilog_chandle)
552+
{
553+
}
554+
555+
bv_typet encoding() const
556+
{
557+
return bv_typet{32};
558+
}
559+
560+
constant_exprt null_expr() const;
561+
};
562+
563+
/// \brief Cast a typet to a \ref verilog_chandle_typet
564+
///
565+
/// This is an unchecked conversion. \a type must be known to be \ref
566+
/// verilog_chandle_typet. Will fail with a precondition violation if type
567+
/// doesn't match.
568+
///
569+
/// \param type: Source type.
570+
/// \return Object of type \ref verilog_chandle_typet
571+
inline const verilog_chandle_typet &to_verilog_chandle_type(const typet &type)
572+
{
573+
PRECONDITION(type.id() == ID_verilog_chandle);
574+
return static_cast<const verilog_chandle_typet &>(type);
575+
}
576+
577+
/// \copydoc to_chandle_type(const typet &)
578+
inline verilog_chandle_typet &to_verilog_chandle_type(typet &type)
579+
{
580+
PRECONDITION(type.id() == ID_verilog_chandle);
581+
return static_cast<verilog_chandle_typet &>(type);
582+
}
583+
547584
#endif

‎src/verilog/vtype.cpp

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -73,6 +73,11 @@ vtypet::vtypet(const typet &type)
7373
vtype = VERILOG_REAL;
7474
width = 32;
7575
}
76+
else if(type.id() == ID_verilog_chandle)
77+
{
78+
vtype = CHANDLE;
79+
width = 32;
80+
}
7681
else
7782
{
7883
width=0;
@@ -117,6 +122,12 @@ std::ostream &operator << (std::ostream &out, const vtypet &vtype)
117122
case vtypet::VERILOG_REAL:
118123
return out << "real";
119124

125+
case vtypet::CHANDLE:
126+
return out << "chandle";
127+
128+
case vtypet::NULL_TYPE:
129+
return out << "null";
130+
120131
case vtypet::UNKNOWN:
121132
case vtypet::OTHER:
122133
default:

‎src/verilog/vtype.h

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,14 @@ class vtypet
3131
{
3232
return vtype == VERILOG_REAL;
3333
}
34+
bool is_chandle() const
35+
{
36+
return vtype == CHANDLE;
37+
}
38+
bool is_null() const
39+
{
40+
return vtype == NULL_TYPE;
41+
}
3442
inline bool is_other() const { return vtype==OTHER; }
3543

3644
protected:
@@ -44,6 +52,8 @@ class vtypet
4452
VERILOG_SIGNED,
4553
VERILOG_UNSIGNED,
4654
VERILOG_REAL,
55+
CHANDLE,
56+
NULL_TYPE,
4757
OTHER
4858
} _vtypet;
4959
_vtypet vtype;

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