place_and_route: Added rules and providers to handle SDC files

Signed-off-by: Jan Bylicki <[email protected]>

Author: jbylicki

pdk/open_road_configuration.bzl

@@ -117,8 +117,7 @@ open_road_pdk_configuration = rule(
             mandatory = True,
             doc = "This value can be an empty list if all cells should be used in P&R",
         ),
-        "endcap_cell": attr.string(
-        ),
+        "endcap_cell": attr.string(),
         "fill_cells": attr.string_list(
             mandatory = True,
         ),
@@ -160,10 +159,8 @@ open_road_pdk_configuration = rule(
         "rc_script_configuration": attr.label(
             allow_single_file = True,
         ),
-        "tap_cell": attr.string(
-        ),
-        "tapcell_distance": attr.int(
-        ),
+        "tap_cell": attr.string(),
+        "tapcell_distance": attr.int(),
         "tapcell_tcl": attr.label(
             allow_single_file = True,
             doc = "TCL file that sets tapcell options. This overrides other tapcell attributes in this rule.",

place_and_route/open_road.bzl

@@ -15,7 +15,7 @@
 """File encapsulating the open road command"""
 
 load("//pdk:open_road_configuration.bzl", "get_open_road_configuration")
-load("//synthesis:defs.bzl", "SynthesisInfo")
+load("//synthesis:defs.bzl", "SdcInfo", "SynthesisInfo")
 
 OpenRoadInfo = provider(
     "Provider to support running openroad outside of bazel",
@@ -100,7 +100,9 @@ def clock_commands(ctx):
     Returns:
         Struct with params inputs and commands. Both return values are lists.
     """
-    sdc = ctx.file.sdc
+    sdc = None
+    if SdcInfo in ctx.attr.sdc:
+        sdc = ctx.attr.sdc[SdcInfo].sdc.files.to_list()[0]
 
     if sdc:
         return struct(inputs = [sdc], commands = ["read_sdc {}".format(sdc.path)])

synthesis/build_defs.bzl

@@ -443,3 +443,31 @@ Example:
     attrs = benchmark_synth_attrs,
     executable = True,
 )
+
+SdcInfo = provider(
+    doc = "sdc",
+    fields = {
+        "sdc": "Path to the SDC file",
+    },
+)
+
+def _sdc_library_impl(ctx):
+    return [
+        DefaultInfo(
+            files = depset(transitive = [t.files for t in ctx.attr.srcs]),
+        ),
+        SdcInfo(
+            sdc = ctx.attr.srcs[0],
+        ),
+    ]
+
+sdc_library = rule(
+    doc = "Define an SDC library.",
+    implementation = _sdc_library_impl,
+    attrs = {
+        "srcs": attr.label_list(
+            doc = "SDC sources.",
+            allow_files = [".sdc"],
+        ),
+    },
+)

synthesis/defs.bzl

@@ -3,9 +3,11 @@
 load(
     ":build_defs.bzl",
     _ExternalSynthesisInfo = "ExternalSynthesisInfo",
+    _SdcInfo = "SdcInfo",
     _SynthesisInfo = "SynthesisInfo",
     _UhdmInfo = "UhdmInfo",
     _benchmark_synth = "benchmark_synth",
+    _sdc_library = "sdc_library",
     _synthesis_binary = "synthesis_binary",
     _synthesize_rtl = "synthesize_rtl",
 )
@@ -16,3 +18,5 @@ synthesis_binary = _synthesis_binary
 SynthesisInfo = _SynthesisInfo
 synthesize_rtl = _synthesize_rtl
 UhdmInfo = _UhdmInfo
+SdcInfo = _SdcInfo
+sdc_library = _sdc_library

tests/BUILD

@@ -19,7 +19,7 @@ load("//flows:basic_asic.bzl", "basic_asic_flow")
 load("//gds_write:build_defs.bzl", "gds_write")
 load("//place_and_route:build_defs.bzl", "place_and_route")
 load("//static_timing:build_defs.bzl", "run_opensta")
-load("//synthesis:defs.bzl", "synthesize_rtl")
+load("//synthesis:defs.bzl", "sdc_library", "synthesize_rtl")
 load("//verilog:defs.bzl", "verilog_library")
 
 package(
@@ -78,14 +78,19 @@ place_and_route(
     synthesized_rtl = ":verilog_adder-synth",
 )
 
+sdc_library(
+    name = "constraint",
+    srcs = ["constraint.sdc"],
+)
+
 place_and_route(
     name = "verilog_counter-place_and_route",
     clock_period = "10",
     core_padding_microns = 20,
     die_height_microns = 200,
     die_width_microns = 200,
     placement_density = "0.7",
-    sdc = "constraint.sdc",
+    sdc = ":constraint",
     synthesized_rtl = ":verilog_counter-synth",
 )