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urishurish
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ol2/tt_autosel: add tt_autosel macro
allows selecting a design automatically by reading its the selected design id from an external I2C EEPROM
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‎ol2/tt_autosel/.gitignore

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fpga/impl
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runs
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failures_report.json

‎ol2/tt_autosel/config.json

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{
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"DESIGN_NAME": "tt_autosel",
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"VERILOG_FILES": ["dir::tt_autosel.v", "dir::i2c_eeprom.v", "dir::i2c_master.v"],
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"FP_SIZING": "absolute",
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"DIE_AREA": "0 0 250 80",
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"FP_IO_HLENGTH": 2,
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"FP_IO_VLENGTH": 2,
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"//": "use alternative efabless decap cells to solve LI density issue",
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"DECAP_CELL": "sky130_fd_sc_hd__decap_3 sky130_fd_sc_hd__decap_4 sky130_fd_sc_hd__decap_6 sky130_fd_sc_hd__decap_8 sky130_ef_sc_hd__decap_12",
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"//": "period is in ns, so 20ns == 50mHz",
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"CLOCK_PERIOD": 20,
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"CLOCK_PORT": "clk",
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"//": "don't use power rings or met5",
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"DESIGN_IS_CORE": false,
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"RT_MAX_LAYER": "met4",
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"//": "make the PDN denser",
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"FP_PDN_VOFFSET": 20.355,
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"FP_PDN_VPITCH": 40.710,
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"//": "save some time",
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"RUN_KLAYOUT_XOR": false,
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"//": "reduce wasted space",
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"TOP_MARGIN_MULT": 1,
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"BOTTOM_MARGIN_MULT": 1,
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"LEFT_MARGIN_MULT": 8,
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"RIGHT_MARGIN_MULT": 8
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}

‎ol2/tt_autosel/fpga/Makefile

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SOURCE_FILES = project.v uart_tx.v ../i2c_master.v ../i2c_eeprom.v ../tt_autosel.v
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TARGET = impl/pnr/project.fs
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GW_SH = $(GOWIN_HOME)/IDE/bin/gw_sh
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$(TARGET): $(SOURCE_FILES)
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$(GW_SH) project.tcl
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.PHONY: all
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all: $(TARGET)
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.PHONY: sram
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sram: $(TARGET)
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openFPGALoader $(TARGET)
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.PHONY: flash
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flash: $(TARGET)
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openFPGALoader -f $(TARGET)
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.PHONY: clean
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clean:
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rm -rf impl

‎ol2/tt_autosel/fpga/README.md

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# Tang Nano 20K Testbench
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FPGA Board: [Tang Nano 20K](https://wiki.sipeed.com/hardware/en/tang/tang-nano-20k/nano-20k.html).
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You need to connect a 1 kbit or 2 kbit I2C EEPROM (e.g. 24C01 or 24C02), program the selected design id into the first two bytes of the EEPROM memory, and connect the EEPROM to the Tang Nano 20K board. After connecting the EEPROM, press the reset button (S1), and observe the ctrl output pins to see if the design id is correctly read from the EEPROM:
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- `ctrl_sel_rst_n` should go low, and then high
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- `ctrl_sel_inc` should pulse high according to the lowest 10 bits of the number stored in the EEPROM
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- `ctrl_ena` should go high
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## Pinout
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| Tang Nano 20K | Function |
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|---------------|----------------|
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| 74 | SDA |
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| 77 | SCL |
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| 27 | ctrl_sel_rst_n |
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| 28 | ctrl_sel_inc |
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| 25 | ctrl_ena |
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## Debug interface
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The test project also implements a UART debug interface (115200 baud, connected through the BL616). The debug interface will print the two bytes read from the EEPROM as a 16-bit hex number (big endian) once per second.

‎ol2/tt_autosel/fpga/project.cst

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# Clock & Reset
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IO_LOC "clk" 4;
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IO_PORT "clk" PULL_MODE=UP BANK_VCCIO=1.8;
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IO_LOC "rst" 88;
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IO_PORT "rst" IO_TYPE=LVCMOS33 PULL_MODE=UP;
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# Debug
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IO_LOC "led" 15;
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IO_PORT "led" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
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IO_LOC "uart_tx" 69;
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IO_PORT "uart_tx" IO_TYPE=LVCMOS33;
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# I2C
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IO_LOC "i2c_sda" 74;
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IO_PORT "i2c_sda" IO_TYPE=LVCMOS33 PULL_MODE=UP;
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IO_LOC "i2c_scl" 77;
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IO_PORT "i2c_scl" IO_TYPE=LVCMOS33 PULL_MODE=UP;
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# Mux controller
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IO_LOC "ctrl_sel_rst_n" 27;
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IO_PORT "ctrl_sel_rst_n" IO_TYPE=LVCMOS33;
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IO_LOC "ctrl_sel_inc" 28;
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IO_PORT "ctrl_sel_inc" IO_TYPE=LVCMOS33;
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IO_LOC "ctrl_ena" 25;
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IO_PORT "ctrl_ena" IO_TYPE=LVCMOS33;

‎ol2/tt_autosel/fpga/project.sdc

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create_clock -name clk -period 37.037 -waveform {0 18.518} [get_ports {clk}]

‎ol2/tt_autosel/fpga/project.tcl

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add_file -type verilog project.v
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add_file -type verilog ../i2c_master.v
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add_file -type verilog ../i2c_eeprom.v
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add_file -type verilog ../tt_autosel.v
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add_file -type verilog uart_tx.v
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add_file -type cst project.cst
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add_file -type sdc project.sdc
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set_device GW2AR-LV18QN88C8/I7
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set_option -synthesis_tool gowinsynthesis
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set_option -output_base_name project
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set_option -verilog_std sysv2017
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set_option -top_module fpga_top
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run all

‎ol2/tt_autosel/fpga/project.v

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`default_nettype none
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// Enables the eeprom_data debug output of tt_autosel:
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`define DEBUG_AUTOSEL
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module fpga_top (
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input wire clk,
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input wire rst,
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output reg led,
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output wire uart_tx,
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inout wire i2c_scl,
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inout wire i2c_sda,
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output wire ctrl_sel_rst_n,
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output wire ctrl_sel_inc,
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output wire ctrl_ena
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);
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parameter CLK_FREQ = 27; // Mhz
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parameter UART_BAUD = 115200; // Khz
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reg [31:0] counter = 0;
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wire scl_i;
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wire scl_o;
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wire scl_oe_n;
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IOBUF scl_buf (
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.O (scl_i),
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.IO (i2c_scl),
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.I (scl_o),
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.OEN(scl_oe_n)
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);
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wire sda_i;
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wire sda_o;
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wire sda_oe_n;
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IOBUF sda_buf (
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.O (sda_i),
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.IO (i2c_sda),
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.I (sda_o),
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.OEN(sda_oe_n)
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);
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// --
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wire [15:0] eeprom_data;
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tt_autosel autosel (
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.clk (clk),
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.rst_n(rst_n),
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.eeprom_data(eeprom_data),
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// I2C master interface
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.scl_i(scl_i),
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.sda_i(sda_i),
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.scl_o(scl_o),
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.scl_oe_n(scl_oe_n),
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.sda_o(sda_o),
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.sda_oe_n(sda_oe_n),
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// Mux ctrl interface
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.ctrl_sel_rst_n(ctrl_sel_rst_n),
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.ctrl_sel_inc(ctrl_sel_inc),
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.ctrl_ena(ctrl_ena)
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);
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// --
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wire rst_n = ~rst;
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wire tx_ready;
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reg [7:0] tx_byte;
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reg tx_valid;
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uart_tx #(
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.CLK_FRE (CLK_FREQ),
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.BAUD_RATE(UART_BAUD)
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) uart_tx_inst (
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.clk(clk),
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.rst_n(rst_n),
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.tx_pin(uart_tx),
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.tx_data(tx_byte),
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.tx_data_valid(tx_valid),
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.tx_data_ready(tx_ready)
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);
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reg [2:0] send_index = 0;
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function [7:0] hexchar(input [3:0] value);
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case (value)
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0: hexchar = "0";
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1: hexchar = "1";
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2: hexchar = "2";
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3: hexchar = "3";
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4: hexchar = "4";
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5: hexchar = "5";
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6: hexchar = "6";
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7: hexchar = "7";
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8: hexchar = "8";
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9: hexchar = "9";
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10: hexchar = "A";
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11: hexchar = "B";
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12: hexchar = "C";
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13: hexchar = "D";
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14: hexchar = "E";
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15: hexchar = "F";
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endcase
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endfunction
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/* Send a byte every 1 second */
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always @(posedge clk) begin
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if (counter == 27000000) begin
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send_index <= 0;
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end else if (tx_ready) begin
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case (send_index)
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0: tx_byte <= hexchar(eeprom_data[15:12]);
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1: tx_byte <= hexchar(eeprom_data[11:8]);
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2: tx_byte <= hexchar(eeprom_data[7:4]);
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3: tx_byte <= hexchar(eeprom_data[3:0]);
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4: tx_byte <= 13; // CR
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5: tx_byte <= 10; // LF
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endcase
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if (send_index < 6) begin
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tx_valid <= 1;
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send_index <= send_index + 1;
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end else begin
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tx_valid <= 0;
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end
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end
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end
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always @(posedge clk) begin
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counter <= counter + 1;
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if (counter == 27000000) begin
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counter <= 0;
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led <= ~led;
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end
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end
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endmodule

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