Performance Testing? (for t3h lulz)

[sajattack]

I thought it might be fun(ny) to do some benchmarks on this core. Here are a few possible options https://github.com/sifive/benchmark-coremark https://github.com/riscv/riscv-tests/tree/master/benchmarks

[cyrozap]

You joke, but I actually intend to do something like this at some point. It would be really nice if we could track performance per-commit, to see how the performance is improving or regressing over time. And for finding the areas that need improvement, I'd like to be able to measure the number of 8051 instructions executed for each RISC-V instruction, since that should be straightforward to measure and would provide an implementation-independent way to predict the performance impact of the emulator. For instance, if you know your single-cycle 8051 runs at 80 MHz, and each RISC-V instruction takes between 50 and 150 8051 instructions to execute, then emulating some RISC-V code on that 8051 core would have similar performance to executing that same code natively on a 533-1600 kHz single-cycle RISC-V core.

[owlshrimp]

Just wanted to drop by and say this project is absolutely amazing and I wish you all the success with it! I would love to be able to write and upload rust code onto old 8051 chips. I think that it would be super cool, though I'm sure there are lots of other more practical use cases (like writing rust firmware for 8051-based laptop ECs).

[jefftrull]

I've managed to put some of the puzzle pieces together for benchmarking and have it working for a handful of the RISCV benchmarks. LMK what you think: https://github.com/jefftrull/riscv-tests-cyrozap/tree/benchmark-via-s51